Blackfin arch: Fix bug - Kernel does not boot if re-program clocks
Don't write conflicting data to EBIU_SDBCTL after the SDRAM is configured. This can cause data corruption, since we might change SDRAM row and column addressing modes. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Michael Hennerich
Bryan Wu
Родитель
260d5d3517
Коммит
68e2fc78e5
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@ -315,20 +315,6 @@ config MEM_SIZE
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depends on BFIN_KERNEL_CLOCK
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default 64
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config MEM_ADD_WIDTH
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int "Memory Address Width"
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depends on BFIN_KERNEL_CLOCK
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depends on (!BF54x)
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range 8 11
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default 9 if BFIN533_EZKIT
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default 9 if BFIN561_EZKIT
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default 9 if H8606_HVSISTEMAS
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default 10 if BFIN527_EZKIT
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default 10 if BFIN537_STAMP
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default 11 if BFIN533_STAMP
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default 10 if PNAV10
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default 10 if BFIN532_IP0X
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config PLL_BYPASS
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bool "Bypass PLL"
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depends on BFIN_KERNEL_CLOCK
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@ -32,7 +32,7 @@
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#include <asm/blackfin.h>
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#include <asm/trace.h>
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#if CONFIG_BFIN_KERNEL_CLOCK
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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#include <asm/mach-common/clocks.h>
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#include <asm/mach/mem_init.h>
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#endif
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@ -185,7 +185,7 @@ ENTRY(__start)
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/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
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call _bf53x_relocate_l1_mem;
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#if CONFIG_BFIN_KERNEL_CLOCK
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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call _start_dma_code;
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#endif
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@ -318,7 +318,7 @@ ENDPROC(_real_start)
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__FINIT
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.section .l1.text
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#if CONFIG_BFIN_KERNEL_CLOCK
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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ENTRY(_start_dma_code)
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/* Enable PHY CLK buffer output */
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@ -398,12 +398,6 @@ ENTRY(_start_dma_code)
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w[p0] = r0.l;
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ssync;
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p0.l = LO(EBIU_SDBCTL);
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p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
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r0 = mem_SDBCTL;
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w[p0] = r0.l;
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ssync;
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P2.H = hi(EBIU_SDGCTL);
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P2.L = lo(EBIU_SDGCTL);
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R0 = [P2];
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@ -31,7 +31,7 @@
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#include <linux/init.h>
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#include <asm/blackfin.h>
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#include <asm/trace.h>
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#if CONFIG_BFIN_KERNEL_CLOCK
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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#include <asm/mach-common/clocks.h>
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#include <asm/mach/mem_init.h>
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#endif
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@ -186,7 +186,7 @@ ENTRY(__start)
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/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
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call _bf53x_relocate_l1_mem;
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#if CONFIG_BFIN_KERNEL_CLOCK
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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call _start_dma_code;
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#endif
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@ -319,7 +319,7 @@ ENDPROC(_real_start)
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__FINIT
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.section .l1.text
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#if CONFIG_BFIN_KERNEL_CLOCK
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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ENTRY(_start_dma_code)
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p0.h = hi(SIC_IWR);
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p0.l = lo(SIC_IWR);
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@ -390,12 +390,6 @@ ENTRY(_start_dma_code)
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w[p0] = r0.l;
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ssync;
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p0.l = LO(EBIU_SDBCTL);
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p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
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r0 = mem_SDBCTL;
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w[p0] = r0.l;
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ssync;
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P2.H = hi(EBIU_SDGCTL);
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P2.L = lo(EBIU_SDGCTL);
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R0 = [P2];
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@ -32,7 +32,7 @@
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#include <asm/blackfin.h>
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#include <asm/trace.h>
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#if CONFIG_BFIN_KERNEL_CLOCK
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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#include <asm/mach-common/clocks.h>
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#include <asm/mach/mem_init.h>
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#endif
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@ -217,7 +217,7 @@ ENTRY(__start)
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/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
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call _bf53x_relocate_l1_mem;
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#if CONFIG_BFIN_KERNEL_CLOCK
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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call _start_dma_code;
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#endif
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@ -350,7 +350,7 @@ ENDPROC(_real_start)
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__FINIT
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.section .l1.text
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#if CONFIG_BFIN_KERNEL_CLOCK
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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ENTRY(_start_dma_code)
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/* Enable PHY CLK buffer output */
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@ -430,12 +430,6 @@ ENTRY(_start_dma_code)
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w[p0] = r0.l;
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ssync;
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p0.l = LO(EBIU_SDBCTL);
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p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
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r0 = mem_SDBCTL;
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w[p0] = r0.l;
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ssync;
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P2.H = hi(EBIU_SDGCTL);
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P2.L = lo(EBIU_SDGCTL);
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R0 = [P2];
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@ -31,7 +31,7 @@
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#include <linux/init.h>
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#include <asm/blackfin.h>
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#include <asm/trace.h>
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#if CONFIG_BFIN_KERNEL_CLOCK
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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#include <asm/mach-common/clocks.h>
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#include <asm/mach/mem_init.h>
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#endif
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@ -130,7 +130,7 @@ ENTRY(__start)
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/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
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call _bf53x_relocate_l1_mem;
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#if CONFIG_BFIN_KERNEL_CLOCK
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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call _start_dma_code;
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#endif
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/* Code for initializing Async memory banks */
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@ -288,7 +288,7 @@ ENDPROC(_real_start)
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__FINIT
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.section .l1.text
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#if CONFIG_BFIN_KERNEL_CLOCK
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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ENTRY(_start_dma_code)
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/* Enable PHY CLK buffer output */
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@ -377,12 +377,6 @@ ENTRY(_start_dma_code)
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w[p0] = r0.l;
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ssync;
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p0.l = LO(EBIU_SDBCTL);
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p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
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r0 = mem_SDBCTL;
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w[p0] = r0.l;
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ssync;
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P2.H = hi(EBIU_SDGCTL);
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P2.L = lo(EBIU_SDGCTL);
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R0 = [P2];
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@ -146,33 +146,6 @@
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#define SDRAM_CL CL_3
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#endif
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#if (CONFIG_MEM_SIZE == 128)
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#define SDRAM_SIZE EBSZ_128
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#endif
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#if (CONFIG_MEM_SIZE == 64)
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#define SDRAM_SIZE EBSZ_64
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#endif
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#if (CONFIG_MEM_SIZE == 32)
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#define SDRAM_SIZE EBSZ_32
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#endif
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#if (CONFIG_MEM_SIZE == 16)
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#define SDRAM_SIZE EBSZ_16
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 11)
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#define SDRAM_WIDTH EBCAW_11
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 10)
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#define SDRAM_WIDTH EBCAW_10
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 9)
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#define SDRAM_WIDTH EBCAW_9
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 8)
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#define SDRAM_WIDTH EBCAW_8
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#endif
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#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
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/* Equation from section 17 (p17-46) of BF533 HRM */
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#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
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@ -133,33 +133,6 @@
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#define SDRAM_CL CL_3
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#endif
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#if (CONFIG_MEM_SIZE == 128)
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#define SDRAM_SIZE EBSZ_128
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#endif
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#if (CONFIG_MEM_SIZE == 64)
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#define SDRAM_SIZE EBSZ_64
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#endif
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#if (CONFIG_MEM_SIZE == 32)
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#define SDRAM_SIZE EBSZ_32
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#endif
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#if (CONFIG_MEM_SIZE == 16)
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#define SDRAM_SIZE EBSZ_16
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 11)
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#define SDRAM_WIDTH EBCAW_11
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 10)
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#define SDRAM_WIDTH EBCAW_10
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 9)
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#define SDRAM_WIDTH EBCAW_9
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 8)
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#define SDRAM_WIDTH EBCAW_8
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#endif
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#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
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/* Equation from section 17 (p17-46) of BF533 HRM */
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#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
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@ -139,33 +139,6 @@
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#define SDRAM_CL CL_3
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#endif
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#if (CONFIG_MEM_SIZE == 128)
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#define SDRAM_SIZE EBSZ_128
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#endif
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#if (CONFIG_MEM_SIZE == 64)
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#define SDRAM_SIZE EBSZ_64
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#endif
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#if (CONFIG_MEM_SIZE == 32)
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#define SDRAM_SIZE EBSZ_32
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#endif
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#if (CONFIG_MEM_SIZE == 16)
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#define SDRAM_SIZE EBSZ_16
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 11)
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#define SDRAM_WIDTH EBCAW_11
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 10)
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#define SDRAM_WIDTH EBCAW_10
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 9)
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#define SDRAM_WIDTH EBCAW_9
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 8)
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#define SDRAM_WIDTH EBCAW_8
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#endif
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#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
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/* Equation from section 17 (p17-46) of BF533 HRM */
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#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
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@ -131,33 +131,6 @@
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#define SDRAM_CL CL_3
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#endif
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#if (CONFIG_MEM_SIZE == 128)
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#define SDRAM_SIZE EB0_SZ_128
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#endif
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#if (CONFIG_MEM_SIZE == 64)
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#define SDRAM_SIZE EB0_SZ_64
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#endif
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#if ( CONFIG_MEM_SIZE == 32)
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#define SDRAM_SIZE EB0_SZ_32
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#endif
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#if (CONFIG_MEM_SIZE == 16)
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#define SDRAM_SIZE EB0_SZ_16
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 11)
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#define SDRAM_WIDTH EB0_CAW_11
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 10)
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#define SDRAM_WIDTH EB0_CAW_10
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 9)
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#define SDRAM_WIDTH EB0_CAW_9
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#endif
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#if (CONFIG_MEM_ADD_WIDTH == 8)
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#define SDRAM_WIDTH EB0_CAW_8
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#endif
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#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EB0_E)
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/* Equation from section 17 (p17-46) of BF533 HRM */
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#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
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