CRIS v32: Update and simplify kernel/irq.c.
- First timer register has changed name to timer0. - Build IRQs with only IRQ number, mask bit will be calculated instead. - Add more IRQs, up to 64 supported. - Use arrays to hold which IRQs triggered instead of trying to do magic with two 32 bit values now that more than 32 IRQs are supported.
This commit is contained in:
Jesper Nilsson
Родитель
96e476697d
Коммит
693d9847b2
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@ -15,15 +15,21 @@
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#include <linux/threads.h>
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#include <linux/spinlock.h>
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#include <linux/kernel_stat.h>
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#include <asm/arch/hwregs/reg_map.h>
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#include <asm/arch/hwregs/reg_rdwr.h>
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#include <asm/arch/hwregs/intr_vect.h>
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#include <asm/arch/hwregs/intr_vect_defs.h>
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#include <hwregs/reg_map.h>
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#include <hwregs/reg_rdwr.h>
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#include <hwregs/intr_vect.h>
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#include <hwregs/intr_vect_defs.h>
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#define CPU_FIXED -1
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/* IRQ masks (refer to comment for crisv32_do_multiple) */
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#define TIMER_MASK (1 << (TIMER_INTR_VECT - FIRST_IRQ))
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#if TIMER0_INTR_VECT - FIRST_IRQ < 32
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#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ))
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#undef TIMER_VECT1
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#else
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#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ - 32))
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#define TIMER_VECT1
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#endif
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#ifdef CONFIG_ETRAX_KGDB
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#if defined(CONFIG_ETRAX_KGDB_PORT0)
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#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
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@ -44,8 +50,8 @@ struct cris_irq_allocation
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cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */
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};
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struct cris_irq_allocation irq_allocations[NR_IRQS] =
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{[0 ... NR_IRQS - 1] = {0, CPU_MASK_ALL}};
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struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] =
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{ [0 ... NR_REAL_IRQS - 1] = {0, CPU_MASK_ALL} };
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static unsigned long irq_regs[NR_CPUS] =
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{
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@ -55,6 +61,12 @@ static unsigned long irq_regs[NR_CPUS] =
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#endif
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};
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#if NR_REAL_IRQS > 32
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#define NBR_REGS 2
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#else
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#define NBR_REGS 1
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#endif
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unsigned long cpu_irq_counters[NR_CPUS];
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unsigned long irq_counters[NR_REAL_IRQS];
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@ -79,45 +91,81 @@ extern void d_mmu_write(void);
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extern void kgdb_init(void);
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extern void breakpoint(void);
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/* From traps.c. */
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extern void breakh_BUG(void);
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/*
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* Build the IRQ handler stubs using macros from irq.h. First argument is the
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* IRQ number, the second argument is the corresponding bit in
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* intr_rw_vect_mask found in asm/arch/hwregs/intr_vect_defs.h.
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* Build the IRQ handler stubs using macros from irq.h.
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*/
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BUILD_IRQ(0x31, (1 << 0)) /* memarb */
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BUILD_IRQ(0x32, (1 << 1)) /* gen_io */
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BUILD_IRQ(0x33, (1 << 2)) /* iop0 */
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BUILD_IRQ(0x34, (1 << 3)) /* iop1 */
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BUILD_IRQ(0x35, (1 << 4)) /* iop2 */
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BUILD_IRQ(0x36, (1 << 5)) /* iop3 */
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BUILD_IRQ(0x37, (1 << 6)) /* dma0 */
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BUILD_IRQ(0x38, (1 << 7)) /* dma1 */
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BUILD_IRQ(0x39, (1 << 8)) /* dma2 */
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BUILD_IRQ(0x3a, (1 << 9)) /* dma3 */
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BUILD_IRQ(0x3b, (1 << 10)) /* dma4 */
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BUILD_IRQ(0x3c, (1 << 11)) /* dma5 */
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BUILD_IRQ(0x3d, (1 << 12)) /* dma6 */
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BUILD_IRQ(0x3e, (1 << 13)) /* dma7 */
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BUILD_IRQ(0x3f, (1 << 14)) /* dma8 */
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BUILD_IRQ(0x40, (1 << 15)) /* dma9 */
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BUILD_IRQ(0x41, (1 << 16)) /* ata */
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BUILD_IRQ(0x42, (1 << 17)) /* sser0 */
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BUILD_IRQ(0x43, (1 << 18)) /* sser1 */
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BUILD_IRQ(0x44, (1 << 19)) /* ser0 */
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BUILD_IRQ(0x45, (1 << 20)) /* ser1 */
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BUILD_IRQ(0x46, (1 << 21)) /* ser2 */
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BUILD_IRQ(0x47, (1 << 22)) /* ser3 */
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BUILD_IRQ(0x48, (1 << 23))
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BUILD_IRQ(0x49, (1 << 24)) /* eth0 */
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BUILD_IRQ(0x4a, (1 << 25)) /* eth1 */
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BUILD_TIMER_IRQ(0x4b, (1 << 26))/* timer */
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BUILD_IRQ(0x4c, (1 << 27)) /* bif_arb */
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BUILD_IRQ(0x4d, (1 << 28)) /* bif_dma */
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BUILD_IRQ(0x4e, (1 << 29)) /* ext */
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BUILD_IRQ(0x4f, (1 << 29)) /* ipi */
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BUILD_IRQ(0x31)
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BUILD_IRQ(0x32)
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BUILD_IRQ(0x33)
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BUILD_IRQ(0x34)
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BUILD_IRQ(0x35)
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BUILD_IRQ(0x36)
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BUILD_IRQ(0x37)
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BUILD_IRQ(0x38)
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BUILD_IRQ(0x39)
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BUILD_IRQ(0x3a)
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BUILD_IRQ(0x3b)
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BUILD_IRQ(0x3c)
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BUILD_IRQ(0x3d)
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BUILD_IRQ(0x3e)
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BUILD_IRQ(0x3f)
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BUILD_IRQ(0x40)
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BUILD_IRQ(0x41)
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BUILD_IRQ(0x42)
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BUILD_IRQ(0x43)
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BUILD_IRQ(0x44)
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BUILD_IRQ(0x45)
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BUILD_IRQ(0x46)
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BUILD_IRQ(0x47)
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BUILD_IRQ(0x48)
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BUILD_IRQ(0x49)
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BUILD_IRQ(0x4a)
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BUILD_IRQ(0x4b)
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BUILD_IRQ(0x4c)
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BUILD_IRQ(0x4d)
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BUILD_IRQ(0x4e)
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BUILD_IRQ(0x4f)
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BUILD_IRQ(0x50)
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#if MACH_IRQS > 32
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BUILD_IRQ(0x51)
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BUILD_IRQ(0x52)
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BUILD_IRQ(0x53)
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BUILD_IRQ(0x54)
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BUILD_IRQ(0x55)
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BUILD_IRQ(0x56)
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BUILD_IRQ(0x57)
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BUILD_IRQ(0x58)
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BUILD_IRQ(0x59)
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BUILD_IRQ(0x5a)
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BUILD_IRQ(0x5b)
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BUILD_IRQ(0x5c)
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BUILD_IRQ(0x5d)
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BUILD_IRQ(0x5e)
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BUILD_IRQ(0x5f)
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BUILD_IRQ(0x60)
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BUILD_IRQ(0x61)
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BUILD_IRQ(0x62)
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BUILD_IRQ(0x63)
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BUILD_IRQ(0x64)
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BUILD_IRQ(0x65)
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BUILD_IRQ(0x66)
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BUILD_IRQ(0x67)
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BUILD_IRQ(0x68)
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BUILD_IRQ(0x69)
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BUILD_IRQ(0x6a)
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BUILD_IRQ(0x6b)
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BUILD_IRQ(0x6c)
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BUILD_IRQ(0x6d)
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BUILD_IRQ(0x6e)
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BUILD_IRQ(0x6f)
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BUILD_IRQ(0x70)
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#endif
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/* Pointers to the low-level handlers. */
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static void (*interrupt[NR_IRQS])(void) = {
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static void (*interrupt[MACH_IRQS])(void) = {
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IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt,
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IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt,
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IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt,
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@ -128,7 +176,20 @@ static void (*interrupt[NR_IRQS])(void) = {
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IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt,
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IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt,
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IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt,
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IRQ0x4f_interrupt
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IRQ0x4f_interrupt, IRQ0x50_interrupt,
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#if MACH_IRQS > 32
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IRQ0x51_interrupt, IRQ0x52_interrupt, IRQ0x53_interrupt,
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IRQ0x54_interrupt, IRQ0x55_interrupt, IRQ0x56_interrupt,
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IRQ0x57_interrupt, IRQ0x58_interrupt, IRQ0x59_interrupt,
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IRQ0x5a_interrupt, IRQ0x5b_interrupt, IRQ0x5c_interrupt,
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IRQ0x5d_interrupt, IRQ0x5e_interrupt, IRQ0x5f_interrupt,
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IRQ0x60_interrupt, IRQ0x61_interrupt, IRQ0x62_interrupt,
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IRQ0x63_interrupt, IRQ0x64_interrupt, IRQ0x65_interrupt,
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IRQ0x66_interrupt, IRQ0x67_interrupt, IRQ0x68_interrupt,
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IRQ0x69_interrupt, IRQ0x6a_interrupt, IRQ0x6b_interrupt,
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IRQ0x6c_interrupt, IRQ0x6d_interrupt, IRQ0x6e_interrupt,
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IRQ0x6f_interrupt, IRQ0x70_interrupt,
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#endif
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};
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void
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@ -137,13 +198,26 @@ block_irq(int irq, int cpu)
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int intr_mask;
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unsigned long flags;
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spin_lock_irqsave(&irq_lock, flags);
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intr_mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
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spin_lock_irqsave(&irq_lock, flags);
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if (irq - FIRST_IRQ < 32)
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intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
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rw_mask, 0);
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else
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intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
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rw_mask, 1);
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/* Remember; 1 let through, 0 block. */
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intr_mask &= ~(1 << (irq - FIRST_IRQ));
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/* Remember; 1 let thru, 0 block. */
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if (irq - FIRST_IRQ < 32)
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intr_mask &= ~(1 << (irq - FIRST_IRQ));
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else
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intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));
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REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, intr_mask);
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if (irq - FIRST_IRQ < 32)
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REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
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0, intr_mask);
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else
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REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
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1, intr_mask);
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spin_unlock_irqrestore(&irq_lock, flags);
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}
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@ -154,12 +228,26 @@ unblock_irq(int irq, int cpu)
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unsigned long flags;
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spin_lock_irqsave(&irq_lock, flags);
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intr_mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
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if (irq - FIRST_IRQ < 32)
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intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
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rw_mask, 0);
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else
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intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
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rw_mask, 1);
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/* Remember; 1 let through, 0 block. */
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intr_mask |= (1 << (irq - FIRST_IRQ));
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/* Remember; 1 let thru, 0 block. */
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if (irq - FIRST_IRQ < 32)
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intr_mask |= (1 << (irq - FIRST_IRQ));
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else
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intr_mask |= (1 << (irq - FIRST_IRQ - 32));
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if (irq - FIRST_IRQ < 32)
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REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
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0, intr_mask);
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else
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REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
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1, intr_mask);
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REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, intr_mask);
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spin_unlock_irqrestore(&irq_lock, flags);
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}
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@ -298,8 +386,9 @@ crisv32_do_multiple(struct pt_regs* regs)
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{
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int cpu;
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int mask;
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int masked;
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int masked[NBR_REGS];
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int bit;
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int i;
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cpu = smp_processor_id();
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@ -308,42 +397,59 @@ crisv32_do_multiple(struct pt_regs* regs)
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*/
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irq_enter();
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/* Get which IRQs that happened. */
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masked = REG_RD_INT(intr_vect, irq_regs[cpu], r_masked_vect);
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for (i = 0; i < NBR_REGS; i++) {
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/* Get which IRQs that happend. */
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masked[i] = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
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r_masked_vect, i);
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/* Calculate new IRQ mask with these IRQs disabled. */
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mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
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mask &= ~masked;
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/* Calculate new IRQ mask with these IRQs disabled. */
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mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
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mask &= ~masked[i];
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/* Timer IRQ is never masked */
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if (masked & TIMER_MASK)
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mask |= TIMER_MASK;
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/* Block all the IRQs */
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REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, mask);
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#ifdef TIMER_VECT1
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if ((i == 1) && (masked[0] & TIMER_MASK))
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mask |= TIMER_MASK;
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#else
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if ((i == 0) && (masked[0] & TIMER_MASK))
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mask |= TIMER_MASK;
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#endif
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/* Block all the IRQs */
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REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
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/* Check for timer IRQ and handle it special. */
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if (masked & TIMER_MASK) {
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masked &= ~TIMER_MASK;
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do_IRQ(TIMER_INTR_VECT, regs);
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#ifdef TIMER_VECT1
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if ((i == 1) && (masked[i] & TIMER_MASK)) {
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masked[i] &= ~TIMER_MASK;
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do_IRQ(TIMER0_INTR_VECT, regs);
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}
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#else
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if ((i == 0) && (masked[i] & TIMER_MASK)) {
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masked[i] &= ~TIMER_MASK;
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do_IRQ(TIMER0_INTR_VECT, regs);
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}
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}
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#endif
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#ifdef IGNORE_MASK
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/* Remove IRQs that can't be handled as multiple. */
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masked &= ~IGNORE_MASK;
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masked[0] &= ~IGNORE_MASK;
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#endif
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/* Handle the rest of the IRQs. */
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for (bit = 0; bit < 32; bit++)
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{
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if (masked & (1 << bit))
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do_IRQ(bit + FIRST_IRQ, regs);
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for (i = 0; i < NBR_REGS; i++) {
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for (bit = 0; bit < 32; bit++) {
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if (masked[i] & (1 << bit))
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do_IRQ(bit + FIRST_IRQ + i*32, regs);
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}
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}
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/* Unblock all the IRQs. */
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mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
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mask |= masked;
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REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, mask);
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for (i = 0; i < NBR_REGS; i++) {
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mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
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mask |= masked[i];
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REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
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}
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/* This irq_exit() will trigger the soft IRQs. */
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irq_exit();
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@ -361,20 +467,21 @@ init_IRQ(void)
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reg_intr_vect_rw_mask vect_mask = {0};
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/* Clear all interrupts masks. */
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REG_WR(intr_vect, regi_irq, rw_mask, vect_mask);
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for (i = 0; i < NBR_REGS; i++)
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REG_WR_VECT(intr_vect, regi_irq, rw_mask, i, vect_mask);
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for (i = 0; i < 256; i++)
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etrax_irv->v[i] = weird_irq;
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/* Point all IRQs to bad handlers. */
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/* Point all IRQ's to bad handlers. */
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for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
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irq_desc[j].chip = &crisv32_irq_type;
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set_exception_vector(i, interrupt[j]);
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}
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/* Mark Timer and IPI IRQs as CPU local */
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irq_allocations[TIMER_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
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irq_desc[TIMER_INTR_VECT].status |= IRQ_PER_CPU;
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irq_allocations[TIMER0_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
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irq_desc[TIMER0_INTR_VECT].status |= IRQ_PER_CPU;
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irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
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irq_desc[IPI_INTR_VECT].status |= IRQ_PER_CPU;
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@ -391,6 +498,11 @@ init_IRQ(void)
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set_exception_vector(0x0a, d_mmu_access);
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set_exception_vector(0x0b, d_mmu_write);
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#ifdef CONFIG_BUG
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/* Break 14 handler, used to implement cheap BUG(). */
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set_exception_vector(0x1e, breakh_BUG);
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#endif
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/* The system-call trap is reached by "break 13". */
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set_exception_vector(0x1d, system_call);
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