SoC code updates for 6.2
This time there are only fairly minor cleanups across the i.MX, ixp4xx, ux500 and renesas platforms. The only notable update is a change to the keystone2 platform to switch switch it over to standard PSCI SMP bringup, which apparently was present in the shipped firmware almost from the start. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmOSBHgACgkQmmx57+YA GNlcdRAAhqal26vFBBLX6b6xbT8+1Wsfrgyzviz8wJAn0HF+fuYuyyUK6SEKwFA7 WUrFgM3CJg3cb1kVIT8cTzvPzLZUukCMNGcfpYN9ZyTOOTfpQP+aF9bsFkPHjAVT AMpxcn1F6n720CjIu8SRHOFWq/BJ7DwP8lfP8PkqkoMtKUWLsjbbh1Mi2g5q5E5t hPrTFppejYkFPKJwBCfWeTrwQlUM8ubg8YLHA2H21rkOdMroukZIXxrJupG/vek3 o043jpXz6eTp4tRAdVoVNBeivFzj288Zl2UO3ucHE/uCKSr8hpakM4FqGWuHofoy 8bfsnFN7KbZVEgkXODqmC1WlAuElSj7Ya7a+Q4xkM1B4uW543pTfpBNNMV8r95/g vjRMO32WuRku++zMQdhaAhA3acF8YQ2kcQkQ/bEIl3i8N8uNqSUdKEY7K3d6BVvL 8kQSD7w0xj2y9zQH6VsoPi8qRR83S6EyuNTpqYFDSv0MrmQm+x257uCbv+iYuiQ4 UzGTtlCy/Ec+Wvm5SL6SHOlKa8U9RX58GKLWhoDlrFCv/IcRme6RPAKpOaDwRgZQ RBPCXSydi2a2a+MpcHeNm2j79pdvcH/KORg0b+4xzZwgODjhM8oTLZDshmR1Ttfh edJoe8c66H2cXjic60pmnweessIJiMnzrvXFC2kUUoqZ4+nQTGY= =4VVl -----END PGP SIGNATURE----- Merge tag 'soc-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC code updates from Arnd Bergmann: "This time there are only fairly minor cleanups across the i.MX, ixp4xx, ux500 and renesas platforms. The only notable update is a change to the keystone2 platform to switch switch it over to standard PSCI SMP bringup, which apparently was present in the shipped firmware almost from the start" * tag 'soc-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: ARM: ixp4xx: Remove unused debug iomap MAINTAINERS: Add DHCOR to the DH electronic i.MX6 board support ARM: ixp4xx: Remove unused static map MAINTAINERS: adjust ARM/INTEL IXP4XX ARM ARCHITECTURE to ixp4xx clean-up ARM: imx3: Remove unneeded #include <linux/pinctrl/machine.h> ARM: mxs: Remove unneeded #include <linux/pinctrl/consumer.h> riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option ARM: ux500: Drop unused register file ARM: ux500: do not directly dereference __iomem arm/mach-ux500: fix repeated words in comments arm64: renesas: Drop selecting GPIOLIB and PINCTRL ARM: shmobile: Drop selecting GPIOLIB and PINCTRL ARM: keystone: Replace platform SMP with PSCI soc: renesas: Kconfig: Explicitly select GPIOLIB and PINCTRL config under SOC_RENESAS
This commit is contained in:
Linus Torvalds
Коммит
69700db421
|
|
@ -2282,8 +2282,6 @@ F: drivers/clocksource/timer-ixp4xx.c
|
|||
F: drivers/crypto/ixp4xx_crypto.c
|
||||
F: drivers/gpio/gpio-ixp4xx.c
|
||||
F: drivers/irqchip/irq-ixp4xx.c
|
||||
F: include/linux/irqchip/irq-ixp4xx.h
|
||||
F: include/linux/platform_data/timer-ixp4xx.h
|
||||
|
||||
ARM/INTEL KEEMBAY ARCHITECTURE
|
||||
M: Paul J. Murphy <paul.j.murphy@intel.com>
|
||||
|
|
@ -6039,11 +6037,12 @@ F: include/net/devlink.h
|
|||
F: include/uapi/linux/devlink.h
|
||||
F: net/core/devlink.c
|
||||
|
||||
DH ELECTRONICS IMX6 DHCOM BOARD SUPPORT
|
||||
DH ELECTRONICS IMX6 DHCOM/DHCOR BOARD SUPPORT
|
||||
M: Christoph Niedermaier <cniedermaier@dh-electronics.com>
|
||||
L: kernel@dh-electronics.com
|
||||
S: Maintained
|
||||
F: arch/arm/boot/dts/imx6*-dhcom-*
|
||||
F: arch/arm/boot/dts/imx6*-dhcor-*
|
||||
|
||||
DH ELECTRONICS STM32MP1 DHCOM/DHCOR BOARD SUPPORT
|
||||
M: Marek Vasut <marex@denx.de>
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
|
|
|||
|
|
@ -2,48 +2,7 @@
|
|||
/*
|
||||
* IXP4xx Device Tree boot support
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
/*
|
||||
* These are the only fixed phys to virt mappings we ever need
|
||||
* we put it right after the UART mapping at 0xffc80000-0xffc81fff
|
||||
*/
|
||||
#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000
|
||||
#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000
|
||||
|
||||
static struct map_desc ixp4xx_of_io_desc[] __initdata = {
|
||||
/*
|
||||
* This is needed for runtime system configuration checks,
|
||||
* such as reading if hardware so-and-so is present. This
|
||||
* could eventually be converted into a syscon once all boards
|
||||
* are converted to device tree.
|
||||
*/
|
||||
{
|
||||
.virtual = IXP4XX_EXP_CFG_BASE_VIRT,
|
||||
.pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
#ifdef CONFIG_DEBUG_UART_8250
|
||||
/* This is needed for LL-debug/earlyprintk/debug-macro.S */
|
||||
{
|
||||
.virtual = CONFIG_DEBUG_UART_VIRT,
|
||||
.pfn = __phys_to_pfn(CONFIG_DEBUG_UART_PHYS),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static void __init ixp4xx_of_map_io(void)
|
||||
{
|
||||
iotable_init(ixp4xx_of_io_desc, ARRAY_SIZE(ixp4xx_of_io_desc));
|
||||
}
|
||||
|
||||
/*
|
||||
* We handle 4 different SoC families. These compatible strings are enough
|
||||
|
|
@ -59,6 +18,5 @@ static const char *ixp4xx_of_board_compat[] = {
|
|||
};
|
||||
|
||||
DT_MACHINE_START(IXP4XX_DT, "IXP4xx (Device Tree)")
|
||||
.map_io = ixp4xx_of_map_io,
|
||||
.dt_compat = ixp4xx_of_board_compat,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
obj-y := keystone.o smc.o
|
||||
|
||||
obj-$(CONFIG_SMP) += platsmp.o
|
||||
obj-y := keystone.o
|
||||
|
||||
# PM domain driver for Keystone SOCs
|
||||
obj-$(CONFIG_ARCH_KEYSTONE) += pm_domain.o
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@
|
|||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/memory.h>
|
||||
|
||||
#include "memory.h"
|
||||
|
|
@ -103,7 +102,6 @@ DT_MACHINE_START(KEYSTONE, "Keystone")
|
|||
#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
|
||||
.dma_zone_size = SZ_2G,
|
||||
#endif
|
||||
.smp = smp_ops(keystone_smp_ops),
|
||||
.init_machine = keystone_init,
|
||||
.dt_compat = keystone_match,
|
||||
.pv_fixup = keystone_pv_fixup,
|
||||
|
|
|
|||
|
|
@ -8,13 +8,8 @@
|
|||
#ifndef __KEYSTONE_H__
|
||||
#define __KEYSTONE_H__
|
||||
|
||||
#define KEYSTONE_MON_CPU_UP_IDX 0x00
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
extern const struct smp_operations keystone_smp_ops;
|
||||
extern void secondary_startup(void);
|
||||
extern u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr);
|
||||
extern int keystone_pm_runtime_init(void);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
|
|
|||
|
|
@ -1,41 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Keystone SOC SMP platform code
|
||||
*
|
||||
* Copyright 2013 Texas Instruments, Inc.
|
||||
* Cyril Chemparathy <cyril@ti.com>
|
||||
* Santosh Shilimkar <santosh.shillimkar@ti.com>
|
||||
*
|
||||
* Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/pgtable.h>
|
||||
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
#include "keystone.h"
|
||||
|
||||
static int keystone_smp_boot_secondary(unsigned int cpu,
|
||||
struct task_struct *idle)
|
||||
{
|
||||
unsigned long start = virt_to_idmap(&secondary_startup);
|
||||
int error;
|
||||
|
||||
pr_debug("keystone-smp: booting cpu %d, vector %08lx\n",
|
||||
cpu, start);
|
||||
|
||||
error = keystone_cpu_smc(KEYSTONE_MON_CPU_UP_IDX, cpu, start);
|
||||
if (error)
|
||||
pr_err("CPU %d bringup failed with %d\n", cpu, error);
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
const struct smp_operations keystone_smp_ops __initconst = {
|
||||
.smp_boot_secondary = keystone_smp_boot_secondary,
|
||||
};
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Keystone Secure APIs
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
/**
|
||||
* u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr)
|
||||
*
|
||||
* Low level CPU monitor API
|
||||
* @command: Monitor command.
|
||||
* @cpu: CPU Number
|
||||
* @addr: Kernel jump address for boot CPU
|
||||
*
|
||||
* Return: Non zero value on failure
|
||||
*/
|
||||
.arch_extension sec
|
||||
ENTRY(keystone_cpu_smc)
|
||||
stmfd sp!, {r4-r11, lr}
|
||||
smc #0
|
||||
ldmfd sp!, {r4-r11, pc}
|
||||
ENDPROC(keystone_cpu_smc)
|
||||
|
|
@ -17,7 +17,6 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/sys_soc.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
|
|
|||
|
|
@ -3,7 +3,5 @@ menuconfig ARCH_RENESAS
|
|||
bool "Renesas ARM SoCs"
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARM_GIC
|
||||
select GPIOLIB
|
||||
select NO_IOPORT_MAP
|
||||
select PINCTRL
|
||||
select ZONE_DMA if ARM_LPAE
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@
|
|||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include "db8500-regs.h"
|
||||
#include "pm_domains.h"
|
||||
|
||||
static int __init ux500_l2x0_unlock(void)
|
||||
|
|
|
|||
|
|
@ -1,195 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2010
|
||||
*/
|
||||
|
||||
#ifndef __MACH_DB8500_REGS_H
|
||||
#define __MACH_DB8500_REGS_H
|
||||
|
||||
/* Base address and bank offsets for ESRAM */
|
||||
#define U8500_ESRAM_BASE 0x40000000
|
||||
#define U8500_ESRAM_BANK_SIZE 0x00020000
|
||||
#define U8500_ESRAM_BANK0 U8500_ESRAM_BASE
|
||||
#define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE)
|
||||
#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
|
||||
#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
|
||||
#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
|
||||
/*
|
||||
* on V1 DMA uses 4KB for logical parameters position is right after the 64KB
|
||||
* reserved for security
|
||||
*/
|
||||
#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
|
||||
|
||||
#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
|
||||
|
||||
/* This address fulfills the 256k alignment requirement of the lcla base */
|
||||
#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4
|
||||
|
||||
#define U8500_PER3_BASE 0x80000000
|
||||
#define U8500_STM_BASE 0x80100000
|
||||
#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
|
||||
#define U8500_PER2_BASE 0x80110000
|
||||
#define U8500_PER1_BASE 0x80120000
|
||||
#define U8500_B2R2_BASE 0x80130000
|
||||
#define U8500_HSEM_BASE 0x80140000
|
||||
#define U8500_PER4_BASE 0x80150000
|
||||
#define U8500_TPIU_BASE 0x80190000
|
||||
#define U8500_ICN_BASE 0x81000000
|
||||
|
||||
#define U8500_BOOT_ROM_BASE 0x90000000
|
||||
/* ASIC ID is at 0xbf4 offset within this region */
|
||||
#define U8500_ASIC_ID_BASE 0x9001D000
|
||||
|
||||
#define U8500_PER6_BASE 0xa03c0000
|
||||
#define U8500_PER7_BASE 0xa03d0000
|
||||
#define U8500_PER5_BASE 0xa03e0000
|
||||
|
||||
#define U8500_SVA_BASE 0xa0100000
|
||||
#define U8500_SIA_BASE 0xa0200000
|
||||
|
||||
#define U8500_SGA_BASE 0xa0300000
|
||||
#define U8500_MCDE_BASE 0xa0350000
|
||||
#define U8500_DMA_BASE 0x801C0000 /* v1 */
|
||||
|
||||
#define U8500_SBAG_BASE 0xa0390000
|
||||
|
||||
#define U8500_SCU_BASE 0xa0410000
|
||||
#define U8500_GIC_CPU_BASE 0xa0410100
|
||||
#define U8500_TWD_BASE 0xa0410600
|
||||
#define U8500_GIC_DIST_BASE 0xa0411000
|
||||
#define U8500_L2CC_BASE 0xa0412000
|
||||
|
||||
#define U8500_MODEM_I2C 0xb7e02000
|
||||
|
||||
#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
|
||||
#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000)
|
||||
#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
|
||||
#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
|
||||
|
||||
#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
|
||||
#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
|
||||
|
||||
/* per6 base addresses */
|
||||
#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
|
||||
#define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000)
|
||||
#define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000)
|
||||
#define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000)
|
||||
#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100)
|
||||
#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
|
||||
#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
|
||||
#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
|
||||
#define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000)
|
||||
#define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000)
|
||||
#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
|
||||
|
||||
/* per5 base addresses */
|
||||
#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
|
||||
#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
|
||||
|
||||
/* per4 base addresses */
|
||||
#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000)
|
||||
#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000)
|
||||
#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000)
|
||||
#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000)
|
||||
#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000)
|
||||
#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000)
|
||||
#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
|
||||
#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
|
||||
#define U9540_DMC1_BASE (U8500_PER4_BASE + 0x0A000)
|
||||
#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
|
||||
#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000)
|
||||
#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
|
||||
#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
|
||||
|
||||
/* per3 base addresses */
|
||||
#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
|
||||
#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
|
||||
#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
|
||||
#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
|
||||
#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
|
||||
#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
|
||||
#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
|
||||
#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
|
||||
#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
|
||||
|
||||
/* per2 base addresses */
|
||||
#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
|
||||
#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
|
||||
#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
|
||||
#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
|
||||
#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
|
||||
#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
|
||||
#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
|
||||
#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
|
||||
#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
|
||||
#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
|
||||
#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
|
||||
#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
|
||||
|
||||
/* per1 base addresses */
|
||||
#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
|
||||
#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
|
||||
#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
|
||||
#define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000)
|
||||
#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
|
||||
#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
|
||||
#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
|
||||
#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000)
|
||||
#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000)
|
||||
#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
|
||||
|
||||
#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040
|
||||
|
||||
#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE
|
||||
#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80)
|
||||
#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE
|
||||
#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80)
|
||||
#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100)
|
||||
#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180)
|
||||
#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE
|
||||
#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
|
||||
#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE
|
||||
|
||||
#define U8500_MCDE_SIZE 0x1000
|
||||
#define U8500_DSI_LINK_SIZE 0x1000
|
||||
#define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE)
|
||||
#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
|
||||
#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
|
||||
#define U8500_DSI_LINK_COUNT 0x3
|
||||
|
||||
/* Modem and APE physical addresses */
|
||||
#define U8500_MODEM_BASE 0xe000000
|
||||
#define U8500_APE_BASE 0x6000000
|
||||
|
||||
/* SoC identification number information */
|
||||
#define U8500_BB_UID_BASE (U8500_BACKUPRAM1_BASE + 0xFC0)
|
||||
|
||||
/* Offsets to specific addresses in some IP blocks for DMA */
|
||||
#define MSP_TX_RX_REG_OFFSET 0
|
||||
#define CRYP1_RX_REG_OFFSET 0x10
|
||||
#define CRYP1_TX_REG_OFFSET 0x8
|
||||
#define HASH1_TX_REG_OFFSET 0x4
|
||||
|
||||
/*
|
||||
* Macros to get at IO space when running virtually
|
||||
* We dont map all the peripherals, let ioremap do
|
||||
* this for us. We map only very basic peripherals here.
|
||||
*/
|
||||
#define U8500_IO_VIRTUAL 0xf0000000
|
||||
#define U8500_IO_PHYSICAL 0xa0000000
|
||||
/* This is where we map in the ROM to check ASIC IDs */
|
||||
#define UX500_VIRT_ROM IOMEM(0xf0000000)
|
||||
|
||||
/* This macro is used in assembly, so no cast */
|
||||
#define IO_ADDRESS(x) \
|
||||
(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
|
||||
|
||||
/* typesafe io address */
|
||||
#define __io_address(n) IOMEM(IO_ADDRESS(n))
|
||||
|
||||
/* Used by some plat-nomadik code */
|
||||
#define io_p2v(n) __io_address(n)
|
||||
|
||||
#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
|
||||
|
||||
#endif
|
||||
|
|
@ -20,8 +20,6 @@
|
|||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
|
||||
#include "db8500-regs.h"
|
||||
|
||||
/* Magic triggers in backup RAM */
|
||||
#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
|
||||
#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
|
||||
|
|
|
|||
|
|
@ -16,8 +16,6 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "db8500-regs.h"
|
||||
|
||||
/* ARM WFI Standby signal register */
|
||||
#define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130)
|
||||
#define PRCM_ARM_WFI_STANDBY_WFI0 0x08
|
||||
|
|
@ -124,7 +122,7 @@ bool prcmu_pending_irq(void)
|
|||
}
|
||||
|
||||
/*
|
||||
* This function checks if the specified cpu is in in WFI. It's usage
|
||||
* This function checks if the specified cpu is in WFI. It's usage
|
||||
* makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
|
||||
* function. Of course passing smp_processor_id() to this function will
|
||||
* always return false...
|
||||
|
|
|
|||
|
|
@ -252,8 +252,6 @@ config ARCH_REALTEK
|
|||
|
||||
config ARCH_RENESAS
|
||||
bool "Renesas SoC Platforms"
|
||||
select GPIOLIB
|
||||
select PINCTRL
|
||||
help
|
||||
This enables support for the ARMv8 based Renesas SoCs.
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,11 @@ config SOC_MICROCHIP_POLARFIRE
|
|||
help
|
||||
This enables support for Microchip PolarFire SoC platforms.
|
||||
|
||||
config ARCH_RENESAS
|
||||
bool "Renesas RISC-V SoCs"
|
||||
help
|
||||
This enables support for the RISC-V based Renesas SoCs.
|
||||
|
||||
config SOC_SIFIVE
|
||||
bool "SiFive SoCs"
|
||||
select SERIAL_SIFIVE if TTY
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@
|
|||
menuconfig SOC_RENESAS
|
||||
bool "Renesas SoC driver support" if COMPILE_TEST && !ARCH_RENESAS
|
||||
default y if ARCH_RENESAS
|
||||
select GPIOLIB
|
||||
select PINCTRL
|
||||
select SOC_BUS
|
||||
|
||||
if SOC_RENESAS
|
||||
|
|
|
|||
|
|
@ -167,20 +167,18 @@ ATTRIBUTE_GROUPS(ux500_soc);
|
|||
static const char *db8500_read_soc_id(struct device_node *backupram)
|
||||
{
|
||||
void __iomem *base;
|
||||
void __iomem *uid;
|
||||
const char *retstr;
|
||||
u32 uid[5];
|
||||
|
||||
base = of_iomap(backupram, 0);
|
||||
if (!base)
|
||||
return NULL;
|
||||
uid = base + 0x1fc0;
|
||||
memcpy_fromio(uid, base + 0x1fc0, sizeof(uid));
|
||||
|
||||
/* Throw these device-specific numbers into the entropy pool */
|
||||
add_device_randomness(uid, 0x14);
|
||||
add_device_randomness(uid, sizeof(uid));
|
||||
retstr = kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
|
||||
readl((u32 *)uid+0),
|
||||
readl((u32 *)uid+1), readl((u32 *)uid+2),
|
||||
readl((u32 *)uid+3), readl((u32 *)uid+4));
|
||||
uid[0], uid[1], uid[2], uid[3], uid[4]);
|
||||
iounmap(base);
|
||||
return retstr;
|
||||
}
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче