nvme.h: add NVM command set SQE/CQE size defines
Reviewed-by: Sagi Grimberg <sagi@grimberg.me> Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Jens Axboe <axboe@fb.com>
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@ -50,6 +50,13 @@ enum {
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#define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
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#define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
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/*
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* Submission and Completion Queue Entry Sizes for the NVM command set.
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* (In bytes and specified as a power of two (2^n)).
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*/
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#define NVME_NVM_IOSQES 6
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#define NVME_NVM_IOCQES 4
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enum {
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NVME_CC_ENABLE = 1 << 0,
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NVME_CC_CSS_NVM = 0 << 4,
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@ -61,8 +68,8 @@ enum {
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NVME_CC_SHN_NORMAL = 1 << 14,
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NVME_CC_SHN_ABRUPT = 2 << 14,
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NVME_CC_SHN_MASK = 3 << 14,
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NVME_CC_IOSQES = 6 << 16,
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NVME_CC_IOCQES = 4 << 20,
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NVME_CC_IOSQES = NVME_NVM_IOSQES << 16,
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NVME_CC_IOCQES = NVME_NVM_IOCQES << 20,
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NVME_CSTS_RDY = 1 << 0,
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NVME_CSTS_CFS = 1 << 1,
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NVME_CSTS_NSSRO = 1 << 4,
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