ARM: mach-shmobile: clock-sh7372: FSI parent select support
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Kuninori Morimoto
Paul Mundt
Родитель
685e4080c6
Коммит
69ce8aa492
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@ -546,27 +546,6 @@ static struct platform_device *qhd_devices[] __initdata = {
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/* FSI */
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#define IRQ_FSI evt2irq(0x1840)
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#define FSIACKCR 0xE6150018
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static void fsiackcr_init(struct clk *clk)
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{
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u32 status = __raw_readl(clk->enable_reg);
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/* use external clock */
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status &= ~0x000000ff;
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status |= 0x00000080;
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__raw_writel(status, clk->enable_reg);
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}
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static struct clk_ops fsiackcr_clk_ops = {
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.init = fsiackcr_init,
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};
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static struct clk fsiackcr_clk = {
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.ops = &fsiackcr_clk_ops,
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.enable_reg = (void __iomem *)FSIACKCR,
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.rate = 0, /* unknown */
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};
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static struct sh_fsi_platform_info fsi_info = {
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.porta_flags = SH_FSI_BRS_INV |
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SH_FSI_OUT_SLAVE_MODE |
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@ -817,6 +796,47 @@ out:
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device_initcall(hdmi_init_pm_clock);
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#define FSIACK_DUMMY_RATE 48000
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static int __init fsi_init_pm_clock(void)
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{
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struct clk *fsia_ick;
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int ret;
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/*
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* FSIACK is connected to AK4642,
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* and the rate is depend on playing sound rate.
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* So, set dummy rate (= 48k) here
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*/
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ret = clk_set_rate(&sh7372_fsiack_clk, FSIACK_DUMMY_RATE);
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if (ret < 0) {
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pr_err("Cannot set FSIACK dummy rate: %d\n", ret);
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return ret;
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}
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fsia_ick = clk_get(&fsi_device.dev, "icka");
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if (IS_ERR(fsia_ick)) {
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ret = PTR_ERR(fsia_ick);
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pr_err("Cannot get FSI ICK: %d\n", ret);
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return ret;
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}
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ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk);
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if (ret < 0) {
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pr_err("Cannot set FSI-A parent: %d\n", ret);
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goto out;
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}
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ret = clk_set_rate(fsia_ick, FSIACK_DUMMY_RATE);
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if (ret < 0)
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pr_err("Cannot set FSI-A rate: %d\n", ret);
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out:
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clk_put(fsia_ick);
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return ret;
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}
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device_initcall(fsi_init_pm_clock);
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/*
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* FIXME !!
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*
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@ -1007,14 +1027,6 @@ static void __init ap4evb_init(void)
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clk_put(clk);
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}
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/* change parent of FSI A */
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clk = clk_get(NULL, "fsia_clk");
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if (!IS_ERR(clk)) {
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clk_register(&fsiackcr_clk);
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clk_set_parent(clk, &fsiackcr_clk);
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clk_put(clk);
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}
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/*
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* set irq priority, to avoid sound chopping
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* when NFS rootfs is used
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@ -292,6 +292,13 @@ struct clk sh7372_pllc2_clk = {
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.parent_num = ARRAY_SIZE(pllc2_parent),
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};
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/* External input clock (pin name: FSIACK/FSIBCK ) */
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struct clk sh7372_fsiack_clk = {
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};
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struct clk sh7372_fsibck_clk = {
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};
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static struct clk *main_clks[] = {
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&sh7372_dv_clki_clk,
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&r_clk,
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@ -305,6 +312,8 @@ static struct clk *main_clks[] = {
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&pllc1_clk,
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&pllc1_div2_clk,
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&sh7372_pllc2_clk,
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&sh7372_fsiack_clk,
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&sh7372_fsibck_clk,
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};
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static void div4_kick(struct clk *clk)
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@ -357,7 +366,7 @@ static struct clk div4_clks[DIV4_NR] = {
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};
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enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
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DIV6_FSIA, DIV6_FSIB, DIV6_SUB, DIV6_SPU,
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DIV6_SUB, DIV6_SPU,
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DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
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DIV6_NR };
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@ -367,8 +376,6 @@ static struct clk div6_clks[DIV6_NR] = {
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[DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
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[DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
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[DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
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[DIV6_FSIA] = SH_CLK_DIV6(&pllc1_div2_clk, FSIACKCR, 0),
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[DIV6_FSIB] = SH_CLK_DIV6(&pllc1_div2_clk, FSIBCKCR, 0),
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[DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
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[DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
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[DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
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@ -377,7 +384,7 @@ static struct clk div6_clks[DIV6_NR] = {
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[DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
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};
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enum { DIV6_HDMI, DIV6_REPARENT_NR };
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enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR };
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/* Indices are important - they are the actual src selecting values */
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static struct clk *hdmi_parent[] = {
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@ -387,9 +394,27 @@ static struct clk *hdmi_parent[] = {
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[3] = NULL, /* pllc2_div4 not implemented yet */
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};
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static struct clk *fsiackcr_parent[] = {
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[0] = &pllc1_div2_clk,
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[1] = &sh7372_pllc2_clk,
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[2] = &sh7372_fsiack_clk, /* external input for FSI A */
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[3] = NULL, /* setting prohibited */
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};
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static struct clk *fsibckcr_parent[] = {
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[0] = &pllc1_div2_clk,
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[1] = &sh7372_pllc2_clk,
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[2] = &sh7372_fsibck_clk, /* external input for FSI B */
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[3] = NULL, /* setting prohibited */
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};
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static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
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[DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
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hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
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[DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0,
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fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
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[DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0,
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fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
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};
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enum { MSTP001,
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@ -429,7 +454,7 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
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[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
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[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
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[MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSIA */
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[MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
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[MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
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[MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
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[MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
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@ -445,6 +470,7 @@ static struct clk mstp_clks[MSTP_NR] = {
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#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
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#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
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#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
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static struct clk_lookup lookups[] = {
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/* main clocks */
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@ -483,8 +509,8 @@ static struct clk_lookup lookups[] = {
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CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
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CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
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CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
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CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FSIA]),
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CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FSIB]),
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CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FSIA]),
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CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FSIB]),
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CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
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CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
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CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
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@ -531,7 +557,10 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
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CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
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CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
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{.con_id = "ick", .dev_id = "sh-mobile-hdmi", .clk = &div6_reparent_clks[DIV6_HDMI]},
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CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
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CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
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CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
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};
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void __init sh7372_clock_init(void)
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@ -462,5 +462,7 @@ extern struct clk sh7372_extal2_clk;
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extern struct clk sh7372_dv_clki_clk;
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extern struct clk sh7372_dv_clki_div2_clk;
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extern struct clk sh7372_pllc2_clk;
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extern struct clk sh7372_fsiack_clk;
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extern struct clk sh7372_fsibck_clk;
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#endif /* __ASM_SH7372_H__ */
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