From 63f559d3412b8bcfa24040e16de6dae27fafd4af Mon Sep 17 00:00:00 2001 From: Zheng Yongjun Date: Fri, 11 Dec 2020 17:00:55 +0800 Subject: [PATCH 01/23] mtd: rawnand: mxc: Convert comma to semicolon Replace a comma between expression statements by a semicolon. Signed-off-by: Zheng Yongjun Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20201211090055.3250-1-zhengyongjun3@huawei.com --- drivers/mtd/nand/raw/mxc_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index fd705dd1768d..f78302e16b84 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -1731,7 +1731,7 @@ static int mxcnd_probe(struct platform_device *pdev) this->legacy.chip_delay = 5; nand_set_controller_data(this, host); - nand_set_flash_node(this, pdev->dev.of_node), + nand_set_flash_node(this, pdev->dev.of_node); this->legacy.dev_ready = mxc_nand_dev_ready; this->legacy.cmdfunc = mxc_nand_command; this->legacy.read_byte = mxc_nand_read_byte; From 5f327f08192e2ff957ea43a2b4a2659663320483 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 4 Jan 2021 09:41:34 +0530 Subject: [PATCH 02/23] dt-bindings: mtd: partitions: Add binding for Qcom SMEM parser Add YAML binding for Qualcomm Shared Memory (SMEM) Flash partition parser. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20210104041137.113075-2-manivannan.sadhasivam@linaro.org --- .../mtd/partitions/qcom,smem-part.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/partitions/qcom,smem-part.yaml diff --git a/Documentation/devicetree/bindings/mtd/partitions/qcom,smem-part.yaml b/Documentation/devicetree/bindings/mtd/partitions/qcom,smem-part.yaml new file mode 100644 index 000000000000..cf3f8c1e035d --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/partitions/qcom,smem-part.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/partitions/qcom,smem-part.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SMEM NAND flash partition parser binding + +maintainers: + - Manivannan Sadhasivam + +description: | + The Qualcomm SoCs supporting the NAND controller interface features a Shared + Memory (SMEM) based partition table scheme. The maximum partitions supported + varies between partition table revisions. V3 supports maximum 16 partitions + and V4 supports 48 partitions. + +properties: + compatible: + const: qcom,smem-part + +required: + - compatible + +additionalProperties: false + +examples: + - | + flash { + partitions { + compatible = "qcom,smem-part"; + }; + }; From 803eb124e1a64e42888542c3444bfe6dac412c7f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 4 Jan 2021 09:41:35 +0530 Subject: [PATCH 03/23] mtd: parsers: Add Qcom SMEM parser NAND based Qualcomm platforms have the partition table populated in the Shared Memory (SMEM). Hence, add a parser for parsing the partitions from it. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20210104041137.113075-3-manivannan.sadhasivam@linaro.org --- drivers/mtd/parsers/Kconfig | 8 ++ drivers/mtd/parsers/Makefile | 1 + drivers/mtd/parsers/qcomsmempart.c | 170 +++++++++++++++++++++++++++++ 3 files changed, 179 insertions(+) create mode 100644 drivers/mtd/parsers/qcomsmempart.c diff --git a/drivers/mtd/parsers/Kconfig b/drivers/mtd/parsers/Kconfig index e72354322f62..d90c30229052 100644 --- a/drivers/mtd/parsers/Kconfig +++ b/drivers/mtd/parsers/Kconfig @@ -160,3 +160,11 @@ config MTD_REDBOOT_PARTS_READONLY 'FIS directory' images, enable this option. endif # MTD_REDBOOT_PARTS + +config MTD_QCOMSMEM_PARTS + tristate "Qualcomm SMEM NAND flash partition parser" + depends on MTD_NAND_QCOM || COMPILE_TEST + depends on QCOM_SMEM + help + This provides support for parsing partitions from Shared Memory (SMEM) + for NAND flash on Qualcomm platforms. diff --git a/drivers/mtd/parsers/Makefile b/drivers/mtd/parsers/Makefile index b0c5f62f9e85..50eb0b0a2210 100644 --- a/drivers/mtd/parsers/Makefile +++ b/drivers/mtd/parsers/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o +obj-$(CONFIG_MTD_QCOMSMEM_PARTS) += qcomsmempart.o diff --git a/drivers/mtd/parsers/qcomsmempart.c b/drivers/mtd/parsers/qcomsmempart.c new file mode 100644 index 000000000000..808cb33d71f8 --- /dev/null +++ b/drivers/mtd/parsers/qcomsmempart.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Qualcomm SMEM NAND flash partition parser + * + * Copyright (C) 2020, Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include + +#define SMEM_AARM_PARTITION_TABLE 9 +#define SMEM_APPS 0 + +#define SMEM_FLASH_PART_MAGIC1 0x55ee73aa +#define SMEM_FLASH_PART_MAGIC2 0xe35ebddb +#define SMEM_FLASH_PTABLE_V3 3 +#define SMEM_FLASH_PTABLE_V4 4 +#define SMEM_FLASH_PTABLE_MAX_PARTS_V3 16 +#define SMEM_FLASH_PTABLE_MAX_PARTS_V4 48 +#define SMEM_FLASH_PTABLE_HDR_LEN (4 * sizeof(u32)) +#define SMEM_FLASH_PTABLE_NAME_SIZE 16 + +/** + * struct smem_flash_pentry - SMEM Flash partition entry + * @name: Name of the partition + * @offset: Offset in blocks + * @length: Length of the partition in blocks + * @attr: Flags for this partition + */ +struct smem_flash_pentry { + char name[SMEM_FLASH_PTABLE_NAME_SIZE]; + __le32 offset; + __le32 length; + u8 attr; +} __packed __aligned(4); + +/** + * struct smem_flash_ptable - SMEM Flash partition table + * @magic1: Partition table Magic 1 + * @magic2: Partition table Magic 2 + * @version: Partition table version + * @numparts: Number of partitions in this ptable + * @pentry: Flash partition entries belonging to this ptable + */ +struct smem_flash_ptable { + __le32 magic1; + __le32 magic2; + __le32 version; + __le32 numparts; + struct smem_flash_pentry pentry[SMEM_FLASH_PTABLE_MAX_PARTS_V4]; +} __packed __aligned(4); + +static int parse_qcomsmem_part(struct mtd_info *mtd, + const struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct smem_flash_pentry *pentry; + struct smem_flash_ptable *ptable; + size_t len = SMEM_FLASH_PTABLE_HDR_LEN; + struct mtd_partition *parts; + int ret, i, numparts; + char *name, *c; + + pr_debug("Parsing partition table info from SMEM\n"); + ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len); + if (IS_ERR(ptable)) { + pr_err("Error reading partition table header\n"); + return PTR_ERR(ptable); + } + + /* Verify ptable magic */ + if (le32_to_cpu(ptable->magic1) != SMEM_FLASH_PART_MAGIC1 || + le32_to_cpu(ptable->magic2) != SMEM_FLASH_PART_MAGIC2) { + pr_err("Partition table magic verification failed\n"); + return -EINVAL; + } + + /* Ensure that # of partitions is less than the max we have allocated */ + numparts = le32_to_cpu(ptable->numparts); + if (numparts > SMEM_FLASH_PTABLE_MAX_PARTS_V4) { + pr_err("Partition numbers exceed the max limit\n"); + return -EINVAL; + } + + /* Find out length of partition data based on table version */ + if (le32_to_cpu(ptable->version) <= SMEM_FLASH_PTABLE_V3) { + len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V3 * + sizeof(struct smem_flash_pentry); + } else if (le32_to_cpu(ptable->version) == SMEM_FLASH_PTABLE_V4) { + len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V4 * + sizeof(struct smem_flash_pentry); + } else { + pr_err("Unknown ptable version (%d)", le32_to_cpu(ptable->version)); + return -EINVAL; + } + + /* + * Now that the partition table header has been parsed, verified + * and the length of the partition table calculated, read the + * complete partition table + */ + ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len); + if (IS_ERR_OR_NULL(ptable)) { + pr_err("Error reading partition table\n"); + return PTR_ERR(ptable); + } + + parts = kcalloc(numparts, sizeof(*parts), GFP_KERNEL); + if (!parts) + return -ENOMEM; + + for (i = 0; i < numparts; i++) { + pentry = &ptable->pentry[i]; + if (pentry->name[0] == '\0') + continue; + + name = kstrdup(pentry->name, GFP_KERNEL); + if (!name) { + ret = -ENOMEM; + goto out_free_parts; + } + + /* Convert name to lower case */ + for (c = name; *c != '\0'; c++) + *c = tolower(*c); + + parts[i].name = name; + parts[i].offset = le32_to_cpu(pentry->offset) * mtd->erasesize; + parts[i].mask_flags = pentry->attr; + parts[i].size = le32_to_cpu(pentry->length) * mtd->erasesize; + pr_debug("%d: %s offs=0x%08x size=0x%08x attr:0x%08x\n", + i, pentry->name, le32_to_cpu(pentry->offset), + le32_to_cpu(pentry->length), pentry->attr); + } + + pr_debug("SMEM partition table found: ver: %d len: %d\n", + le32_to_cpu(ptable->version), numparts); + *pparts = parts; + + return numparts; + +out_free_parts: + while (--i >= 0) + kfree(parts[i].name); + kfree(parts); + *pparts = NULL; + + return ret; +} + +static const struct of_device_id qcomsmem_of_match_table[] = { + { .compatible = "qcom,smem-part" }, + {}, +}; +MODULE_DEVICE_TABLE(of, qcomsmem_of_match_table); + +static struct mtd_part_parser mtd_parser_qcomsmem = { + .parse_fn = parse_qcomsmem_part, + .name = "qcomsmem", + .of_match_table = qcomsmem_of_match_table, +}; +module_mtd_part_parser(mtd_parser_qcomsmem); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_DESCRIPTION("Qualcomm SMEM NAND flash partition parser"); From 82bfd11f1b0364cfd75069d1464f92cc2a985660 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 4 Jan 2021 09:41:36 +0530 Subject: [PATCH 04/23] mtd: rawnand: qcom: Add support for Qcom SMEM parser Add support for using Qualcomm SMEM based flash partition parser in Qualcomm NAND controller. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20210104041137.113075-4-manivannan.sadhasivam@linaro.org --- drivers/mtd/nand/raw/qcom_nandc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 667e4bfe369f..fd4c318b520f 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2821,6 +2821,8 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) return 0; } +static const char * const probes[] = { "qcomsmem", NULL }; + static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, struct qcom_nand_host *host, struct device_node *dn) @@ -2884,7 +2886,7 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, } } - ret = mtd_device_register(mtd, NULL, 0); + ret = mtd_device_parse_register(mtd, probes, NULL, NULL, 0); if (ret) nand_cleanup(chip); From d5802468c358cd421c09355467be36a41ea5b5d6 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Wed, 13 Jan 2021 13:15:45 +0300 Subject: [PATCH 05/23] mtd: spi-nor: intel-spi: Add support for Intel Alder Lake-P SPI serial flash Intel Alder Lake-P has the same SPI serial flash controller as Alder Lake-S. Add Alder Lake-P PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20210113101545.71579-1-mika.westerberg@linux.intel.com --- drivers/mtd/spi-nor/controllers/intel-spi-pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/controllers/intel-spi-pci.c b/drivers/mtd/spi-nor/controllers/intel-spi-pci.c index 555fe55d14ae..825610a2e9dc 100644 --- a/drivers/mtd/spi-nor/controllers/intel-spi-pci.c +++ b/drivers/mtd/spi-nor/controllers/intel-spi-pci.c @@ -73,6 +73,7 @@ static const struct pci_device_id intel_spi_pci_ids[] = { { PCI_VDEVICE(INTEL, 0x43a4), (unsigned long)&cnl_info }, { PCI_VDEVICE(INTEL, 0x4b24), (unsigned long)&bxt_info }, { PCI_VDEVICE(INTEL, 0x4da4), (unsigned long)&bxt_info }, + { PCI_VDEVICE(INTEL, 0x51a4), (unsigned long)&cnl_info }, { PCI_VDEVICE(INTEL, 0x7aa4), (unsigned long)&cnl_info }, { PCI_VDEVICE(INTEL, 0xa0a4), (unsigned long)&bxt_info }, { PCI_VDEVICE(INTEL, 0xa1a4), (unsigned long)&bxt_info }, From fe6653460ee7a7dbe0cd5fd322992af862ce5ab0 Mon Sep 17 00:00:00 2001 From: Pan Bian Date: Thu, 21 Jan 2021 01:18:47 -0800 Subject: [PATCH 06/23] mtd: spi-nor: hisi-sfc: Put child node np on error path Put the child node np when it fails to get or register device. Fixes: e523f11141bd ("mtd: spi-nor: add hisilicon spi-nor flash controller driver") Cc: stable@vger.kernel.org Signed-off-by: Pan Bian [ta: Add Fixes tag and Cc stable] Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20210121091847.85362-1-bianpan2016@163.com --- drivers/mtd/spi-nor/controllers/hisi-sfc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/controllers/hisi-sfc.c b/drivers/mtd/spi-nor/controllers/hisi-sfc.c index 7c26f8f565cb..47fbf1d1e557 100644 --- a/drivers/mtd/spi-nor/controllers/hisi-sfc.c +++ b/drivers/mtd/spi-nor/controllers/hisi-sfc.c @@ -399,8 +399,10 @@ static int hisi_spi_nor_register_all(struct hifmc_host *host) for_each_available_child_of_node(dev->of_node, np) { ret = hisi_spi_nor_register(np, host); - if (ret) + if (ret) { + of_node_put(np); goto fail; + } if (host->num_chip == HIFMC_MAX_CHIP_NUM) { dev_warn(dev, "Flash device number exceeds the maximum chipselect number\n"); From b81770a7007c4286880ed4b182e22b1897f27cfe Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Fri, 11 Sep 2020 11:23:21 +0100 Subject: [PATCH 07/23] mtd: remove redundant assignment to pointer eb Pointer eb is being assigned a value that is never read, the assignment is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20200911102321.22515-1-colin.king@canonical.com --- drivers/mtd/mtdswap.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mtd/mtdswap.c b/drivers/mtd/mtdswap.c index 58eefa43af14..795dec4483c2 100644 --- a/drivers/mtd/mtdswap.c +++ b/drivers/mtd/mtdswap.c @@ -1053,7 +1053,6 @@ static int mtdswap_writesect(struct mtd_blktrans_dev *dev, if (ret < 0) return ret; - eb = d->eb_data + (newblock / d->pages_per_eblk); d->page_data[page] = newblock; return 0; From dc2b3e5cbc8087224fcd8698b0dc56131e0bf37d Mon Sep 17 00:00:00 2001 From: yangerkun Date: Mon, 25 Jan 2021 20:49:36 +0800 Subject: [PATCH 08/23] mtd: phram: use div_u64_rem to stop overwrite len in phram_setup We now support user to set erase page size, and use do_div between len and erase size to determine the reasonableness for the erase size. However, do_div is a macro and will overwrite the value of len. Which results a mtd device with unexcepted size. Fix it by use div_u64_rem. Fixes: ffad560394de ("mtd: phram: Allow the user to set the erase page size.") Signed-off-by: yangerkun Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20210125124936.651812-1-yangerkun@huawei.com --- drivers/mtd/devices/phram.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/devices/phram.c b/drivers/mtd/devices/phram.c index cfd170946ba4..5b04ae6c3057 100644 --- a/drivers/mtd/devices/phram.c +++ b/drivers/mtd/devices/phram.c @@ -222,6 +222,7 @@ static int phram_setup(const char *val) uint64_t start; uint64_t len; uint64_t erasesize = PAGE_SIZE; + uint32_t rem; int i, ret; if (strnlen(val, sizeof(buf)) >= sizeof(buf)) @@ -263,8 +264,11 @@ static int phram_setup(const char *val) } } + if (erasesize) + div_u64_rem(len, (uint32_t)erasesize, &rem); + if (len == 0 || erasesize == 0 || erasesize > len - || erasesize > UINT_MAX || do_div(len, (uint32_t)erasesize) != 0) { + || erasesize > UINT_MAX || rem) { parse_err("illegal erasesize or len\n"); goto error; } From 12ba8f8ce29fdd277f3100052eddc1afd2f5ea3f Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 28 Jan 2021 12:36:52 +0300 Subject: [PATCH 09/23] mtd: parser: imagetag: fix error codes in bcm963xx_parse_imagetag_partitions() If the kstrtouint() calls fail, then this should return a negative error code but it currently returns success. Fixes: dd84cb022b31 ("mtd: bcm63xxpart: move imagetag parsing to its own parser") Signed-off-by: Dan Carpenter Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/YBKFtNaFHGYBj+u4@mwanda --- drivers/mtd/parsers/parser_imagetag.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/parsers/parser_imagetag.c b/drivers/mtd/parsers/parser_imagetag.c index d69607b48227..fab0949aabba 100644 --- a/drivers/mtd/parsers/parser_imagetag.c +++ b/drivers/mtd/parsers/parser_imagetag.c @@ -83,6 +83,7 @@ static int bcm963xx_parse_imagetag_partitions(struct mtd_info *master, pr_err("invalid rootfs address: %*ph\n", (int)sizeof(buf->flash_image_start), buf->flash_image_start); + ret = -EINVAL; goto out; } @@ -92,6 +93,7 @@ static int bcm963xx_parse_imagetag_partitions(struct mtd_info *master, pr_err("invalid kernel address: %*ph\n", (int)sizeof(buf->kernel_address), buf->kernel_address); + ret = -EINVAL; goto out; } @@ -100,6 +102,7 @@ static int bcm963xx_parse_imagetag_partitions(struct mtd_info *master, pr_err("invalid kernel length: %*ph\n", (int)sizeof(buf->kernel_length), buf->kernel_length); + ret = -EINVAL; goto out; } @@ -108,6 +111,7 @@ static int bcm963xx_parse_imagetag_partitions(struct mtd_info *master, pr_err("invalid total length: %*ph\n", (int)sizeof(buf->total_length), buf->total_length); + ret = -EINVAL; goto out; } From 7b844cf445f0a7daa68be0ce71eb2c88d68b0c5d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 4 Jan 2021 09:41:37 +0530 Subject: [PATCH 10/23] mtd: parsers: afs: Fix freeing the part name memory in failure In the case of failure while parsing the partitions, the iterator should be pre decremented by one before starting to free the memory allocated by kstrdup(). Because in the failure case, kstrdup() will not succeed and thus no memory will be allocated for the current iteration. Fixes: 1fca1f6abb38 ("mtd: afs: simplify partition parsing") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij Cc: Linus Walleij Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20210104041137.113075-5-manivannan.sadhasivam@linaro.org --- drivers/mtd/parsers/afs.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/mtd/parsers/afs.c b/drivers/mtd/parsers/afs.c index 980e332bdac4..26116694c821 100644 --- a/drivers/mtd/parsers/afs.c +++ b/drivers/mtd/parsers/afs.c @@ -370,10 +370,8 @@ static int parse_afs_partitions(struct mtd_info *mtd, return i; out_free_parts: - while (i >= 0) { + while (--i >= 0) kfree(parts[i].name); - i--; - } kfree(parts); *pparts = NULL; return ret; From 2e64e0ba2b657ca5c0eece887aeb73cff660f92c Mon Sep 17 00:00:00 2001 From: Zheng Yongjun Date: Fri, 8 Jan 2021 17:23:00 +0800 Subject: [PATCH 11/23] mtd: convert comma to semicolon Replace a comma between expression statements by a semicolon. Signed-off-by: Zheng Yongjun Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20210108092300.18909-1-zhengyongjun3@huawei.com --- drivers/mtd/maps/pci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/maps/pci.c b/drivers/mtd/maps/pci.c index 377ef0fc4e3e..ca00d211e73e 100644 --- a/drivers/mtd/maps/pci.c +++ b/drivers/mtd/maps/pci.c @@ -90,8 +90,8 @@ intel_iq80310_init(struct pci_dev *dev, struct map_pci_info *map) u32 win_base; map->map.bankwidth = 1; - map->map.read = mtd_pci_read8, - map->map.write = mtd_pci_write8, + map->map.read = mtd_pci_read8; + map->map.write = mtd_pci_write8; map->map.size = 0x00800000; map->base = ioremap(pci_resource_start(dev, 0), @@ -185,8 +185,8 @@ intel_dc21285_init(struct pci_dev *dev, struct map_pci_info *map) return -ENXIO; map->map.bankwidth = 4; - map->map.read = mtd_pci_read32, - map->map.write = mtd_pci_write32, + map->map.read = mtd_pci_read32; + map->map.write = mtd_pci_write32; map->map.size = len; map->base = ioremap(base, len); From 106a3ec368fd5c34d5138e645f163249612d335d Mon Sep 17 00:00:00 2001 From: Zheng Yongjun Date: Fri, 8 Jan 2021 17:23:25 +0800 Subject: [PATCH 12/23] mtd: st_spi_fsm: convert comma to semicolon Replace a comma between expression statements by a semicolon. Signed-off-by: Zheng Yongjun Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20210108092325.19037-1-zhengyongjun3@huawei.com --- drivers/mtd/devices/st_spi_fsm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 1888523d9745..983999c020d6 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -924,7 +924,7 @@ static int stfsm_read_status(struct stfsm *fsm, uint8_t cmd, BUG_ON(bytes != 1 && bytes != 2); seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | - SEQ_OPC_OPCODE(cmd)), + SEQ_OPC_OPCODE(cmd)); stfsm_load_seq(fsm, seq); From e64ab8e8fa014e5fa1571b4cf256b930451d5d00 Mon Sep 17 00:00:00 2001 From: Zheng Yongjun Date: Fri, 8 Jan 2021 17:23:14 +0800 Subject: [PATCH 13/23] mtd: rawnand: marvell: convert comma to semicolon Replace a comma between expression statements by a semicolon. Signed-off-by: Zheng Yongjun Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20210108092314.18972-1-zhengyongjun3@huawei.com --- drivers/mtd/nand/raw/marvell_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c index 42d4881d598d..79da6b02e209 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -2396,7 +2396,7 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr, * be greater than that to be sure tCCS delay is respected. */ nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), - period_ns) - 2, + period_ns) - 2; nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), period_ns); From 94d07f6a539db14ced8c0c2ae6ed4ab9623a24ab Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 20 Jan 2021 16:05:26 +0100 Subject: [PATCH 14/23] mtd: rawnand: tango: Remove the driver The tango platform is getting removed [1], so the driver is no longer needed. [1] https://lore.kernel.org/linux-arm-kernel/20210120124812.2800027-1-arnd@kernel.org/T/ Cc: Marc Gonzalez Cc: Mans Rullgard Signed-off-by: Arnd Bergmann Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20210120150555.1610132-1-arnd@kernel.org --- drivers/mtd/nand/raw/Kconfig | 7 - drivers/mtd/nand/raw/Makefile | 1 - drivers/mtd/nand/raw/tango_nand.c | 727 ------------------------------ 3 files changed, 735 deletions(-) delete mode 100644 drivers/mtd/nand/raw/tango_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 442a039b92f3..06f11cb73bf9 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -102,13 +102,6 @@ config MTD_NAND_S3C2410_CLKSTOP when the is NAND chip selected or released, but will save approximately 5mA of power when there is nothing happening. -config MTD_NAND_TANGO - tristate "Tango NAND controller" - depends on ARCH_TANGO || COMPILE_TEST - depends on HAS_IOMEM - help - Enables the NAND Flash controller on Tango chips. - config MTD_NAND_SHARPSL tristate "Sharp SL Series (C7xx + others) NAND controller" depends on ARCH_PXA || COMPILE_TEST diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 32475a28d8f8..d011c6c53f8f 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -10,7 +10,6 @@ obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o -obj-$(CONFIG_MTD_NAND_TANGO) += tango_nand.o obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o obj-$(CONFIG_MTD_NAND_FSMC) += fsmc_nand.o diff --git a/drivers/mtd/nand/raw/tango_nand.c b/drivers/mtd/nand/raw/tango_nand.c deleted file mode 100644 index 359187b5a4be..000000000000 --- a/drivers/mtd/nand/raw/tango_nand.c +++ /dev/null @@ -1,727 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Sigma Designs - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Offsets relative to chip->base */ -#define PBUS_CMD 0 -#define PBUS_ADDR 4 -#define PBUS_DATA 8 - -/* Offsets relative to reg_base */ -#define NFC_STATUS 0x00 -#define NFC_FLASH_CMD 0x04 -#define NFC_DEVICE_CFG 0x08 -#define NFC_TIMING1 0x0c -#define NFC_TIMING2 0x10 -#define NFC_XFER_CFG 0x14 -#define NFC_PKT_0_CFG 0x18 -#define NFC_PKT_N_CFG 0x1c -#define NFC_BB_CFG 0x20 -#define NFC_ADDR_PAGE 0x24 -#define NFC_ADDR_OFFSET 0x28 -#define NFC_XFER_STATUS 0x2c - -/* NFC_STATUS values */ -#define CMD_READY BIT(31) - -/* NFC_FLASH_CMD values */ -#define NFC_READ 1 -#define NFC_WRITE 2 - -/* NFC_XFER_STATUS values */ -#define PAGE_IS_EMPTY BIT(16) - -/* Offsets relative to mem_base */ -#define METADATA 0x000 -#define ERROR_REPORT 0x1c0 - -/* - * Error reports are split in two bytes: - * byte 0 for the first packet in the page (PKT_0) - * byte 1 for other packets in the page (PKT_N, for N > 0) - * ERR_COUNT_PKT_N is the max error count over all but the first packet. - */ -#define ERR_COUNT_PKT_0(v) (((v) >> 0) & 0x3f) -#define ERR_COUNT_PKT_N(v) (((v) >> 8) & 0x3f) -#define DECODE_FAIL_PKT_0(v) (((v) & BIT(7)) == 0) -#define DECODE_FAIL_PKT_N(v) (((v) & BIT(15)) == 0) - -/* Offsets relative to pbus_base */ -#define PBUS_CS_CTRL 0x83c -#define PBUS_PAD_MODE 0x8f0 - -/* PBUS_CS_CTRL values */ -#define PBUS_IORDY BIT(31) - -/* - * PBUS_PAD_MODE values - * In raw mode, the driver communicates directly with the NAND chips. - * In NFC mode, the NAND Flash controller manages the communication. - * We use NFC mode for read and write; raw mode for everything else. - */ -#define MODE_RAW 0 -#define MODE_NFC BIT(31) - -#define METADATA_SIZE 4 -#define BBM_SIZE 6 -#define FIELD_ORDER 15 - -#define MAX_CS 4 - -struct tango_nfc { - struct nand_controller hw; - void __iomem *reg_base; - void __iomem *mem_base; - void __iomem *pbus_base; - struct tango_chip *chips[MAX_CS]; - struct dma_chan *chan; - int freq_kHz; -}; - -#define to_tango_nfc(ptr) container_of(ptr, struct tango_nfc, hw) - -struct tango_chip { - struct nand_chip nand_chip; - void __iomem *base; - u32 timing1; - u32 timing2; - u32 xfer_cfg; - u32 pkt_0_cfg; - u32 pkt_n_cfg; - u32 bb_cfg; -}; - -#define to_tango_chip(ptr) container_of(ptr, struct tango_chip, nand_chip) - -#define XFER_CFG(cs, page_count, steps, metadata_size) \ - ((cs) << 24 | (page_count) << 16 | (steps) << 8 | (metadata_size)) - -#define PKT_CFG(size, strength) ((size) << 16 | (strength)) - -#define BB_CFG(bb_offset, bb_size) ((bb_offset) << 16 | (bb_size)) - -#define TIMING(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3)) - -static void tango_select_target(struct nand_chip *chip, unsigned int cs) -{ - struct tango_nfc *nfc = to_tango_nfc(chip->controller); - struct tango_chip *tchip = to_tango_chip(chip); - - writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1); - writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2); - writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG); - writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG); - writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG); - writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG); -} - -static int tango_waitrdy(struct nand_chip *chip, unsigned int timeout_ms) -{ - struct tango_nfc *nfc = to_tango_nfc(chip->controller); - u32 status; - - return readl_relaxed_poll_timeout(nfc->pbus_base + PBUS_CS_CTRL, - status, status & PBUS_IORDY, 20, - timeout_ms); -} - -static int tango_exec_instr(struct nand_chip *chip, - const struct nand_op_instr *instr) -{ - struct tango_chip *tchip = to_tango_chip(chip); - unsigned int i; - - switch (instr->type) { - case NAND_OP_CMD_INSTR: - writeb_relaxed(instr->ctx.cmd.opcode, tchip->base + PBUS_CMD); - return 0; - case NAND_OP_ADDR_INSTR: - for (i = 0; i < instr->ctx.addr.naddrs; i++) - writeb_relaxed(instr->ctx.addr.addrs[i], - tchip->base + PBUS_ADDR); - return 0; - case NAND_OP_DATA_IN_INSTR: - ioread8_rep(tchip->base + PBUS_DATA, instr->ctx.data.buf.in, - instr->ctx.data.len); - return 0; - case NAND_OP_DATA_OUT_INSTR: - iowrite8_rep(tchip->base + PBUS_DATA, instr->ctx.data.buf.out, - instr->ctx.data.len); - return 0; - case NAND_OP_WAITRDY_INSTR: - return tango_waitrdy(chip, - instr->ctx.waitrdy.timeout_ms); - default: - break; - } - - return -EINVAL; -} - -static int tango_exec_op(struct nand_chip *chip, - const struct nand_operation *op, - bool check_only) -{ - unsigned int i; - int ret = 0; - - if (check_only) - return 0; - - tango_select_target(chip, op->cs); - for (i = 0; i < op->ninstrs; i++) { - ret = tango_exec_instr(chip, &op->instrs[i]); - if (ret) - break; - } - - return ret; -} - -/* - * The controller does not check for bitflips in erased pages, - * therefore software must check instead. - */ -static int check_erased_page(struct nand_chip *chip, u8 *buf) -{ - struct mtd_info *mtd = nand_to_mtd(chip); - u8 *meta = chip->oob_poi + BBM_SIZE; - u8 *ecc = chip->oob_poi + BBM_SIZE + METADATA_SIZE; - const int ecc_size = chip->ecc.bytes; - const int pkt_size = chip->ecc.size; - int i, res, meta_len, bitflips = 0; - - for (i = 0; i < chip->ecc.steps; ++i) { - meta_len = i ? 0 : METADATA_SIZE; - res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size, - meta, meta_len, - chip->ecc.strength); - if (res < 0) - mtd->ecc_stats.failed++; - else - mtd->ecc_stats.corrected += res; - - bitflips = max(res, bitflips); - buf += pkt_size; - ecc += ecc_size; - } - - return bitflips; -} - -static int decode_error_report(struct nand_chip *chip) -{ - u32 status, res; - struct mtd_info *mtd = nand_to_mtd(chip); - struct tango_nfc *nfc = to_tango_nfc(chip->controller); - - status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS); - if (status & PAGE_IS_EMPTY) - return 0; - - res = readl_relaxed(nfc->mem_base + ERROR_REPORT); - - if (DECODE_FAIL_PKT_0(res) || DECODE_FAIL_PKT_N(res)) - return -EBADMSG; - - /* ERR_COUNT_PKT_N is max, not sum, but that's all we have */ - mtd->ecc_stats.corrected += - ERR_COUNT_PKT_0(res) + ERR_COUNT_PKT_N(res); - - return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res)); -} - -static void tango_dma_callback(void *arg) -{ - complete(arg); -} - -static int do_dma(struct tango_nfc *nfc, enum dma_data_direction dir, int cmd, - const void *buf, int len, int page) -{ - void __iomem *addr = nfc->reg_base + NFC_STATUS; - struct dma_chan *chan = nfc->chan; - struct dma_async_tx_descriptor *desc; - enum dma_transfer_direction tdir; - struct scatterlist sg; - struct completion tx_done; - int err = -EIO; - u32 res, val; - - sg_init_one(&sg, buf, len); - if (dma_map_sg(chan->device->dev, &sg, 1, dir) != 1) - return -EIO; - - tdir = dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; - desc = dmaengine_prep_slave_sg(chan, &sg, 1, tdir, DMA_PREP_INTERRUPT); - if (!desc) - goto dma_unmap; - - desc->callback = tango_dma_callback; - desc->callback_param = &tx_done; - init_completion(&tx_done); - - writel_relaxed(MODE_NFC, nfc->pbus_base + PBUS_PAD_MODE); - - writel_relaxed(page, nfc->reg_base + NFC_ADDR_PAGE); - writel_relaxed(0, nfc->reg_base + NFC_ADDR_OFFSET); - writel_relaxed(cmd, nfc->reg_base + NFC_FLASH_CMD); - - dmaengine_submit(desc); - dma_async_issue_pending(chan); - - res = wait_for_completion_timeout(&tx_done, HZ); - if (res > 0) - err = readl_poll_timeout(addr, val, val & CMD_READY, 0, 1000); - - writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE); - -dma_unmap: - dma_unmap_sg(chan->device->dev, &sg, 1, dir); - - return err; -} - -static int tango_read_page(struct nand_chip *chip, u8 *buf, - int oob_required, int page) -{ - struct mtd_info *mtd = nand_to_mtd(chip); - struct tango_nfc *nfc = to_tango_nfc(chip->controller); - int err, res, len = mtd->writesize; - - tango_select_target(chip, chip->cur_cs); - if (oob_required) - chip->ecc.read_oob(chip, page); - - err = do_dma(nfc, DMA_FROM_DEVICE, NFC_READ, buf, len, page); - if (err) - return err; - - res = decode_error_report(chip); - if (res < 0) { - chip->ecc.read_oob_raw(chip, page); - res = check_erased_page(chip, buf); - } - - return res; -} - -static int tango_write_page(struct nand_chip *chip, const u8 *buf, - int oob_required, int page) -{ - struct mtd_info *mtd = nand_to_mtd(chip); - struct tango_nfc *nfc = to_tango_nfc(chip->controller); - const struct nand_sdr_timings *timings; - int err, len = mtd->writesize; - u8 status; - - /* Calling tango_write_oob() would send PAGEPROG twice */ - if (oob_required) - return -ENOTSUPP; - - tango_select_target(chip, chip->cur_cs); - writel_relaxed(0xffffffff, nfc->mem_base + METADATA); - err = do_dma(nfc, DMA_TO_DEVICE, NFC_WRITE, buf, len, page); - if (err) - return err; - - timings = nand_get_sdr_timings(nand_get_interface_config(chip)); - err = tango_waitrdy(chip, PSEC_TO_MSEC(timings->tR_max)); - if (err) - return err; - - err = nand_status_op(chip, &status); - if (err) - return err; - - return (status & NAND_STATUS_FAIL) ? -EIO : 0; -} - -static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos) -{ - *pos += len; - - if (!*buf) { - /* skip over "len" bytes */ - nand_change_read_column_op(chip, *pos, NULL, 0, false); - } else { - struct tango_chip *tchip = to_tango_chip(chip); - - ioread8_rep(tchip->base + PBUS_DATA, *buf, len); - *buf += len; - } -} - -static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos) -{ - *pos += len; - - if (!*buf) { - /* skip over "len" bytes */ - nand_change_write_column_op(chip, *pos, NULL, 0, false); - } else { - struct tango_chip *tchip = to_tango_chip(chip); - - iowrite8_rep(tchip->base + PBUS_DATA, *buf, len); - *buf += len; - } -} - -/* - * Physical page layout (not drawn to scale) - * - * NB: Bad Block Marker area splits PKT_N in two (N1, N2). - * - * +---+-----------------+-------+-----+-----------+-----+----+-------+ - * | M | PKT_0 | ECC_0 | ... | N1 | BBM | N2 | ECC_N | - * +---+-----------------+-------+-----+-----------+-----+----+-------+ - * - * Logical page layout: - * - * +-----+---+-------+-----+-------+ - * oob = | BBM | M | ECC_0 | ... | ECC_N | - * +-----+---+-------+-----+-------+ - * - * +-----------------+-----+-----------------+ - * buf = | PKT_0 | ... | PKT_N | - * +-----------------+-----+-----------------+ - */ -static void raw_read(struct nand_chip *chip, u8 *buf, u8 *oob) -{ - struct mtd_info *mtd = nand_to_mtd(chip); - u8 *oob_orig = oob; - const int page_size = mtd->writesize; - const int ecc_size = chip->ecc.bytes; - const int pkt_size = chip->ecc.size; - int pos = 0; /* position within physical page */ - int rem = page_size; /* bytes remaining until BBM area */ - - if (oob) - oob += BBM_SIZE; - - aux_read(chip, &oob, METADATA_SIZE, &pos); - - while (rem > pkt_size) { - aux_read(chip, &buf, pkt_size, &pos); - aux_read(chip, &oob, ecc_size, &pos); - rem = page_size - pos; - } - - aux_read(chip, &buf, rem, &pos); - aux_read(chip, &oob_orig, BBM_SIZE, &pos); - aux_read(chip, &buf, pkt_size - rem, &pos); - aux_read(chip, &oob, ecc_size, &pos); -} - -static void raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob) -{ - struct mtd_info *mtd = nand_to_mtd(chip); - const u8 *oob_orig = oob; - const int page_size = mtd->writesize; - const int ecc_size = chip->ecc.bytes; - const int pkt_size = chip->ecc.size; - int pos = 0; /* position within physical page */ - int rem = page_size; /* bytes remaining until BBM area */ - - if (oob) - oob += BBM_SIZE; - - aux_write(chip, &oob, METADATA_SIZE, &pos); - - while (rem > pkt_size) { - aux_write(chip, &buf, pkt_size, &pos); - aux_write(chip, &oob, ecc_size, &pos); - rem = page_size - pos; - } - - aux_write(chip, &buf, rem, &pos); - aux_write(chip, &oob_orig, BBM_SIZE, &pos); - aux_write(chip, &buf, pkt_size - rem, &pos); - aux_write(chip, &oob, ecc_size, &pos); -} - -static int tango_read_page_raw(struct nand_chip *chip, u8 *buf, - int oob_required, int page) -{ - tango_select_target(chip, chip->cur_cs); - nand_read_page_op(chip, page, 0, NULL, 0); - raw_read(chip, buf, chip->oob_poi); - return 0; -} - -static int tango_write_page_raw(struct nand_chip *chip, const u8 *buf, - int oob_required, int page) -{ - tango_select_target(chip, chip->cur_cs); - nand_prog_page_begin_op(chip, page, 0, NULL, 0); - raw_write(chip, buf, chip->oob_poi); - return nand_prog_page_end_op(chip); -} - -static int tango_read_oob(struct nand_chip *chip, int page) -{ - tango_select_target(chip, chip->cur_cs); - nand_read_page_op(chip, page, 0, NULL, 0); - raw_read(chip, NULL, chip->oob_poi); - return 0; -} - -static int tango_write_oob(struct nand_chip *chip, int page) -{ - tango_select_target(chip, chip->cur_cs); - nand_prog_page_begin_op(chip, page, 0, NULL, 0); - raw_write(chip, NULL, chip->oob_poi); - return nand_prog_page_end_op(chip); -} - -static int oob_ecc(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_ecc_ctrl *ecc = &chip->ecc; - - if (idx >= ecc->steps) - return -ERANGE; - - res->offset = BBM_SIZE + METADATA_SIZE + ecc->bytes * idx; - res->length = ecc->bytes; - - return 0; -} - -static int oob_free(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) -{ - return -ERANGE; /* no free space in spare area */ -} - -static const struct mtd_ooblayout_ops tango_nand_ooblayout_ops = { - .ecc = oob_ecc, - .free = oob_free, -}; - -static u32 to_ticks(int kHz, int ps) -{ - return DIV_ROUND_UP_ULL((u64)kHz * ps, NSEC_PER_SEC); -} - -static int tango_set_timings(struct nand_chip *chip, int csline, - const struct nand_interface_config *conf) -{ - const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf); - struct tango_nfc *nfc = to_tango_nfc(chip->controller); - struct tango_chip *tchip = to_tango_chip(chip); - u32 Trdy, Textw, Twc, Twpw, Tacc, Thold, Trpw, Textr; - int kHz = nfc->freq_kHz; - - if (IS_ERR(sdr)) - return PTR_ERR(sdr); - - if (csline == NAND_DATA_IFACE_CHECK_ONLY) - return 0; - - Trdy = to_ticks(kHz, sdr->tCEA_max - sdr->tREA_max); - Textw = to_ticks(kHz, sdr->tWB_max); - Twc = to_ticks(kHz, sdr->tWC_min); - Twpw = to_ticks(kHz, sdr->tWC_min - sdr->tWP_min); - - Tacc = to_ticks(kHz, sdr->tREA_max); - Thold = to_ticks(kHz, sdr->tREH_min); - Trpw = to_ticks(kHz, sdr->tRC_min - sdr->tREH_min); - Textr = to_ticks(kHz, sdr->tRHZ_max); - - tchip->timing1 = TIMING(Trdy, Textw, Twc, Twpw); - tchip->timing2 = TIMING(Tacc, Thold, Trpw, Textr); - - return 0; -} - -static int tango_attach_chip(struct nand_chip *chip) -{ - struct nand_ecc_ctrl *ecc = &chip->ecc; - - ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; - ecc->algo = NAND_ECC_ALGO_BCH; - ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE); - - ecc->read_page_raw = tango_read_page_raw; - ecc->write_page_raw = tango_write_page_raw; - ecc->read_page = tango_read_page; - ecc->write_page = tango_write_page; - ecc->read_oob = tango_read_oob; - ecc->write_oob = tango_write_oob; - - return 0; -} - -static const struct nand_controller_ops tango_controller_ops = { - .attach_chip = tango_attach_chip, - .setup_interface = tango_set_timings, - .exec_op = tango_exec_op, -}; - -static int chip_init(struct device *dev, struct device_node *np) -{ - u32 cs; - int err, res; - struct mtd_info *mtd; - struct nand_chip *chip; - struct tango_chip *tchip; - struct nand_ecc_ctrl *ecc; - struct tango_nfc *nfc = dev_get_drvdata(dev); - - tchip = devm_kzalloc(dev, sizeof(*tchip), GFP_KERNEL); - if (!tchip) - return -ENOMEM; - - res = of_property_count_u32_elems(np, "reg"); - if (res < 0) - return res; - - if (res != 1) - return -ENOTSUPP; /* Multi-CS chips are not supported */ - - err = of_property_read_u32_index(np, "reg", 0, &cs); - if (err) - return err; - - if (cs >= MAX_CS) - return -EINVAL; - - chip = &tchip->nand_chip; - ecc = &chip->ecc; - mtd = nand_to_mtd(chip); - - chip->options = NAND_USES_DMA | - NAND_NO_SUBPAGE_WRITE | - NAND_WAIT_TCCS; - chip->controller = &nfc->hw; - tchip->base = nfc->pbus_base + (cs * 256); - - nand_set_flash_node(chip, np); - mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops); - mtd->dev.parent = dev; - - err = nand_scan(chip, 1); - if (err) - return err; - - tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE); - tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength); - tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength); - tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE); - - err = mtd_device_register(mtd, NULL, 0); - if (err) { - nand_cleanup(chip); - return err; - } - - nfc->chips[cs] = tchip; - - return 0; -} - -static int tango_nand_remove(struct platform_device *pdev) -{ - struct tango_nfc *nfc = platform_get_drvdata(pdev); - struct nand_chip *chip; - int cs, ret; - - dma_release_channel(nfc->chan); - - for (cs = 0; cs < MAX_CS; ++cs) { - if (nfc->chips[cs]) { - chip = &nfc->chips[cs]->nand_chip; - ret = mtd_device_unregister(nand_to_mtd(chip)); - WARN_ON(ret); - nand_cleanup(chip); - } - } - - return 0; -} - -static int tango_nand_probe(struct platform_device *pdev) -{ - int err; - struct clk *clk; - struct resource *res; - struct tango_nfc *nfc; - struct device_node *np; - - nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); - if (!nfc) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - nfc->reg_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(nfc->reg_base)) - return PTR_ERR(nfc->reg_base); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - nfc->mem_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(nfc->mem_base)) - return PTR_ERR(nfc->mem_base); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 2); - nfc->pbus_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(nfc->pbus_base)) - return PTR_ERR(nfc->pbus_base); - - writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE); - - clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(clk)) - return PTR_ERR(clk); - - nfc->chan = dma_request_chan(&pdev->dev, "rxtx"); - if (IS_ERR(nfc->chan)) - return PTR_ERR(nfc->chan); - - platform_set_drvdata(pdev, nfc); - nand_controller_init(&nfc->hw); - nfc->hw.ops = &tango_controller_ops; - nfc->freq_kHz = clk_get_rate(clk) / 1000; - - for_each_child_of_node(pdev->dev.of_node, np) { - err = chip_init(&pdev->dev, np); - if (err) { - tango_nand_remove(pdev); - of_node_put(np); - return err; - } - } - - return 0; -} - -static const struct of_device_id tango_nand_ids[] = { - { .compatible = "sigma,smp8758-nand" }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, tango_nand_ids); - -static struct platform_driver tango_nand_driver = { - .probe = tango_nand_probe, - .remove = tango_nand_remove, - .driver = { - .name = "tango-nand", - .of_match_table = tango_nand_ids, - }, -}; - -module_platform_driver(tango_nand_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Sigma Designs"); -MODULE_DESCRIPTION("Tango4 NAND Flash controller driver"); From 073abfa7ea9a5b0537d6f92b42baedaf82a04c53 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sun, 24 Jan 2021 08:39:55 +0100 Subject: [PATCH 15/23] mtd: rawnand: intel: Fix an error handling path in 'ebu_dma_start()' If 'dmaengine_prep_slave_single()' fails, we must undo a previous 'dma_map_single()' call, as already done in all the other error handling paths of this function. Fixes: 0b1039f016e8 ("mtd: rawnand: Add NAND controller support on Intel LGM SoC") Signed-off-by: Christophe JAILLET Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20210124073955.728797-1-christophe.jaillet@wanadoo.fr --- drivers/mtd/nand/raw/intel-nand-controller.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/intel-nand-controller.c b/drivers/mtd/nand/raw/intel-nand-controller.c index fdb112e8a90d..4c08e9f9fbbe 100644 --- a/drivers/mtd/nand/raw/intel-nand-controller.c +++ b/drivers/mtd/nand/raw/intel-nand-controller.c @@ -318,8 +318,10 @@ static int ebu_dma_start(struct ebu_nand_controller *ebu_host, u32 dir, } tx = dmaengine_prep_slave_single(chan, buf_dma, len, dir, flags); - if (!tx) - return -ENXIO; + if (!tx) { + ret = -ENXIO; + goto err_unmap; + } tx->callback = callback; tx->callback_param = ebu_host; From abdf5a5ef9652bad4d58058bc22ddf23543ba3e1 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Fri, 2 Oct 2020 14:17:59 +0900 Subject: [PATCH 16/23] mtd: spi-nor: sfdp: Fix wrong erase type bitmask for overlaid region At the time spi_nor_region_check_overlay() is called, the erase types are sorted in ascending order of erase size. The 'erase_type' should be masked with 'BIT(erase[i].idx)' instead of 'BIT(i)'. Fixes: b038e8e3be72 ("mtd: spi-nor: parse SFDP Sector Map Parameter Table") Cc: stable@vger.kernel.org Signed-off-by: Takahiro Kuwano [ta: Add Fixes tag and Cc to stable] Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/fd90c40d5b626a1319a78fc2bcee79a8871d4d57.1601612872.git.Takahiro.Kuwano@infineon.com --- drivers/mtd/spi-nor/sfdp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 6ee7719e5903..b3d44bd19a2b 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -788,7 +788,7 @@ spi_nor_region_check_overlay(struct spi_nor_erase_region *region, int i; for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { - if (!(erase_type & BIT(i))) + if (!(erase[i].size && erase_type & BIT(erase[i].idx))) continue; if (region->size & erase[i].size_mask) { spi_nor_region_mark_overlay(region); From 9166f4af32db74e1544a2149aef231ff24515ea3 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Fri, 2 Oct 2020 14:18:00 +0900 Subject: [PATCH 17/23] mtd: spi-nor: sfdp: Fix last erase region marking The place of spi_nor_region_mark_end() must be moved, because 'i' is re-used for the index of erase[]. Fixes: b038e8e3be72 ("mtd: spi-nor: parse SFDP Sector Map Parameter Table") Cc: stable@vger.kernel.org Signed-off-by: Takahiro Kuwano [ta: Add Fixes tag and Cc to stable] Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/02ce8d84b7989ebee33382f6494df53778dd508e.1601612872.git.Takahiro.Kuwano@infineon.com --- drivers/mtd/spi-nor/sfdp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index b3d44bd19a2b..25142ec4737b 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -858,6 +858,7 @@ spi_nor_init_non_uniform_erase_map(struct spi_nor *nor, offset = (region[i].offset & ~SNOR_ERASE_FLAGS_MASK) + region[i].size; } + spi_nor_region_mark_end(®ion[i - 1]); save_uniform_erase_type = map->uniform_erase_type; map->uniform_erase_type = spi_nor_sort_erase_mask(map, @@ -881,8 +882,6 @@ spi_nor_init_non_uniform_erase_map(struct spi_nor *nor, if (!(regions_erase_type & BIT(erase[i].idx))) spi_nor_set_erase_type(&erase[i], 0, 0xFF); - spi_nor_region_mark_end(®ion[i - 1]); - return 0; } From 969b276718de37dfe66fce3a5633f611e8cd58fd Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Fri, 2 Oct 2020 14:18:01 +0900 Subject: [PATCH 18/23] mtd: spi-nor: core: Fix erase type discovery for overlaid region In case of overlaid regions in which their biggest erase size command overpasses in size the region's size, only the non-overlaid portion of the sector gets erased. For example, if a Sector Erase command is applied to a 256-kB range that is overlaid by 4-kB sectors, the overlaid 4-kB sectors are not affected by the erase. For overlaid regions, 'region->size' is assigned to 'cmd->size' later in spi_nor_init_erase_cmd(), so 'erase->size' can be greater than 'len'. Fixes: 5390a8df769e ("mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories") Cc: stable@vger.kernel.org Signed-off-by: Takahiro Kuwano [ta: Update commit description, add Fixes tag and Cc to stable] Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/fa5d8b944a5cca488ac54ba37c95e775ac2deb34.1601612872.git.Takahiro.Kuwano@infineon.com --- drivers/mtd/spi-nor/core.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 20df44b753da..d25d8b0a482e 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1364,14 +1364,15 @@ spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map, erase = &map->erase_type[i]; + /* Alignment is not mandatory for overlaid regions */ + if (region->offset & SNOR_OVERLAID_REGION && + region->size <= len) + return erase; + /* Don't erase more than what the user has asked for. */ if (erase->size > len) continue; - /* Alignment is not mandatory for overlaid regions */ - if (region->offset & SNOR_OVERLAID_REGION) - return erase; - spi_nor_div_by_erase_size(erase, addr, &rem); if (rem) continue; From 58fa22f68fcaff20ce4d08a6adffa64f65ccd37d Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Fri, 2 Oct 2020 14:18:02 +0900 Subject: [PATCH 19/23] mtd: spi-nor: core: Add erase size check for erase command initialization Even if erase type is same as previous region, erase size can be different if the previous region is overlaid region. Since 'region->size' is assigned to 'cmd->size' for overlaid region, comparing 'erase->size' and 'cmd->size' can detect previous overlaid region. Fixes: 5390a8df769e ("mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories") Cc: stable@vger.kernel.org Signed-off-by: Takahiro Kuwano [ta: Add Fixes tag and Cc to stable] Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/13d47e8d8991b8a7fd8cc7b9e2a5319c56df35cc.1601612872.git.Takahiro.Kuwano@infineon.com --- drivers/mtd/spi-nor/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index d25d8b0a482e..b17faccc95c4 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1516,6 +1516,7 @@ static int spi_nor_init_erase_cmd_list(struct spi_nor *nor, goto destroy_erase_cmd_list; if (prev_erase != erase || + erase->size != cmd->size || region->offset & SNOR_OVERLAID_REGION) { cmd = spi_nor_init_erase_cmd(region, erase); if (IS_ERR(cmd)) { From a7a5acba0e06b8f9923faa1a726f0ac1380b719a Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 21 Jan 2021 13:05:45 +0200 Subject: [PATCH 20/23] mtd: spi-nor: Add Global Block Unlock command The Global Block Unlock command has different names depending on the manufacturer, but always the same command value: 0x98. Macronix's MX25U12835F names it Gang Block Unlock, Winbond's W25Q128FV names it Global Block Unlock and Microchip's SST26VF064B names it Global Block Protection Unlock. Used in the Individual Block Protection mode, which is mutually exclusive with the Block Protection mode (BP0-3). Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Reviewed-by: Michael Walle Link: https://lore.kernel.org/r/20210121110546.382633-1-tudor.ambarus@microchip.com --- drivers/mtd/spi-nor/core.c | 37 +++++++++++++++++++++++++++++++++++++ drivers/mtd/spi-nor/core.h | 1 + include/linux/mtd/spi-nor.h | 1 + 3 files changed, 39 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index b17faccc95c4..47ded0977056 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -853,6 +853,43 @@ int spi_nor_wait_till_ready(struct spi_nor *nor) DEFAULT_READY_WAIT_JIFFIES); } +/** + * spi_nor_global_block_unlock() - Unlock Global Block Protection. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_global_block_unlock(struct spi_nor *nor) +{ + int ret; + + ret = spi_nor_write_enable(nor); + if (ret) + return ret; + + if (nor->spimem) { + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_GBULK, 0), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); + + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + + ret = spi_mem_exec_op(nor->spimem, &op); + } else { + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK, + NULL, 0); + } + + if (ret) { + dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret); + return ret; + } + + return spi_nor_wait_till_ready(nor); +} + /** * spi_nor_write_sr() - Write the Status Register. * @nor: pointer to 'struct spi_nor'. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index d631ee299de3..eb26796db026 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -434,6 +434,7 @@ int spi_nor_write_disable(struct spi_nor *nor); int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); int spi_nor_write_ear(struct spi_nor *nor, u8 ear); int spi_nor_wait_till_ready(struct spi_nor *nor); +int spi_nor_global_block_unlock(struct spi_nor *nor); int spi_nor_lock_and_prep(struct spi_nor *nor); void spi_nor_unlock_and_unprep(struct spi_nor *nor); int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d13958de6d8a..a0d572855444 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -53,6 +53,7 @@ #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */ #define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */ #define SPINOR_OP_SRST 0x99 /* Software Reset */ +#define SPINOR_OP_GBULK 0x98 /* Global Block Unlock */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */ From 75386810d3a61f4bb9e180774291454f7235b8b3 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 21 Jan 2021 13:05:46 +0200 Subject: [PATCH 21/23] mtd: spi-nor: sst: Add support for Global Unlock on sst26vf Even if sst26vf shares the SPINOR_OP_GBULK opcode with Macronix (ex. MX25U12835F) and Winbound (ex. W25Q128FV), it has its own Individual Block Protection scheme, which is also capable to read-lock individual parameter blocks. Thus the sst26vf's Individual Block Protection scheme will reside in the sst.c manufacturer driver. Add support to unlock the entire flash memory. The device is write-protected by default after a power-on reset cycle (volatile software protection), in order to avoid inadvertent writes during power-up. Could do an erase, write, read back, and compare when MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle Link: https://lore.kernel.org/r/20210121110546.382633-2-tudor.ambarus@microchip.com --- drivers/mtd/spi-nor/core.c | 2 +- drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/sst.c | 52 ++++++++++++++++++++++++++++++++++++-- 3 files changed, 52 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 47ded0977056..0522304f52fa 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -465,7 +465,7 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) * * Return: 0 on success, -errno otherwise. */ -static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) +int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) { int ret; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index eb26796db026..4a3f7f150b5d 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -441,6 +441,7 @@ int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor); int spi_nor_read_sr(struct spi_nor *nor, u8 *sr); +int spi_nor_read_cr(struct spi_nor *nor, u8 *cr); int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len); int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1); diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c index 00e48da0744a..980f4c09c91d 100644 --- a/drivers/mtd/spi-nor/sst.c +++ b/drivers/mtd/spi-nor/sst.c @@ -8,6 +8,53 @@ #include "core.h" +#define SST26VF_CR_BPNV BIT(3) + +static int sst26vf_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) +{ + return -EOPNOTSUPP; +} + +static int sst26vf_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) +{ + int ret; + + /* We only support unlocking the entire flash array. */ + if (ofs != 0 || len != nor->params->size) + return -EINVAL; + + ret = spi_nor_read_cr(nor, nor->bouncebuf); + if (ret) + return ret; + + if (!(nor->bouncebuf[0] & SST26VF_CR_BPNV)) { + dev_dbg(nor->dev, "Any block has been permanently locked\n"); + return -EINVAL; + } + + return spi_nor_global_block_unlock(nor); +} + +static int sst26vf_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) +{ + return -EOPNOTSUPP; +} + +static const struct spi_nor_locking_ops sst26vf_locking_ops = { + .lock = sst26vf_lock, + .unlock = sst26vf_unlock, + .is_locked = sst26vf_is_locked, +}; + +static void sst26vf_default_init(struct spi_nor *nor) +{ + nor->params->locking_ops = &sst26vf_locking_ops; +} + +static const struct spi_nor_fixups sst26vf_fixups = { + .default_init = sst26vf_default_init, +}; + static const struct flash_info sst_parts[] = { /* SST -- large erase sizes are "overlays", "sectors" are 4K */ { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, @@ -39,8 +86,9 @@ static const struct flash_info sst_parts[] = { { "sst26vf016b", INFO(0xbf2641, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ) }, { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, - SECT_4K | SPI_NOR_DUAL_READ | - SPI_NOR_QUAD_READ) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) + .fixups = &sst26vf_fixups }, }; static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, From 6418522022c706fd867b00b2571edba48b8fa8c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 11 Feb 2021 23:04:25 +0100 Subject: [PATCH 22/23] dt-bindings: mtd: move partition binding to its own file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Single partition binding is quite common and may be: 1. Used by multiple parsers 2. Extended for more specific cases Move it to separated file to avoid code duplication. Signed-off-by: Rafał Miłecki Reviewed-by: Rob Herring Signed-off-by: Richard Weinberger --- .../mtd/partitions/fixed-partitions.yaml | 33 +------------ .../bindings/mtd/partitions/partition.yaml | 47 +++++++++++++++++++ 2 files changed, 48 insertions(+), 32 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/partitions/partition.yaml diff --git a/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml index 6d4a3450e064..ea4cace6a955 100644 --- a/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml +++ b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml @@ -27,38 +27,7 @@ properties: patternProperties: "@[0-9a-f]+$": - description: node describing a single flash partition - type: object - - properties: - reg: - description: partition's offset and size within the flash - maxItems: 1 - - label: - description: The label / name for this partition. If omitted, the label - is taken from the node name (excluding the unit address). - - read-only: - description: This parameter, if present, is a hint that this partition - should only be mounted read-only. This is usually used for flash - partitions containing early-boot firmware images or data which should - not be clobbered. - type: boolean - - lock: - description: Do not unlock the partition at initialization time (not - supported on all devices) - type: boolean - - slc-mode: - description: This parameter, if present, allows one to emulate SLC mode - on a partition attached to an MLC NAND thus making this partition - immune to paired-pages corruptions - type: boolean - - required: - - reg + $ref: "partition.yaml#" required: - "#address-cells" diff --git a/Documentation/devicetree/bindings/mtd/partitions/partition.yaml b/Documentation/devicetree/bindings/mtd/partitions/partition.yaml new file mode 100644 index 000000000000..e1ac08064425 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/partitions/partition.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/partitions/partition.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Partition + +description: | + This binding describes a single flash partition. Each partition must have its + relative offset and size specified. Depending on partition function extra + properties can be used. + +maintainers: + - Rafał Miłecki + +properties: + reg: + description: partition's offset and size within the flash + maxItems: 1 + + label: + description: The label / name for this partition. If omitted, the label + is taken from the node name (excluding the unit address). + + read-only: + description: This parameter, if present, is a hint that this partition + should only be mounted read-only. This is usually used for flash + partitions containing early-boot firmware images or data which should + not be clobbered. + type: boolean + + lock: + description: Do not unlock the partition at initialization time (not + supported on all devices) + type: boolean + + slc-mode: + description: This parameter, if present, allows one to emulate SLC mode + on a partition attached to an MLC NAND thus making this partition + immune to paired-pages corruptions + type: boolean + +required: + - reg + +additionalProperties: true From 6e9dff6fe3fbc452f16566e4a7e293b0decefdba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 11 Feb 2021 23:04:26 +0100 Subject: [PATCH 23/23] dt-bindings: mtd: add binding for BCM4908 partitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM4908 uses fixed partitions layout but function of some partitions may vary. Some devices use multiple firmware partitions and those partitions should be marked to let system discover their purpose. Signed-off-by: Rafał Miłecki Signed-off-by: Richard Weinberger --- .../partitions/brcm,bcm4908-partitions.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/partitions/brcm,bcm4908-partitions.yaml diff --git a/Documentation/devicetree/bindings/mtd/partitions/brcm,bcm4908-partitions.yaml b/Documentation/devicetree/bindings/mtd/partitions/brcm,bcm4908-partitions.yaml new file mode 100644 index 000000000000..7b113e5e3421 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/partitions/brcm,bcm4908-partitions.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/partitions/brcm,bcm4908-partitions.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM4908 partitioning + +description: | + Broadcom BCM4908 CFE bootloader supports two firmware partitions. One is used + for regular booting, the other is treated as fallback. + + This binding allows defining all fixed partitions and marking those containing + firmware. System can use that information e.g. for booting or flashing + purposes. + +maintainers: + - Rafał Miłecki + +properties: + compatible: + const: brcm,bcm4908-partitions + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + +patternProperties: + "^partition@[0-9a-f]+$": + $ref: "partition.yaml#" + properties: + compatible: + const: brcm,bcm4908-firmware + unevaluatedProperties: false + +required: + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + partitions { + compatible = "brcm,bcm4908-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "cferom"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + compatible = "brcm,bcm4908-firmware"; + reg = <0x100000 0xf00000>; + }; + + partition@1000000 { + compatible = "brcm,bcm4908-firmware"; + reg = <0x1000000 0xf00000>; + }; + + partition@1f00000 { + label = "calibration"; + reg = <0x1f00000 0x100000>; + }; + };