perf/x86/amd/ibs: Add bitfield definitions in new <asm/amd-ibs.h> header
Add <asm/amd-ibs.h> with bitfield definitions for IBS MSRs, and demonstrate usage within the driver. Also move 'struct perf_ibs_data' where it can be shared with the perf tool that will soon be using it. No functional changes. Signed-off-by: Kim Phillips <kim.phillips@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20210817221048.88063-9-kim.phillips@amd.com
This commit is contained in:
Kim Phillips
Ingo Molnar
Родитель
05485745ad
Коммит
6a371bafe6
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@ -26,6 +26,7 @@ static u32 ibs_caps;
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#include <linux/hardirq.h>
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#include <asm/nmi.h>
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#include <asm/amd-ibs.h>
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#define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
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#define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT
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@ -100,15 +101,6 @@ struct perf_ibs {
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u64 (*get_count)(u64 config);
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};
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struct perf_ibs_data {
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u32 size;
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union {
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u32 data[0]; /* data buffer starts here */
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u32 caps;
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};
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u64 regs[MSR_AMD64_IBS_REG_COUNT_MAX];
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};
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static int
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perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period)
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{
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@ -329,11 +321,14 @@ static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
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static u64 get_ibs_fetch_count(u64 config)
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{
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return (config & IBS_FETCH_CNT) >> 12;
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union ibs_fetch_ctl fetch_ctl = (union ibs_fetch_ctl)config;
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return fetch_ctl.fetch_cnt << 4;
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}
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static u64 get_ibs_op_count(u64 config)
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{
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union ibs_op_ctl op_ctl = (union ibs_op_ctl)config;
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u64 count = 0;
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/*
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@ -341,12 +336,12 @@ static u64 get_ibs_op_count(u64 config)
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* and the lower 7 bits of CurCnt are randomized.
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* Otherwise CurCnt has the full 27-bit current counter value.
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*/
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if (config & IBS_OP_VAL) {
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count = (config & IBS_OP_MAX_CNT) << 4;
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if (op_ctl.op_val) {
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count = op_ctl.opmaxcnt << 4;
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if (ibs_caps & IBS_CAPS_OPCNTEXT)
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count += config & IBS_OP_MAX_CNT_EXT_MASK;
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count += op_ctl.opmaxcnt_ext << 20;
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} else if (ibs_caps & IBS_CAPS_RDWROPCNT) {
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count = (config & IBS_OP_CUR_CNT) >> 32;
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count = op_ctl.opcurcnt;
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}
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return count;
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@ -0,0 +1,132 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* From PPR Vol 1 for AMD Family 19h Model 01h B1
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* 55898 Rev 0.35 - Feb 5, 2021
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*/
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#include <asm/msr-index.h>
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/*
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* IBS Hardware MSRs
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*/
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/* MSR 0xc0011030: IBS Fetch Control */
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union ibs_fetch_ctl {
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__u64 val;
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struct {
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__u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
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fetch_cnt:16, /* 16-31: instruction fetch count */
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fetch_lat:16, /* 32-47: instruction fetch latency */
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fetch_en:1, /* 48: instruction fetch enable */
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fetch_val:1, /* 49: instruction fetch valid */
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fetch_comp:1, /* 50: instruction fetch complete */
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ic_miss:1, /* 51: i-cache miss */
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phy_addr_valid:1,/* 52: physical address valid */
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l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size
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* (needs IbsPhyAddrValid) */
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l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */
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l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */
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rand_en:1, /* 57: random tagging enable */
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fetch_l2_miss:1,/* 58: L2 miss for sampled fetch
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* (needs IbsFetchComp) */
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reserved:5; /* 59-63: reserved */
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};
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};
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/* MSR 0xc0011033: IBS Execution Control */
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union ibs_op_ctl {
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__u64 val;
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struct {
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__u64 opmaxcnt:16, /* 0-15: periodic op max. count */
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reserved0:1, /* 16: reserved */
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op_en:1, /* 17: op sampling enable */
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op_val:1, /* 18: op sample valid */
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cnt_ctl:1, /* 19: periodic op counter control */
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opmaxcnt_ext:7, /* 20-26: upper 7 bits of periodic op maximum count */
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reserved1:5, /* 27-31: reserved */
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opcurcnt:27, /* 32-58: periodic op counter current count */
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reserved2:5; /* 59-63: reserved */
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};
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};
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/* MSR 0xc0011035: IBS Op Data 2 */
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union ibs_op_data {
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__u64 val;
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struct {
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__u64 comp_to_ret_ctr:16, /* 0-15: op completion to retire count */
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tag_to_ret_ctr:16, /* 15-31: op tag to retire count */
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reserved1:2, /* 32-33: reserved */
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op_return:1, /* 34: return op */
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op_brn_taken:1, /* 35: taken branch op */
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op_brn_misp:1, /* 36: mispredicted branch op */
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op_brn_ret:1, /* 37: branch op retired */
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op_rip_invalid:1, /* 38: RIP is invalid */
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op_brn_fuse:1, /* 39: fused branch op */
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op_microcode:1, /* 40: microcode op */
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reserved2:23; /* 41-63: reserved */
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};
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};
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/* MSR 0xc0011036: IBS Op Data 2 */
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union ibs_op_data2 {
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__u64 val;
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struct {
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__u64 data_src:3, /* 0-2: data source */
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reserved0:1, /* 3: reserved */
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rmt_node:1, /* 4: destination node */
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cache_hit_st:1, /* 5: cache hit state */
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reserved1:57; /* 5-63: reserved */
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};
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};
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/* MSR 0xc0011037: IBS Op Data 3 */
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union ibs_op_data3 {
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__u64 val;
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struct {
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__u64 ld_op:1, /* 0: load op */
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st_op:1, /* 1: store op */
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dc_l1tlb_miss:1, /* 2: data cache L1TLB miss */
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dc_l2tlb_miss:1, /* 3: data cache L2TLB hit in 2M page */
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dc_l1tlb_hit_2m:1, /* 4: data cache L1TLB hit in 2M page */
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dc_l1tlb_hit_1g:1, /* 5: data cache L1TLB hit in 1G page */
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dc_l2tlb_hit_2m:1, /* 6: data cache L2TLB hit in 2M page */
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dc_miss:1, /* 7: data cache miss */
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dc_mis_acc:1, /* 8: misaligned access */
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reserved:4, /* 9-12: reserved */
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dc_wc_mem_acc:1, /* 13: write combining memory access */
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dc_uc_mem_acc:1, /* 14: uncacheable memory access */
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dc_locked_op:1, /* 15: locked operation */
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dc_miss_no_mab_alloc:1, /* 16: DC miss with no MAB allocated */
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dc_lin_addr_valid:1, /* 17: data cache linear address valid */
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dc_phy_addr_valid:1, /* 18: data cache physical address valid */
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dc_l2_tlb_hit_1g:1, /* 19: data cache L2 hit in 1GB page */
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l2_miss:1, /* 20: L2 cache miss */
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sw_pf:1, /* 21: software prefetch */
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op_mem_width:4, /* 22-25: load/store size in bytes */
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op_dc_miss_open_mem_reqs:6, /* 26-31: outstanding mem reqs on DC fill */
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dc_miss_lat:16, /* 32-47: data cache miss latency */
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tlb_refill_lat:16; /* 48-63: L1 TLB refill latency */
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};
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};
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/* MSR 0xc001103c: IBS Fetch Control Extended */
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union ic_ibs_extd_ctl {
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__u64 val;
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struct {
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__u64 itlb_refill_lat:16, /* 0-15: ITLB Refill latency for sampled fetch */
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reserved:48; /* 16-63: reserved */
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};
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};
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/*
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* IBS driver related
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*/
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struct perf_ibs_data {
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u32 size;
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union {
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u32 data[0]; /* data buffer starts here */
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u32 caps;
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};
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u64 regs[MSR_AMD64_IBS_REG_COUNT_MAX];
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};
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