net: aquantia: replace AQ_HW_WAIT_FOR with readx_poll_timeout_atomic
David noticed the original define was hiding 'err' variable reference. Thats confusing and counterintuitive. Andrew noted the whole macro could be replaced with standard readx_poll kernel macro. This makes code more readable. Signed-off-by: Nikita Danilov <nikita.danilov@aquantia.com> Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Nikita Danilov
David S. Miller
Родитель
8006e3730b
Коммит
6a7f227731
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@ -14,6 +14,8 @@
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#ifndef AQ_HW_UTILS_H
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#define AQ_HW_UTILS_H
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#include <linux/iopoll.h>
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#include "aq_common.h"
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#ifndef HIDWORD
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@ -23,18 +25,6 @@
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#define AQ_HW_SLEEP(_US_) mdelay(_US_)
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#define AQ_HW_WAIT_FOR(_B_, _US_, _N_) \
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do { \
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unsigned int AQ_HW_WAIT_FOR_i; \
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for (AQ_HW_WAIT_FOR_i = _N_; (!(_B_)) && (AQ_HW_WAIT_FOR_i);\
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--AQ_HW_WAIT_FOR_i) {\
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udelay(_US_); \
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} \
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if (!AQ_HW_WAIT_FOR_i) {\
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err = -ETIME; \
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} \
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} while (0)
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#define aq_pr_err(...) pr_err(AQ_CFG_DRV_NAME ": " __VA_ARGS__)
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#define aq_pr_trace(...) pr_info(AQ_CFG_DRV_NAME ": " __VA_ARGS__)
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@ -85,6 +85,7 @@ const struct aq_hw_caps_s hw_atl_a0_caps_aqc109 = {
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static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
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{
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int err = 0;
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u32 val;
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hw_atl_glb_glb_reg_res_dis_set(self, 1U);
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hw_atl_pci_pci_reg_res_dis_set(self, 0U);
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@ -95,7 +96,9 @@ static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
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hw_atl_glb_soft_res_set(self, 1);
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/* check 10 times by 1ms */
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AQ_HW_WAIT_FOR(hw_atl_glb_soft_res_get(self) == 0, 1000U, 10U);
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err = readx_poll_timeout_atomic(hw_atl_glb_soft_res_get,
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self, val, val == 0,
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1000U, 10000U);
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if (err < 0)
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goto err_exit;
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@ -103,7 +106,9 @@ static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
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hw_atl_itr_res_irq_set(self, 1U);
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/* check 10 times by 1ms */
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AQ_HW_WAIT_FOR(hw_atl_itr_res_irq_get(self) == 0, 1000U, 10U);
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err = readx_poll_timeout_atomic(hw_atl_itr_res_irq_get,
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self, val, val == 0,
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1000U, 10000U);
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if (err < 0)
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goto err_exit;
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@ -181,6 +186,7 @@ static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self,
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int err = 0;
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unsigned int i = 0U;
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unsigned int addr = 0U;
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u32 val;
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for (i = 10, addr = 0U; i--; ++addr) {
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u32 key_data = cfg->is_rss ?
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@ -188,8 +194,9 @@ static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self,
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hw_atl_rpf_rss_key_wr_data_set(self, key_data);
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hw_atl_rpf_rss_key_addr_set(self, addr);
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hw_atl_rpf_rss_key_wr_en_set(self, 1U);
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AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
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1000U, 10U);
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err = readx_poll_timeout_atomic(hw_atl_rpf_rss_key_wr_en_get,
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self, val, val == 0,
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1000U, 10000U);
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if (err < 0)
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goto err_exit;
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}
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@ -209,6 +216,7 @@ static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self,
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int err = 0;
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u16 bitary[1 + (HW_ATL_A0_RSS_REDIRECTION_MAX *
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HW_ATL_A0_RSS_REDIRECTION_BITS / 16U)];
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u32 val;
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memset(bitary, 0, sizeof(bitary));
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@ -222,8 +230,9 @@ static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self,
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hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
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hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
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hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
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AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
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1000U, 10U);
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err = readx_poll_timeout_atomic(hw_atl_rpf_rss_redir_wr_en_get,
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self, val, val == 0,
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1000U, 10000U);
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if (err < 0)
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goto err_exit;
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}
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@ -173,6 +173,7 @@ static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
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int err = 0;
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unsigned int i = 0U;
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unsigned int addr = 0U;
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u32 val;
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for (i = 10, addr = 0U; i--; ++addr) {
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u32 key_data = cfg->is_rss ?
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@ -180,8 +181,9 @@ static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
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hw_atl_rpf_rss_key_wr_data_set(self, key_data);
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hw_atl_rpf_rss_key_addr_set(self, addr);
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hw_atl_rpf_rss_key_wr_en_set(self, 1U);
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AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
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1000U, 10U);
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err = readx_poll_timeout_atomic(hw_atl_rpf_rss_key_wr_en_get,
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self, val, val == 0,
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1000U, 10000U);
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if (err < 0)
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goto err_exit;
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}
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@ -201,6 +203,7 @@ static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
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int err = 0;
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u16 bitary[1 + (HW_ATL_B0_RSS_REDIRECTION_MAX *
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HW_ATL_B0_RSS_REDIRECTION_BITS / 16U)];
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u32 val;
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memset(bitary, 0, sizeof(bitary));
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@ -214,8 +217,9 @@ static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
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hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
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hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
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hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
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AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
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1000U, 10U);
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err = readx_poll_timeout_atomic(hw_atl_rpf_rss_redir_wr_en_get,
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self, val, val == 0,
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1000U, 10000U);
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if (err < 0)
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goto err_exit;
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}
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@ -1585,3 +1585,24 @@ void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
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HW_ATL_RPF_L3_DSTA_ADR(location + i),
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ipv6_dest[i]);
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}
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u32 hw_atl_sem_ram_get(struct aq_hw_s *self)
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{
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return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
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}
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u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp)
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{
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return aq_hw_read_reg(aq_hw,
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HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp));
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}
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u32 hw_atl_scrpad12_get(struct aq_hw_s *self)
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{
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return hw_atl_scrpad_get(self, 0xB);
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}
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u32 hw_atl_scrpad25_get(struct aq_hw_s *self)
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{
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return hw_atl_scrpad_get(self, 0x18);
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}
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@ -752,4 +752,16 @@ void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
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void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
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u32 *ipv6_dest);
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/* get global microprocessor ram semaphore */
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u32 hw_atl_sem_ram_get(struct aq_hw_s *self);
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/* get global microprocessor scratch pad register */
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u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp);
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/* get global microprocessor scratch pad 12 register */
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u32 hw_atl_scrpad12_get(struct aq_hw_s *self);
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/* get global microprocessor scratch pad 25 register */
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u32 hw_atl_scrpad25_get(struct aq_hw_s *self);
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#endif /* HW_ATL_LLH_H */
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@ -2519,4 +2519,6 @@
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/* Default value of bitfield l3_da0[1F:0] */
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#define HW_ATL_RPF_L3_DSTA_DEFAULT 0x0
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#define HW_ATL_FW_SM_RAM 0x2U
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#endif /* HW_ATL_LLH_INTERNAL_H */
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@ -25,7 +25,9 @@
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#define HW_ATL_MIF_ADDR 0x0208U
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#define HW_ATL_MIF_VAL 0x020CU
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#define HW_ATL_FW_SM_RAM 0x2U
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#define HW_ATL_RPC_CONTROL_ADR 0x0338U
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#define HW_ATL_RPC_STATE_ADR 0x033CU
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#define HW_ATL_MPI_FW_VERSION 0x18
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#define HW_ATL_MPI_CONTROL_ADR 0x0368U
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#define HW_ATL_MPI_STATE_ADR 0x036CU
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@ -53,6 +55,12 @@ static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual);
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static int hw_atl_utils_mpi_set_state(struct aq_hw_s *self,
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enum hal_atl_utils_fw_state_e state);
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static u32 hw_atl_utils_get_mpi_mbox_tid(struct aq_hw_s *self);
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static u32 hw_atl_utils_mpi_get_state(struct aq_hw_s *self);
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static u32 hw_atl_utils_mif_cmd_get(struct aq_hw_s *self);
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static u32 hw_atl_utils_mif_addr_get(struct aq_hw_s *self);
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static u32 hw_atl_utils_rpc_state_get(struct aq_hw_s *self);
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int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops)
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{
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int err = 0;
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@ -234,6 +242,7 @@ int hw_atl_utils_soft_reset(struct aq_hw_s *self)
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{
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int k;
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u32 boot_exit_code = 0;
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u32 val;
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for (k = 0; k < 1000; ++k) {
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u32 flb_status = aq_hw_read_reg(self,
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@ -260,9 +269,11 @@ int hw_atl_utils_soft_reset(struct aq_hw_s *self)
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int err = 0;
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hw_atl_utils_mpi_set_state(self, MPI_DEINIT);
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AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR) &
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HW_ATL_MPI_STATE_MSK) == MPI_DEINIT,
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10, 1000U);
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err = readx_poll_timeout_atomic(hw_atl_utils_mpi_get_state,
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self, val,
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(val & HW_ATL_MPI_STATE_MSK) ==
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MPI_DEINIT,
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10, 10000U);
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if (err)
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return err;
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}
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@ -277,10 +288,11 @@ int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
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u32 *p, u32 cnt)
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{
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int err = 0;
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u32 val;
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AQ_HW_WAIT_FOR(hw_atl_reg_glb_cpu_sem_get(self,
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HW_ATL_FW_SM_RAM) == 1U,
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1U, 10000U);
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err = readx_poll_timeout_atomic(hw_atl_sem_ram_get,
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self, val, val == 1U,
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1U, 10000U);
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if (err < 0) {
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bool is_locked;
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@ -299,13 +311,14 @@ int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
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aq_hw_write_reg(self, HW_ATL_MIF_CMD, 0x00008000U);
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if (IS_CHIP_FEATURE(REVISION_B1))
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AQ_HW_WAIT_FOR(a != aq_hw_read_reg(self,
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HW_ATL_MIF_ADDR),
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1, 1000U);
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err = readx_poll_timeout_atomic(hw_atl_utils_mif_addr_get,
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self, val, val != a,
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1U, 1000U);
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else
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AQ_HW_WAIT_FOR(!(0x100 & aq_hw_read_reg(self,
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HW_ATL_MIF_CMD)),
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1, 1000U);
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err = readx_poll_timeout_atomic(hw_atl_utils_mif_cmd_get,
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self, val,
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!(val & 0x100),
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1U, 1000U);
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*(p++) = aq_hw_read_reg(self, HW_ATL_MIF_VAL);
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a += 4;
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@ -320,6 +333,7 @@ err_exit:
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static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
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u32 cnt)
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{
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u32 val;
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int err = 0;
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bool is_locked;
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@ -337,10 +351,11 @@ static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
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(0x80000000 | (0xFFFF & (offset * 4))));
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hw_atl_mcp_up_force_intr_set(self, 1);
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/* 1000 times by 10us = 10ms */
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AQ_HW_WAIT_FOR((aq_hw_read_reg(self,
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0x32C) & 0xF0000000) !=
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0x80000000,
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10, 1000);
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err = readx_poll_timeout_atomic(hw_atl_scrpad12_get,
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self, val,
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(val & 0xF0000000) ==
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0x80000000,
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10U, 10000U);
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}
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} else {
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u32 offset = 0;
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@ -351,8 +366,10 @@ static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
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aq_hw_write_reg(self, 0x20C, p[offset]);
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aq_hw_write_reg(self, 0x200, 0xC000);
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AQ_HW_WAIT_FOR((aq_hw_read_reg(self, 0x200U) &
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0x100) == 0, 10, 1000);
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err = readx_poll_timeout_atomic(hw_atl_utils_mif_cmd_get,
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self, val,
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(val & 0x100) == 0,
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1000U, 10000U);
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}
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}
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@ -395,15 +412,14 @@ static int hw_atl_utils_init_ucp(struct aq_hw_s *self,
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hw_atl_reg_glb_cpu_scratch_scp_set(self, 0x00000000U, 25U);
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/* check 10 times by 1ms */
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AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
|
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aq_hw_read_reg(self, 0x360U)), 1000U, 10U);
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err = readx_poll_timeout_atomic(hw_atl_scrpad25_get,
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self, self->mbox_addr,
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self->mbox_addr != 0U,
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1000U, 10000U);
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return err;
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}
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#define HW_ATL_RPC_CONTROL_ADR 0x0338U
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#define HW_ATL_RPC_STATE_ADR 0x033CU
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struct aq_hw_atl_utils_fw_rpc_tid_s {
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union {
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u32 val;
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@ -452,10 +468,10 @@ int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
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self->rpc_tid = sw.tid;
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AQ_HW_WAIT_FOR(sw.tid ==
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(fw.val =
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aq_hw_read_reg(self, HW_ATL_RPC_STATE_ADR),
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fw.tid), 1000U, 100U);
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err = readx_poll_timeout_atomic(hw_atl_utils_rpc_state_get,
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self, fw.val,
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sw.tid == fw.tid,
|
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1000U, 100000U);
|
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if (fw.len == 0xFFFFU) {
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err = hw_atl_utils_fw_rpc_call(self, sw.len);
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@ -559,10 +575,11 @@ static int hw_atl_utils_mpi_set_state(struct aq_hw_s *self,
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transaction_id = mbox.transaction_id;
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|
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AQ_HW_WAIT_FOR(transaction_id !=
|
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(hw_atl_utils_mpi_read_mbox(self, &mbox),
|
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mbox.transaction_id),
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1000U, 100U);
|
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err = readx_poll_timeout_atomic(hw_atl_utils_get_mpi_mbox_tid,
|
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self, mbox.transaction_id,
|
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transaction_id !=
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mbox.transaction_id,
|
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1000U, 100000U);
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if (err < 0)
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goto err_exit;
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||||
}
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|
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@ -905,6 +922,35 @@ err_exit:
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return err;
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}
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static u32 hw_atl_utils_get_mpi_mbox_tid(struct aq_hw_s *self)
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{
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struct hw_atl_utils_mbox_header mbox;
|
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|
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hw_atl_utils_mpi_read_mbox(self, &mbox);
|
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return mbox.transaction_id;
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}
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|
||||
static u32 hw_atl_utils_mpi_get_state(struct aq_hw_s *self)
|
||||
{
|
||||
return aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR);
|
||||
}
|
||||
|
||||
static u32 hw_atl_utils_mif_cmd_get(struct aq_hw_s *self)
|
||||
{
|
||||
return aq_hw_read_reg(self, HW_ATL_MIF_CMD);
|
||||
}
|
||||
|
||||
static u32 hw_atl_utils_mif_addr_get(struct aq_hw_s *self)
|
||||
{
|
||||
return aq_hw_read_reg(self, HW_ATL_MIF_ADDR);
|
||||
}
|
||||
|
||||
static u32 hw_atl_utils_rpc_state_get(struct aq_hw_s *self)
|
||||
{
|
||||
return aq_hw_read_reg(self, HW_ATL_RPC_STATE_ADR);
|
||||
}
|
||||
|
||||
const struct aq_fw_ops aq_fw_1x_ops = {
|
||||
.init = hw_atl_utils_mpi_create,
|
||||
.deinit = hw_atl_fw1x_deinit,
|
||||
|
|
|
|||
|
|
@ -20,15 +20,14 @@
|
|||
#include "hw_atl_utils.h"
|
||||
#include "hw_atl_llh.h"
|
||||
|
||||
#define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
|
||||
#define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
|
||||
#define HW_ATL_FW2X_MPI_RPC_ADDR 0x334
|
||||
|
||||
#define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
|
||||
#define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
|
||||
#define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368
|
||||
#define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C
|
||||
|
||||
#define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
|
||||
#define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
|
||||
#define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
|
||||
|
||||
#define HW_ATL_FW2X_CAP_PAUSE BIT(CAPS_HI_PAUSE)
|
||||
#define HW_ATL_FW2X_CAP_ASYM_PAUSE BIT(CAPS_HI_ASYMMETRIC_PAUSE)
|
||||
|
|
@ -72,17 +71,24 @@ static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
|
|||
static int aq_fw2x_set_state(struct aq_hw_s *self,
|
||||
enum hal_atl_utils_fw_state_e state);
|
||||
|
||||
static u32 aq_fw2x_mbox_get(struct aq_hw_s *self);
|
||||
static u32 aq_fw2x_rpc_get(struct aq_hw_s *self);
|
||||
static u32 aq_fw2x_state2_get(struct aq_hw_s *self);
|
||||
|
||||
static int aq_fw2x_init(struct aq_hw_s *self)
|
||||
{
|
||||
int err = 0;
|
||||
|
||||
/* check 10 times by 1ms */
|
||||
AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
|
||||
aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)),
|
||||
1000U, 10U);
|
||||
AQ_HW_WAIT_FOR(0U != (self->rpc_addr =
|
||||
aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR)),
|
||||
1000U, 100U);
|
||||
err = readx_poll_timeout_atomic(aq_fw2x_mbox_get,
|
||||
self, self->mbox_addr,
|
||||
self->mbox_addr != 0U,
|
||||
1000U, 10000U);
|
||||
|
||||
err = readx_poll_timeout_atomic(aq_fw2x_rpc_get,
|
||||
self, self->rpc_addr,
|
||||
self->rpc_addr != 0U,
|
||||
1000U, 100000U);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
@ -286,16 +292,18 @@ static int aq_fw2x_update_stats(struct aq_hw_s *self)
|
|||
int err = 0;
|
||||
u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
|
||||
u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
|
||||
u32 stats_val;
|
||||
|
||||
/* Toggle statistics bit for FW to update */
|
||||
mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
|
||||
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
|
||||
|
||||
/* Wait FW to report back */
|
||||
AQ_HW_WAIT_FOR(orig_stats_val !=
|
||||
(aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
|
||||
BIT(CAPS_HI_STATISTICS)),
|
||||
1U, 10000U);
|
||||
err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
|
||||
self, stats_val,
|
||||
orig_stats_val != (stats_val &
|
||||
BIT(CAPS_HI_STATISTICS)),
|
||||
1U, 10000U);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
|
|
@ -309,6 +317,7 @@ static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac)
|
|||
unsigned int rpc_size = 0U;
|
||||
u32 mpi_opts;
|
||||
int err = 0;
|
||||
u32 val;
|
||||
|
||||
rpc_size = sizeof(rpc->msg_id) + sizeof(*cfg);
|
||||
|
||||
|
|
@ -337,8 +346,10 @@ static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac)
|
|||
mpi_opts |= HW_ATL_FW2X_CTRL_SLEEP_PROXY;
|
||||
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
|
||||
|
||||
AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
|
||||
HW_ATL_FW2X_CTRL_SLEEP_PROXY), 1U, 10000U);
|
||||
err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
|
||||
self, val,
|
||||
val & HW_ATL_FW2X_CTRL_SLEEP_PROXY,
|
||||
1U, 10000U);
|
||||
|
||||
err_exit:
|
||||
return err;
|
||||
|
|
@ -350,6 +361,7 @@ static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac)
|
|||
struct fw2x_msg_wol *msg = NULL;
|
||||
u32 mpi_opts;
|
||||
int err = 0;
|
||||
u32 val;
|
||||
|
||||
err = hw_atl_utils_fw_rpc_wait(self, &rpc);
|
||||
if (err < 0)
|
||||
|
|
@ -374,8 +386,9 @@ static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac)
|
|||
mpi_opts |= HW_ATL_FW2X_CTRL_WOL;
|
||||
aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
|
||||
|
||||
AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
|
||||
HW_ATL_FW2X_CTRL_WOL), 1U, 10000U);
|
||||
err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
|
||||
self, val, val & HW_ATL_FW2X_CTRL_WOL,
|
||||
1U, 10000U);
|
||||
|
||||
err_exit:
|
||||
return err;
|
||||
|
|
@ -471,6 +484,21 @@ static u32 aq_fw2x_get_flow_control(struct aq_hw_s *self, u32 *fcmode)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static u32 aq_fw2x_mbox_get(struct aq_hw_s *self)
|
||||
{
|
||||
return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR);
|
||||
}
|
||||
|
||||
static u32 aq_fw2x_rpc_get(struct aq_hw_s *self)
|
||||
{
|
||||
return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR);
|
||||
}
|
||||
|
||||
static u32 aq_fw2x_state2_get(struct aq_hw_s *self)
|
||||
{
|
||||
return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);
|
||||
}
|
||||
|
||||
const struct aq_fw_ops aq_fw_2x_ops = {
|
||||
.init = aq_fw2x_init,
|
||||
.deinit = aq_fw2x_deinit,
|
||||
|
|
|
|||
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