serial: 8250_pci: port failed after wakeup from S3
Serial ports of F81504/F81508/F81512 will failed when wakeup from S3(STR). It's due to when the system wakeup from S3(STR), this PCI device's configuration space from 0x40 to 0x40 + max_port * 0x08 should be re-configured. We move all initialization from pci_fintek_setup() to pci_fintek_init() and set it to pci_serial_quirks .init section. It's will re-init this device when system wakeup from pciserial_resume_ports(). Signed-off-by: Peter Hung <hpeter+linux_kernel@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Peter Hung
Greg Kroah-Hartman
Родитель
ca782f16ce
Коммит
6a8bc239a8
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@ -1690,88 +1690,71 @@ static int pci_fintek_setup(struct serial_private *priv,
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struct uart_8250_port *port, int idx)
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{
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struct pci_dev *pdev = priv->dev;
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unsigned long iobase;
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u8 config_base;
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u32 bar_data[3];
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u16 iobase;
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/*
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* Find each UARTs offset in PCI configuraion space
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*/
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switch (idx) {
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case 0:
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config_base = 0x40;
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config_base = 0x40 + 0x08 * idx;
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/* Get the io address from configuration space */
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pci_read_config_word(pdev, config_base + 4, &iobase);
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dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
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port->port.iotype = UPIO_PORT;
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port->port.iobase = iobase;
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return 0;
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}
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static int pci_fintek_init(struct pci_dev *dev)
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{
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unsigned long iobase;
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u32 max_port, i;
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u32 bar_data[3];
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u8 config_base;
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switch (dev->device) {
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case 0x1104: /* 4 ports */
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case 0x1108: /* 8 ports */
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max_port = dev->device & 0xff;
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break;
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case 1:
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config_base = 0x48;
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break;
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case 2:
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config_base = 0x50;
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break;
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case 3:
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config_base = 0x58;
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break;
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case 4:
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config_base = 0x60;
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break;
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case 5:
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config_base = 0x68;
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break;
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case 6:
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config_base = 0x70;
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break;
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case 7:
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config_base = 0x78;
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break;
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case 8:
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config_base = 0x80;
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break;
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case 9:
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config_base = 0x88;
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break;
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case 10:
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config_base = 0x90;
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break;
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case 11:
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config_base = 0x98;
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case 0x1112: /* 12 ports */
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max_port = 12;
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break;
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default:
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/* Unknown number of ports, get out of here */
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return -EINVAL;
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}
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/* Get the io address dispatch from the BIOS */
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pci_read_config_dword(pdev, 0x24, &bar_data[0]);
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pci_read_config_dword(pdev, 0x20, &bar_data[1]);
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pci_read_config_dword(pdev, 0x1c, &bar_data[2]);
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pci_read_config_dword(dev, 0x24, &bar_data[0]);
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pci_read_config_dword(dev, 0x20, &bar_data[1]);
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pci_read_config_dword(dev, 0x1c, &bar_data[2]);
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/* Calculate Real IO Port */
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iobase = (bar_data[idx/4] & 0xffffffe0) + (idx % 4) * 8;
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for (i = 0; i < max_port; ++i) {
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/* UART0 configuration offset start from 0x40 */
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config_base = 0x40 + 0x08 * i;
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dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx config_base=0x%2x\n",
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__func__, idx, iobase, config_base);
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/* Calculate Real IO Port */
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iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
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/* Enable UART I/O port */
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pci_write_config_byte(pdev, config_base + 0x00, 0x01);
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/* Enable UART I/O port */
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pci_write_config_byte(dev, config_base + 0x00, 0x01);
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/* Select 128-byte FIFO and 8x FIFO threshold */
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pci_write_config_byte(pdev, config_base + 0x01, 0x33);
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/* Select 128-byte FIFO and 8x FIFO threshold */
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pci_write_config_byte(dev, config_base + 0x01, 0x33);
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/* LSB UART */
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pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
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/* LSB UART */
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pci_write_config_byte(dev, config_base + 0x04,
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(u8)(iobase & 0xff));
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/* MSB UART */
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pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
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/* MSB UART */
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pci_write_config_byte(dev, config_base + 0x05,
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(u8)((iobase & 0xff00) >> 8));
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/* irq number, this usually fails, but the spec says to do it anyway. */
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pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
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pci_write_config_byte(dev, config_base + 0x06, dev->irq);
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}
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port->port.iotype = UPIO_PORT;
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port->port.iobase = iobase;
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port->port.mapbase = 0;
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port->port.membase = NULL;
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port->port.regshift = 0;
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return 0;
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return max_port;
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}
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static int skip_tx_en_setup(struct serial_private *priv,
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@ -2814,6 +2797,7 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = pci_fintek_setup,
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.init = pci_fintek_init,
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},
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{
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.vendor = 0x1c29,
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@ -2821,6 +2805,7 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = pci_fintek_setup,
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.init = pci_fintek_init,
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},
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{
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.vendor = 0x1c29,
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@ -2828,6 +2813,7 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = pci_fintek_setup,
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.init = pci_fintek_init,
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},
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/*
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