powerpc/8xx: Use hardware assistance in TLB handlers
Today, on the 8xx the TLB handlers do SW tablewalk by doing all the calculation in ASM, in order to match with the Linux page table structure. The 8xx offers hardware assistance which allows significant size reduction of the TLB handlers, hence also reduces the time spent in the handlers. However, using this HW assistance implies some constraints on the page table structure: - Regardless of the main page size used (4k or 16k), the level 1 table (PGD) contains 1024 entries and each PGD entry covers a 4Mbytes area which is managed by a level 2 table (PTE) containing also 1024 entries each describing a 4k page. - 16k pages require 4 identifical entries in the L2 table - 512k pages PTE have to be spread every 128 bytes in the L2 table - 8M pages PTE are at the address pointed by the L1 entry and each 8M page require 2 identical entries in the PGD. This patch modifies the TLB handlers to use HW assistance for 4K PAGES. Before that patch, the mean time spent in TLB miss handlers is: - ITLB miss: 80 ticks - DTLB miss: 62 ticks After that patch, the mean time spent in TLB miss handlers is: - ITLB miss: 72 ticks - DTLB miss: 54 ticks So the improvement is 10% for ITLB and 13% for DTLB misses Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Christophe Leroy
Michael Ellerman
Родитель
5af543be14
Коммит
6a8f911b50
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@ -292,7 +292,7 @@ SystemCall:
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. = 0x1100
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/*
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* For the MPC8xx, this is a software tablewalk to load the instruction
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* TLB. The task switch loads the M_TW register with the pointer to the first
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* TLB. The task switch loads the M_TWB register with the pointer to the first
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* level table.
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* If we discover there is no second level table (value is zero) or if there
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* is an invalid pte, we load that into the TLB, which causes another fault
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@ -323,6 +323,7 @@ InstructionTLBMiss:
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*/
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mfspr r10, SPRN_SRR0 /* Get effective address of fault */
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INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
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mtspr SPRN_MD_EPN, r10
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/* Only modules will cause ITLB Misses as we always
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* pin the first 8MB of kernel memory */
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#ifdef ITLB_MISS_KERNEL
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@ -339,7 +340,7 @@ InstructionTLBMiss:
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#endif
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#endif
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#endif
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mfspr r11, SPRN_M_TW /* Get level 1 table */
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mfspr r11, SPRN_M_TWB /* Get level 1 table */
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#ifdef ITLB_MISS_KERNEL
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#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
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beq+ 3f
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@ -349,16 +350,14 @@ InstructionTLBMiss:
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#ifndef CONFIG_PIN_TLB_TEXT
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blt cr7, ITLBMissLinear
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#endif
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lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
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rlwinm r11, r11, 0, 20, 31
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oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
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3:
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#endif
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/* Insert level 1 index */
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rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
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lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
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/* Extract level 2 index */
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rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
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rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
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mtspr SPRN_MD_TWC, r11
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mfspr r10, SPRN_MD_TWC
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lwz r10, 0(r10) /* Get the pte */
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#ifdef ITLB_MISS_KERNEL
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mtcr r12
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@ -417,7 +416,7 @@ DataStoreTLBMiss:
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mfspr r10, SPRN_MD_EPN
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rlwinm r11, r10, 16, 0xfff8
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cmpli cr0, r11, PAGE_OFFSET@h
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mfspr r11, SPRN_M_TW /* Get level 1 table */
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mfspr r11, SPRN_M_TWB /* Get level 1 table */
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blt+ 3f
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rlwinm r11, r10, 16, 0xfff8
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#ifndef CONFIG_PIN_TLB_IMMR
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@ -430,20 +429,16 @@ DataStoreTLBMiss:
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patch_site 0b, patch__dtlbmiss_immr_jmp
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#endif
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blt cr7, DTLBMissLinear
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lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
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mfspr r11, SPRN_M_TWB /* Get level 1 table */
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rlwinm r11, r11, 0, 20, 31
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oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
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3:
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/* Insert level 1 index */
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rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
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lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
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/* We have a pte table, so load fetch the pte from the table.
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*/
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/* Extract level 2 index */
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rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
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rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
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mtspr SPRN_MD_TWC, r11
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mfspr r10, SPRN_MD_TWC
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lwz r10, 0(r10) /* Get the pte */
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4:
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mtcr r12
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/* Insert the Guarded flag into the TWC from the Linux PTE.
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@ -668,9 +663,10 @@ FixupDAR:/* Entry point for dcbx workaround. */
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mtspr SPRN_SPRG_SCRATCH2, r10
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/* fetch instruction from memory. */
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mfspr r10, SPRN_SRR0
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mtspr SPRN_MD_EPN, r10
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rlwinm r11, r10, 16, 0xfff8
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cmpli cr0, r11, PAGE_OFFSET@h
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mfspr r11, SPRN_M_TW /* Get level 1 table */
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mfspr r11, SPRN_M_TWB /* Get level 1 table */
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blt+ 3f
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rlwinm r11, r10, 16, 0xfff8
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@ -680,17 +676,17 @@ FixupDAR:/* Entry point for dcbx workaround. */
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/* create physical page address from effective address */
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tophys(r11, r10)
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blt- cr7, 201f
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lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
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/* Insert level 1 index */
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3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
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mfspr r11, SPRN_M_TWB /* Get level 1 table */
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rlwinm r11, r11, 0, 20, 31
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oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
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3:
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lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
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mtspr SPRN_MD_TWC, r11
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mtcr r11
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mfspr r11, SPRN_MD_TWC
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lwz r11, 0(r11) /* Get the pte */
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bt 28,200f /* bit 28 = Large page (8M) */
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bt 29,202f /* bit 29 = Large page (8M or 512K) */
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rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */
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/* Insert level 2 index */
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rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
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lwz r11, 0(r11) /* Get the pte */
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/* concat physical page address(r11) and page offset(r10) */
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rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
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201: lwz r11,0(r11)
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@ -712,18 +708,12 @@ FixupDAR:/* Entry point for dcbx workaround. */
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141: mfspr r10,SPRN_SPRG_SCRATCH2
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b DARFixed /* Nope, go back to normal TLB processing */
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/* concat physical page address(r11) and page offset(r10) */
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200:
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rlwinm r11, r10, 0, ~HUGEPD_SHIFT_MASK
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lwz r11, 0(r11) /* Get the pte */
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/* concat physical page address(r11) and page offset(r10) */
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rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
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b 201b
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202:
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rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
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rlwimi r11, r10, 32 - (PAGE_SHIFT_512K - 2), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
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lwz r11, 0(r11) /* Get the pte */
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/* concat physical page address(r11) and page offset(r10) */
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rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31
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b 201b
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@ -839,7 +829,7 @@ start_here:
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lis r6, swapper_pg_dir@ha
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tophys(r6,r6)
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mtspr SPRN_M_TW, r6
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mtspr SPRN_M_TWB, r6
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bl early_init /* We have to do this with MMU on */
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@ -175,12 +175,12 @@ void set_context(unsigned long id, pgd_t *pgd)
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*(ptr + 1) = pgd;
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#endif
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/* Register M_TW will contain base address of level 1 table minus the
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/* Register M_TWB will contain base address of level 1 table minus the
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* lower part of the kernel PGDIR base address, so that all accesses to
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* level 1 table are done relative to lower part of kernel PGDIR base
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* address.
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*/
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mtspr(SPRN_M_TW, __pa(pgd) - offset);
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mtspr(SPRN_M_TWB, __pa(pgd) - offset);
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/* Update context */
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mtspr(SPRN_M_CASID, id - 1);
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