Updates to dts file structure for Altera's SOCFPGA
* Does not include any new bindings or bindings change * Add dts file for a SOCFPGA with an Arria V FPGA * Add a clocks property for the TWD timer * Add support for Terasic SocKit Board which has Cyclone5 FPGA * From Steffen Trumtrar: "This series includes some minor cleanups (indentation and clock labels) and reorders the socfpga dts hierarchy from: socfpga.dtsi -> socfpga_$board.dts -> socfpga_$otherboard.dts to socfpga.dtsi -> socfpga_cyclone5.dtsi --> socfpga_cyclone5_$board.dts --> socfpga_cyclone5_$otherboard.dts " -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJSVdPOAAoJEBmUBAuBoyj0pJcQALhtTLPhih/7GLlMUPEeH9JK KEx6IyPjg/+70Ap+dwdalv5WM13SoVy9beIEBceLgk7q/iRRmMtlrCgpHZkkGktp s4DF+xIqtJRtOjiJQwbAEpknE1MgiaDCJjtQAKUDppq9g2swik0nztpzDwgDIvFF dGwJffRYQUwvCQ6UqFdIyUudbGvDpHgsuI67/mRsR7jzdJMPhO1BX8A6X4i7feRY QP8RJWVpO8/6Vvh93rCF4AfapBZIpnRoUU60vfhgXHLw6BiPIwMCI4l60ccvXIzy yKfM68FZAPq8Loz4YKFcvH/AiHBlUVNHNPZtPd8HsPoKP6pn9kFsbz8S+0VfVH5Y PDiuaFSIFE98YyPIZ/YsCkMENAOoSmiYQFGnErIp1Ve8BIyjMWytnt7uxdMl41SM tYsjVyfMobnRwcyd6gWuQACgOeqSzWJJwH2m8Wz+HiugcOgQtnXmMmu9YaZyaOxK aS65w5jtxLje+tN7HmY3vUBVxMSDxd01wVFaDfxsjOAUWbOVnFh+hUtVkUL/5zOJ 7R5S1yVZw3pe6OY+N4gy0V+1w2T0WxfLxXly97B5JN5baeHtEvJmAj9/ukf92LES O4Ub2wEjrz72kl2IY20vWLBiAD+Q6405b7hfNJUKZ+ugKkcsdDseiMguv10aDREG kdp6J7h8aLxUBWWgAkVH =jmLh -----END PGP SIGNATURE----- Merge tag 'socfpga-dts-updates-for-v3.13' of git://git.rocketboards.org/linux-socfpga-next into next/dt From Dinh Nguyen: Updates to dts file structure for Altera's SOCFPGA * Does not include any new bindings or bindings change * Add dts file for a SOCFPGA with an Arria V FPGA * Add a clocks property for the TWD timer * Add support for Terasic SocKit Board which has Cyclone5 FPGA * From Steffen Trumtrar: "This series includes some minor cleanups (indentation and clock labels) and reorders the socfpga dts hierarchy from: socfpga.dtsi -> socfpga_$board.dts -> socfpga_$otherboard.dts to socfpga.dtsi -> socfpga_cyclone5.dtsi --> socfpga_cyclone5_$board.dts --> socfpga_cyclone5_$otherboard.dts " * tag 'socfpga-dts-updates-for-v3.13' of git://git.rocketboards.org/linux-socfpga-next: dts: socfpga: Add support for Altera's SOCFPGA Arria V board ARM: socfpga: dts: fix s2f_* clock name ARM: socfpga: dts: cleanup indentation ARM: socfpga: dts: Add support for terasic SoCkit ARM: socfpga: dts: Move common nodes to cyclone5 dtsi arm: socfpga: Add clock for smp_twd timer Signed-off-by: Kevin Hilman <khilman@linaro.org>
This commit is contained in:
Kevin Hilman
Коммит
6a9d10d529
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@ -217,7 +217,9 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
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r8a73a4-ape6evm-reference.dtb \
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sh7372-mackerel.dtb
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dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb
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dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
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dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
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socfpga_cyclone5_socdk.dtb \
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socfpga_cyclone5_sockit.dtb \
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socfpga_vt.dtb
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dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
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spear1340-evb.dtb
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@ -147,7 +147,7 @@
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reg = <0x58>;
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};
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cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
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cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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@ -198,7 +198,7 @@
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reg = <0x98>;
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};
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s2f_usr1_clk: s2f_usr1_clk {
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h2f_usr1_clk: h2f_usr1_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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@ -235,7 +235,7 @@
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reg = <0xD0>;
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};
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s2f_usr2_clk: s2f_usr2_clk {
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h2f_usr2_clk: h2f_usr2_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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@ -243,197 +243,197 @@
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};
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};
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mpu_periph_clk: mpu_periph_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mpuclk>;
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fixed-divider = <4>;
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mpu_periph_clk: mpu_periph_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mpuclk>;
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fixed-divider = <4>;
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};
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mpu_l2_ram_clk: mpu_l2_ram_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mpuclk>;
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fixed-divider = <2>;
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mpu_l2_ram_clk: mpu_l2_ram_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mpuclk>;
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fixed-divider = <2>;
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};
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l4_main_clk: l4_main_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>;
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clk-gate = <0x60 0>;
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l4_main_clk: l4_main_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>;
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clk-gate = <0x60 0>;
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};
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l3_main_clk: l3_main_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>;
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l3_main_clk: l3_main_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>;
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};
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l3_mp_clk: l3_mp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>;
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div-reg = <0x64 0 2>;
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clk-gate = <0x60 1>;
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l3_mp_clk: l3_mp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>;
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div-reg = <0x64 0 2>;
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clk-gate = <0x60 1>;
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};
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l3_sp_clk: l3_sp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>;
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div-reg = <0x64 2 2>;
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};
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l4_mp_clk: l4_mp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>, <&per_base_clk>;
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div-reg = <0x64 4 3>;
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clk-gate = <0x60 2>;
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l3_sp_clk: l3_sp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>;
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div-reg = <0x64 2 2>;
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};
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l4_sp_clk: l4_sp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>, <&per_base_clk>;
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div-reg = <0x64 7 3>;
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clk-gate = <0x60 3>;
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l4_mp_clk: l4_mp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>, <&per_base_clk>;
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div-reg = <0x64 4 3>;
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clk-gate = <0x60 2>;
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};
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dbg_at_clk: dbg_at_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&dbg_base_clk>;
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div-reg = <0x68 0 2>;
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clk-gate = <0x60 4>;
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l4_sp_clk: l4_sp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>, <&per_base_clk>;
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div-reg = <0x64 7 3>;
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clk-gate = <0x60 3>;
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};
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dbg_clk: dbg_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&dbg_base_clk>;
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div-reg = <0x68 2 2>;
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clk-gate = <0x60 5>;
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dbg_at_clk: dbg_at_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&dbg_base_clk>;
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div-reg = <0x68 0 2>;
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clk-gate = <0x60 4>;
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};
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dbg_trace_clk: dbg_trace_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&dbg_base_clk>;
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div-reg = <0x6C 0 3>;
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clk-gate = <0x60 6>;
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dbg_clk: dbg_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&dbg_base_clk>;
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div-reg = <0x68 2 2>;
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clk-gate = <0x60 5>;
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};
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dbg_timer_clk: dbg_timer_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&dbg_base_clk>;
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clk-gate = <0x60 7>;
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dbg_trace_clk: dbg_trace_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&dbg_base_clk>;
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div-reg = <0x6C 0 3>;
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clk-gate = <0x60 6>;
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};
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cfg_clk: cfg_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&cfg_s2f_usr0_clk>;
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clk-gate = <0x60 8>;
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dbg_timer_clk: dbg_timer_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&dbg_base_clk>;
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clk-gate = <0x60 7>;
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};
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s2f_user0_clk: s2f_user0_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&cfg_s2f_usr0_clk>;
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clk-gate = <0x60 9>;
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cfg_clk: cfg_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&cfg_h2f_usr0_clk>;
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clk-gate = <0x60 8>;
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};
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emac_0_clk: emac_0_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&emac0_clk>;
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clk-gate = <0xa0 0>;
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h2f_user0_clk: h2f_user0_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&cfg_h2f_usr0_clk>;
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clk-gate = <0x60 9>;
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};
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emac_1_clk: emac_1_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&emac1_clk>;
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clk-gate = <0xa0 1>;
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emac_0_clk: emac_0_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&emac0_clk>;
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clk-gate = <0xa0 0>;
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};
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usb_mp_clk: usb_mp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&per_base_clk>;
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clk-gate = <0xa0 2>;
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div-reg = <0xa4 0 3>;
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emac_1_clk: emac_1_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&emac1_clk>;
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clk-gate = <0xa0 1>;
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};
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spi_m_clk: spi_m_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&per_base_clk>;
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clk-gate = <0xa0 3>;
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div-reg = <0xa4 3 3>;
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usb_mp_clk: usb_mp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&per_base_clk>;
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clk-gate = <0xa0 2>;
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div-reg = <0xa4 0 3>;
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};
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can0_clk: can0_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&per_base_clk>;
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clk-gate = <0xa0 4>;
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div-reg = <0xa4 6 3>;
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spi_m_clk: spi_m_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&per_base_clk>;
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clk-gate = <0xa0 3>;
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div-reg = <0xa4 3 3>;
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};
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can1_clk: can1_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&per_base_clk>;
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clk-gate = <0xa0 5>;
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div-reg = <0xa4 9 3>;
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can0_clk: can0_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&per_base_clk>;
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clk-gate = <0xa0 4>;
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div-reg = <0xa4 6 3>;
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};
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gpio_db_clk: gpio_db_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&per_base_clk>;
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clk-gate = <0xa0 6>;
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||||
div-reg = <0xa8 0 24>;
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||||
can1_clk: can1_clk {
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||||
#clock-cells = <0>;
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||||
compatible = "altr,socfpga-gate-clk";
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clocks = <&per_base_clk>;
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||||
clk-gate = <0xa0 5>;
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||||
div-reg = <0xa4 9 3>;
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||||
};
|
||||
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||||
s2f_user1_clk: s2f_user1_clk {
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||||
#clock-cells = <0>;
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||||
compatible = "altr,socfpga-gate-clk";
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||||
clocks = <&s2f_usr1_clk>;
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||||
clk-gate = <0xa0 7>;
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||||
gpio_db_clk: gpio_db_clk {
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||||
#clock-cells = <0>;
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||||
compatible = "altr,socfpga-gate-clk";
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||||
clocks = <&per_base_clk>;
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||||
clk-gate = <0xa0 6>;
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||||
div-reg = <0xa8 0 24>;
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||||
};
|
||||
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||||
sdmmc_clk: sdmmc_clk {
|
||||
#clock-cells = <0>;
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||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
|
||||
clk-gate = <0xa0 8>;
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||||
h2f_user1_clk: h2f_user1_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&h2f_usr1_clk>;
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||||
clk-gate = <0xa0 7>;
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||||
};
|
||||
|
||||
nand_x_clk: nand_x_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
|
||||
clk-gate = <0xa0 9>;
|
||||
sdmmc_clk: sdmmc_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
|
||||
clk-gate = <0xa0 8>;
|
||||
};
|
||||
|
||||
nand_clk: nand_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
|
||||
clk-gate = <0xa0 10>;
|
||||
fixed-divider = <4>;
|
||||
nand_x_clk: nand_x_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
|
||||
clk-gate = <0xa0 9>;
|
||||
};
|
||||
|
||||
qspi_clk: qspi_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
|
||||
clk-gate = <0xa0 11>;
|
||||
nand_clk: nand_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
|
||||
clk-gate = <0xa0 10>;
|
||||
fixed-divider = <4>;
|
||||
};
|
||||
|
||||
qspi_clk: qspi_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
|
||||
clk-gate = <0xa0 11>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -473,6 +473,7 @@
|
|||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xfffec600 0x100>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
clocks = <&mpu_periph_clk>;
|
||||
};
|
||||
|
||||
timer0: timer0@ffc08000 {
|
||||
|
|
@ -516,9 +517,9 @@
|
|||
};
|
||||
|
||||
rstmgr@ffd05000 {
|
||||
compatible = "altr,rst-mgr";
|
||||
reg = <0xffd05000 0x1000>;
|
||||
};
|
||||
compatible = "altr,rst-mgr";
|
||||
reg = <0xffd05000 0x1000>;
|
||||
};
|
||||
|
||||
sysmgr@ffd08000 {
|
||||
compatible = "altr,sys-mgr";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "socfpga.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
clkmgr@ffd04000 {
|
||||
clocks {
|
||||
osc1 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0@ffc02000 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
serial1@ffc03000 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
sysmgr@ffd08000 {
|
||||
cpu1-start-addr = <0xffd080c4>;
|
||||
};
|
||||
|
||||
timer0@ffc08000 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
timer1@ffc09000 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
timer2@ffd00000 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
timer3@ffd01000 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/include/ "socfpga_arria5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Altera SOCFPGA Arria V SoC Development Kit";
|
||||
compatible = "altr,socfpga-arria5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
memory {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
/* this allow the ethaddr uboot environmnet variable contents
|
||||
* to be added to the gmac1 device tree blob.
|
||||
*/
|
||||
ethernet0 = &gmac1;
|
||||
};
|
||||
};
|
||||
|
|
@ -19,26 +19,6 @@
|
|||
/include/ "socfpga.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Altera SOCFPGA Cyclone V";
|
||||
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,57600";
|
||||
};
|
||||
|
||||
memory {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
/* this allow the ethaddr uboot environmnet variable contents
|
||||
* to be added to the gmac1 device tree blob.
|
||||
*/
|
||||
ethernet0 = &gmac1;
|
||||
};
|
||||
|
||||
soc {
|
||||
clkmgr@ffd04000 {
|
||||
clocks {
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/include/ "socfpga_cyclone5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Altera SOCFPGA Cyclone V SoC Development Kit";
|
||||
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
memory {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
/* this allow the ethaddr uboot environmnet variable contents
|
||||
* to be added to the gmac1 device tree blob.
|
||||
*/
|
||||
ethernet0 = &gmac1;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/include/ "socfpga_cyclone5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Terasic SoCkit";
|
||||
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
memory {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; /* 1GB */
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
status = "okay";
|
||||
};
|
||||
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