Few omap interconnect dts fixes for v4.16 merge window
Now that we have the dts clocks for the clkctrl clock and the interconnect binding, we need to update the existing ti-sysc users according to the binding to make it usable for drivers. Apologies for not being able to send this earlier but it took me few revisions to get the smartreflex changes right and tested with yet to be posted patches to make smartreflex probe with dts and I wanted to have it sit in next for a while to make sure we're not introducing regressions for legacy platform data based booting. Note that this is based on a merge with commit20a2742e57("dt-bindings: ti-sysc: Update binding for timers and capabilities") to avoid a merge conflict with the binding changes. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlpiDqURHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXMmOg/9Hr2lan1ZTqNBTgBixbcxj+gmovVlwjKa 1tXtNlkTco17BjEyDmKb3dzS16zT5YXv27RrIjCukQsKvVr2HOW4EnJ6iPPP6Y97 bp3Tx3ejqzoUNCcTUII4nWLZKaFXZ6C27sDrylEovsDJR9InocNYk5RhYDuPKPAw 3YaG/+QuRLc98YzjPGbSzUZws4EDUJhfHBqsVBwr4UFNJblRJe65kTFeH7BkZ9F8 eXenpUcS1JQMjMARR7aZck+7/3jyjtqWft1GjFWUto2kfx0tA8Ay4SyOqJxS9REa 0TK/Qdik2KDqP3wgBy7FLgXakmMOWttDFB5LUsWZbSyIO9vTgZj4RimSRgctfMxx XbyiJKovlNq1uDIPv3z/rHOala3WifNnzpf0m9izE5kbMW7vdHVycwzmJ2/Ushz6 rV4pqYVZ7o+SSnYRoiSdEQ/MMgMuypuL1+mhpIHL/rh+vCBGVaUfKRkrIcFwfujL H0nhB4PG8DEyOoc6dr8X317jUCgj0X6xTBO8jJUhT5R8tMHuKjqSSAq1QKCL7q5K /tvjkE4fEIs+Hr0bSkBZ+Jd/llWZrmkD7a1etJtw5WbRnPROYYRsb0PeNDFWTtOF nw/S4YF1F3k6BzOQobH2BjkXOCTJD1FhnfH7hmTLJ3ZReyQLafKFu2DHdje8GyFm XjGUuctAC24= =oKRR -----END PGP SIGNATURE----- Merge tag 'omap-for-v4.16/dt-clk-dts-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt Pull "Few omap interconnect dts fixes for v4.16 merge window" from Tony Lindgren: Now that we have the dts clocks for the clkctrl clock and the interconnect binding, we need to update the existing ti-sysc users according to the binding to make it usable for drivers. Apologies for not being able to send this earlier but it took me few revisions to get the smartreflex changes right and tested with yet to be posted patches to make smartreflex probe with dts and I wanted to have it sit in next for a while to make sure we're not introducing regressions for legacy platform data based booting. Note that this is based on a merge with commit20a2742e57("dt-bindings: ti-sysc: Update binding for timers and capabilities") to avoid a merge conflict with the binding changes. * tag 'omap-for-v4.16/dt-clk-dts-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: Update ti-sysc data for existing users ARM: dts: Fix smartreflex compatible for omap3 shared mpu-iva instance dt-bindings: ti-sysc: Update binding for timers and capabilities
This commit is contained in:
Arnd Bergmann
Коммит
6ab1e867ac
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@ -26,6 +26,8 @@ Required standard properties:
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or one of the following derivative types for hardware
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needing special workarounds:
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"ti,sysc-omap2-timer"
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"ti,sysc-omap4-timer"
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"ti,sysc-omap3430-sr"
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"ti,sysc-omap3630-sr"
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"ti,sysc-omap4-sr"
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@ -49,6 +51,26 @@ Required standard properties:
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Optional properties:
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- ti,sysc-mask shall contain mask of supported register bits for the
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SYSCONFIG register as documented in the Technical Reference
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Manual (TRM) for the interconnect target module
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- ti,sysc-midle list of master idle modes supported by the interconnect
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target module as documented in the TRM for SYSCONFIG
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register MIDLEMODE bits
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- ti,sysc-sidle list of slave idle modes supported by the interconnect
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target module as documented in the TRM for SYSCONFIG
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register SIDLEMODE bits
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- ti,sysc-delay-us delay needed after OCP softreset before accssing
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SYSCONFIG register again
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- ti,syss-mask optional mask of reset done status bits as described in the
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TRM for SYSSTATUS registers, typically 1 with some devices
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having separate reset done bits for children like OHCI and
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EHCI
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- clocks clock specifier for each name in the clock-names as
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specified in the binding documentation for ti-clkctrl,
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typically available for all interconnect targets on TI SoCs
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@ -61,6 +83,9 @@ Optional properties:
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- ti,hwmods optional TI interconnect module name to use legacy
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hwmod platform data
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- ti,no-reset-on-init interconnect target module should not be reset at init
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- ti,no-idle-on-init interconnect target module should not be idled at init
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Example: Single instance of MUSB controller on omap4 using interconnect ranges
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using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
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@ -74,6 +99,17 @@ using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
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reg-names = "rev", "sysc", "syss";
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clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
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clock-names = "fck";
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ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,syss-mask = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x2b000 0x1000>;
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@ -7,7 +7,7 @@ Required properties:
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compatible: Shall be one of the following:
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"ti,omap3-smartreflex-core"
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"ti,omap3-smartreflex-iva"
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"ti,omap3-smartreflex-mpu-iva"
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"ti,omap4-smartreflex-core"
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"ti,omap4-smartreflex-mpu"
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"ti,omap4-smartreflex-iva"
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@ -99,9 +99,5 @@
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status = "disabled";
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};
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&smartreflex_mpu_iva {
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status = "disabled";
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};
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/include/ "am35xx-clocks.dtsi"
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/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
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@ -7,6 +7,8 @@
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* Based on "omap4.dtsi"
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/clock/dra7.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/dra.h>
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#include <dt-bindings/clock/dra7.h>
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@ -1523,9 +1525,15 @@
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target-module@4a0dd000 {
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compatible = "ti,sysc-omap4-sr";
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ti,hwmods = "smartreflex_core";
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reg = <0x4a0dd000 0x4>,
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<0x4a0dd008 0x4>;
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reg-names = "rev", "sysc";
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reg = <0x4a0dd038 0x4>;
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_CORE_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x4a0dd000 0x001000>;
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@ -1536,9 +1544,15 @@
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target-module@4a0d9000 {
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compatible = "ti,sysc-omap4-sr";
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ti,hwmods = "smartreflex_mpu";
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reg = <0x4a0d9000 0x4>,
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<0x4a0d9008 0x4>;
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reg-names = "rev", "sysc";
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reg = <0x4a0d9038 0x4>;
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_MPU_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x4a0d9000 0x001000>;
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@ -587,20 +587,6 @@
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dma-names = "rx";
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};
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smartreflex_core: smartreflex@480cb000 {
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compatible = "ti,omap3-smartreflex-core";
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ti,hwmods = "smartreflex_core";
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reg = <0x480cb000 0x400>;
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interrupts = <19>;
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};
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smartreflex_mpu_iva: smartreflex@480c9000 {
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compatible = "ti,omap3-smartreflex-iva";
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ti,hwmods = "smartreflex_mpu_iva";
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reg = <0x480c9000 0x400>;
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interrupts = <18>;
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};
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timer1: timer@48318000 {
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compatible = "ti,omap3430-timer";
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reg = <0x48318000 0x400>;
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@ -8,6 +8,7 @@
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* kind, whether express or implied.
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/media/omap3-isp.h>
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#include "omap3.dtsi"
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@ -61,6 +62,44 @@
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compatible = "ti,omap34xx-bandgap";
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#thermal-sensor-cells = <0>;
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};
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target-module@480cb000 {
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compatible = "ti,sysc-omap3430-sr", "ti,sysc";
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ti,hwmods = "smartreflex_core";
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reg = <0x480cb024 0x4>;
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
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clocks = <&sr2_fck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x480cb000 0x001000>;
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smartreflex_core: smartreflex@0 {
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compatible = "ti,omap3-smartreflex-core";
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reg = <0 0x400>;
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interrupts = <19>;
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};
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};
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target-module@480c9000 {
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compatible = "ti,sysc-omap3430-sr", "ti,sysc";
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ti,hwmods = "smartreflex_mpu_iva";
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reg = <0x480c9024 0x4>;
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
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clocks = <&sr1_fck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x480c9000 0x001000>;
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smartreflex_mpu_iva: smartreflex@480c9000 {
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compatible = "ti,omap3-smartreflex-mpu-iva";
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reg = <0 0x400>;
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interrupts = <18>;
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};
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};
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};
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thermal_zones: thermal-zones {
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@ -8,6 +8,7 @@
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* kind, whether express or implied.
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/media/omap3-isp.h>
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#include "omap3.dtsi"
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@ -93,6 +94,51 @@
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compatible = "ti,omap36xx-bandgap";
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#thermal-sensor-cells = <0>;
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};
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target-module@480cb000 {
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compatible = "ti,sysc-omap3630-sr", "ti,sysc";
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ti,hwmods = "smartreflex_core";
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reg = <0x480cb038 0x4>;
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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clocks = <&sr2_fck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x480cb000 0x001000>;
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smartreflex_core: smartreflex@0 {
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compatible = "ti,omap3-smartreflex-core";
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reg = <0 0x400>;
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interrupts = <19>;
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};
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};
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target-module@480c9000 {
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compatible = "ti,sysc-omap3630-sr", "ti,sysc";
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ti,hwmods = "smartreflex_mpu_iva";
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reg = <0x480c9038 0x4>;
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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clocks = <&sr1_fck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x480c9000 0x001000>;
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smartreflex_mpu_iva: smartreflex@480c9000 {
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compatible = "ti,omap3-smartreflex-mpu-iva";
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reg = <0 0x400>;
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interrupts = <18>;
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};
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};
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};
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thermal_zones: thermal-zones {
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|
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@ -6,6 +6,8 @@
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/clock/omap4.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/omap.h>
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@ -398,6 +400,13 @@
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reg = <0x48076000 0x4>,
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<0x48076010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x48076000 0x001000>;
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|
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@ -468,9 +477,15 @@
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target-module@4a0db000 {
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compatible = "ti,sysc-sr";
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ti,hwmods = "smartreflex_iva";
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reg = <0x4a0db000 0x4>,
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<0x4a0db008 0x4>;
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reg-names = "rev", "sysc";
|
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reg = <0x4a0db038 0x4>;
|
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x4a0db000 0x001000>;
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|
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@ -485,9 +500,15 @@
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target-module@4a0dd000 {
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compatible = "ti,sysc-sr";
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ti,hwmods = "smartreflex_core";
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reg = <0x4a0dd000 0x4>,
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<0x4a0dd008 0x4>;
|
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reg-names = "rev", "sysc";
|
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reg = <0x4a0dd038 0x4>;
|
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
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<SYSC_IDLE_NO>,
|
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<SYSC_IDLE_SMART>,
|
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<SYSC_IDLE_SMART_WKUP>;
|
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clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>;
|
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clock-names = "fck";
|
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#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x4a0dd000 0x001000>;
|
||||
|
|
@ -502,9 +523,15 @@
|
|||
target-module@4a0d9000 {
|
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compatible = "ti,sysc-sr";
|
||||
ti,hwmods = "smartreflex_mpu";
|
||||
reg = <0x4a0d9000 0x4>,
|
||||
<0x4a0d9008 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
reg = <0x4a0d9038 0x4>;
|
||||
reg-names = "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x4a0d9000 0x001000>;
|
||||
|
|
@ -725,6 +752,18 @@
|
|||
reg = <0x52000000 0x4>,
|
||||
<0x52000010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,sysc-delay-us = <2>;
|
||||
clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x52000000 0x1000000>;
|
||||
|
|
@ -829,8 +868,15 @@
|
|||
target-module@40128000 {
|
||||
compatible = "ti,sysc-mcasp";
|
||||
ti,hwmods = "mcasp";
|
||||
reg = <0x40128004 0x4>;
|
||||
reg-names = "sysc";
|
||||
reg = <0x40128000 0x4>,
|
||||
<0x40128004 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x40128000 0x1000>, /* MPU */
|
||||
|
|
@ -850,6 +896,13 @@
|
|||
reg = <0x4012c000 0x4>,
|
||||
<0x4012c010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
|
||||
|
|
@ -864,6 +917,15 @@
|
|||
reg = <0x401f1000 0x4>,
|
||||
<0x401f1010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */
|
||||
|
|
@ -970,6 +1032,16 @@
|
|||
reg = <0x4a10a000 0x4>,
|
||||
<0x4a10a010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-delay-us = <2>;
|
||||
clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x4a10a000 0x1000>;
|
||||
|
|
@ -1199,6 +1271,16 @@
|
|||
reg = <0x5601fc00 0x4>,
|
||||
<0x5601fc10 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x56000000 0x2000000>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
/* TI sysc interconnect target module defines */
|
||||
|
||||
/* Generic sysc found on omap2 and later, also known as type1 */
|
||||
#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8)
|
||||
#define SYSC_OMAP2_EMUFREE (1 << 5)
|
||||
#define SYSC_OMAP2_ENAWAKEUP (1 << 2)
|
||||
#define SYSC_OMAP2_SOFTRESET (1 << 1)
|
||||
#define SYSC_OMAP2_AUTOIDLE (1 << 0)
|
||||
|
||||
/* Generic sysc found on omap4 and later, also known as type2 */
|
||||
#define SYSC_OMAP4_DMADISABLE (1 << 16)
|
||||
#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */
|
||||
#define SYSC_OMAP4_SOFTRESET (1 << 0)
|
||||
|
||||
/* SmartReflex sysc found on 36xx and later */
|
||||
#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26)
|
||||
|
||||
/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
|
||||
#define SYSC_IDLE_FORCE 0
|
||||
#define SYSC_IDLE_NO 1
|
||||
#define SYSC_IDLE_SMART 2
|
||||
#define SYSC_IDLE_SMART_WKUP 3
|
||||
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