ARM: tegra: minor fixes
This branch contains a variety of small build and run-time fixes that weren't important enough for 3.9. * Enable CPU errata WARs in secondary reset handler as a preparation for multi-platform support, and a related fix. * Don't touch DBLGAR in reset/resume handlers, so enable the code to run on A15 cores. * Minor build fixes. * A fix to the Tegra clock driver. * Some error-handling fixes. This branch is based on the previous fixes-for-mmc pull request. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRXvmIAAoJEMzrak5tbycx+YkP/1cnb3ushPA1/7xG+NzOMv/e eTx1FUL6yt0D5bSUFwFJ7YIlbnYyunGGY+hUfLWe1NjRWnDmLxM4ACOjDUqRoYc6 GjGG+66okOZOj2MlOxmvLYcKUW7L9LSz+GWqP2NVsGUlwsXb1M4UhX0tmKn6dqeg P7o5zTysbLruFrmwWr1eT4Jugz286fN5cSyVZvMrSf7GZ25k4h2f9AvPvaSDrFNH syOokOll1S5cpS7s95yiV4ANn8jT+5xGDNyukiiYLiCb/xq2lDIfDtZEKCk5Uh8D QLB3Rbt3NQNeeQLvY8ARJcDjz4/pFYARk0LUU6y3MoP6pem+/usOxI1Xte3Luw+G X0YHJjUN3kR1XIVKiwBPZhEN+FYg8jk2omUPUsiUptTHXBTrjbjghbcXL+/rk2FK hspdyPD3KzcRus7cKjzXwGNFI9rkz9nqcO98YjnJzMrhopDWVOd+uE8qxcsGXKJW tR+/rSgPZLCWsX+gAiEigIiZv+CiB57cVS6pD6NDy9SYV9Ax1xiYcSS8g5zOOlQE KD+rCMFsVxJRZuiNeKVnj/qamytRGiNgmdZxG59KSWNqs9uPp9o3pGeNjaLeUcAw pg7bYCeV7bcckNuL4FljdfT6rzLPuQIM52saCdQ26PZjOnI/sJdbWt9RqZhJ8wUc cOB9LPyUUxJkhOGW+c32 =5rB4 -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/fixes-non-critical From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: minor fixes This branch contains a variety of small build and run-time fixes that weren't important enough for 3.9. * Enable CPU errata WARs in secondary reset handler as a preparation for multi-platform support, and a related fix. * Don't touch DBLGAR in reset/resume handlers, so enable the code to run on A15 cores. * Minor build fixes. * A fix to the Tegra clock driver. * Some error-handling fixes. This branch is based on the previous fixes-for-mmc pull request. * tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra: powergate: Don't error out if new state == old state ARM: tegra: Export tegra_powergate_sequence_power_up() memory: tegra30: Fix build error w/o PM ARM: tegra: fix ignored return value of regulator_enable ARM: tegra: fix the logical detection of power on sequence of warm boot CPUs ARM: tegra: Fix unchecked return value ARM: tegra: don't unlock MMIO access to DBGLAR clk: tegra: No 7.1 super clk dividers on Tegra20 ARM: tegra: remove save/restore of CPU diag register ARM: tegra: add CPU errata WARs to Tegra reset handler ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc host Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Коммит
6abb057679
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@ -444,7 +444,7 @@
|
|||
};
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sdhci@c8000600 {
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cd-gpios = <&gpio 23 0>; /* gpio PC7 */
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cd-gpios = <&gpio 23 1>; /* gpio PC7 */
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};
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sound {
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|
|
|
@ -437,7 +437,7 @@
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sdhci@c8000200 {
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status = "okay";
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cd-gpios = <&gpio 69 0>; /* gpio PI5 */
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cd-gpios = <&gpio 69 1>; /* gpio PI5 */
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wp-gpios = <&gpio 57 0>; /* gpio PH1 */
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power-gpios = <&gpio 155 0>; /* gpio PT3 */
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bus-width = <4>;
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|
@ -445,7 +445,7 @@
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sdhci@c8000600 {
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status = "okay";
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cd-gpios = <&gpio 58 0>; /* gpio PH2 */
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cd-gpios = <&gpio 58 1>; /* gpio PH2 */
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wp-gpios = <&gpio 59 0>; /* gpio PH3 */
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power-gpios = <&gpio 70 0>; /* gpio PI6 */
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bus-width = <8>;
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|
|
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@ -436,7 +436,7 @@
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sdhci@c8000000 {
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status = "okay";
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cd-gpios = <&gpio 173 0>; /* gpio PV5 */
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cd-gpios = <&gpio 173 1>; /* gpio PV5 */
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wp-gpios = <&gpio 57 0>; /* gpio PH1 */
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power-gpios = <&gpio 169 0>; /* gpio PV1 */
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bus-width = <4>;
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|
|
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@ -584,7 +584,7 @@
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sdhci@c8000400 {
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status = "okay";
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cd-gpios = <&gpio 69 0>; /* gpio PI5 */
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cd-gpios = <&gpio 69 1>; /* gpio PI5 */
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wp-gpios = <&gpio 57 0>; /* gpio PH1 */
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power-gpios = <&gpio 70 0>; /* gpio PI6 */
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bus-width = <4>;
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|
|
|
@ -465,7 +465,7 @@
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};
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sdhci@c8000600 {
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cd-gpios = <&gpio 58 0>; /* gpio PH2 */
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cd-gpios = <&gpio 58 1>; /* gpio PH2 */
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wp-gpios = <&gpio 59 0>; /* gpio PH3 */
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bus-width = <4>;
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status = "okay";
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|
|
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@ -325,7 +325,7 @@
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sdhci@c8000600 {
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status = "okay";
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cd-gpios = <&gpio 121 0>; /* gpio PP1 */
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cd-gpios = <&gpio 121 1>; /* gpio PP1 */
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wp-gpios = <&gpio 122 0>; /* gpio PP2 */
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bus-width = <4>;
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};
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|
|
|
@ -520,7 +520,7 @@
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sdhci@c8000400 {
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status = "okay";
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cd-gpios = <&gpio 69 0>; /* gpio PI5 */
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cd-gpios = <&gpio 69 1>; /* gpio PI5 */
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wp-gpios = <&gpio 57 0>; /* gpio PH1 */
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power-gpios = <&gpio 70 0>; /* gpio PI6 */
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bus-width = <4>;
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|
|
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@ -510,6 +510,7 @@
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sdhci@c8000400 {
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status = "okay";
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cd-gpios = <&gpio 69 1>; /* gpio PI5 */
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wp-gpios = <&gpio 173 0>; /* gpio PV5 */
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bus-width = <8>;
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};
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|
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@ -257,7 +257,7 @@
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sdhci@78000000 {
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status = "okay";
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cd-gpios = <&gpio 69 0>; /* gpio PI5 */
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cd-gpios = <&gpio 69 1>; /* gpio PI5 */
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wp-gpios = <&gpio 155 0>; /* gpio PT3 */
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power-gpios = <&gpio 31 0>; /* gpio PD7 */
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bus-width = <4>;
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|
|
|
@ -311,7 +311,7 @@
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sdhci@78000000 {
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status = "okay";
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cd-gpios = <&gpio 69 0>; /* gpio PI5 */
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cd-gpios = <&gpio 69 1>; /* gpio PI5 */
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wp-gpios = <&gpio 155 0>; /* gpio PT3 */
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power-gpios = <&gpio 31 0>; /* gpio PD7 */
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bus-width = <4>;
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|
|
|
@ -62,7 +62,11 @@ int __init harmony_pcie_init(void)
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goto err_reg;
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}
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regulator_enable(regulator);
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err = regulator_enable(regulator);
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if (err) {
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pr_err("%s: regulator_enable failed: %d\n", __func__, err);
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goto err_en;
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}
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err = tegra_pcie_init(true, true);
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if (err) {
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@ -74,6 +78,7 @@ int __init harmony_pcie_init(void)
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err_pcie:
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regulator_disable(regulator);
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err_en:
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regulator_put(regulator);
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err_reg:
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gpio_free(en_vdd_1v05);
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|
|
|
@ -102,12 +102,8 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
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smp_wmb();
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save_cpu_arch_register();
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cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
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restore_cpu_arch_register();
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
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return true;
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|
|
|
@ -7,8 +7,5 @@
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ENTRY(tegra_secondary_startup)
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bl v7_invalidate_l1
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/* Enable coresight */
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mov32 r0, 0xC5ACCE55
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mcr p14, 0, r0, c7, c12, 6
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b secondary_startup
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ENDPROC(tegra_secondary_startup)
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@ -91,7 +91,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
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if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
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timeout = jiffies + msecs_to_jiffies(50);
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do {
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if (!tegra_powergate_is_powered(pwrgateid))
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if (tegra_powergate_is_powered(pwrgateid))
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goto remove_clamps;
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udelay(10);
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} while (time_before(jiffies, timeout));
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@ -124,6 +124,9 @@ remove_clamps:
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/* Remove I/O clamps. */
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ret = tegra_powergate_remove_clamping(pwrgateid);
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if (ret)
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return ret;
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udelay(10);
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/* Clear flow controller CSR. */
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@ -46,26 +46,11 @@
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#define PMC_CPUPWROFF_TIMER 0xcc
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#ifdef CONFIG_PM_SLEEP
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static unsigned int g_diag_reg;
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static DEFINE_SPINLOCK(tegra_lp2_lock);
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static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
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static struct clk *tegra_pclk;
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void (*tegra_tear_down_cpu)(void);
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void save_cpu_arch_register(void)
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{
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/* read diagnostic register */
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asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
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return;
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}
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void restore_cpu_arch_register(void)
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{
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/* write diagnostic register */
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asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
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return;
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}
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static void set_power_timers(unsigned long us_on, unsigned long us_off)
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{
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unsigned long long ticks;
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@ -119,8 +104,6 @@ static void restore_cpu_complex(void)
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tegra_cpu_clock_resume();
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flowctrl_cpu_suspend_exit(cpu);
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restore_cpu_arch_register();
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}
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/*
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@ -145,8 +128,6 @@ static void suspend_cpu_complex(void)
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tegra_cpu_clock_suspend();
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flowctrl_cpu_suspend_enter(cpu);
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save_cpu_arch_register();
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}
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void tegra_clear_cpu_in_lp2(int phy_cpu_id)
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@ -22,6 +22,7 @@
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/seq_file.h>
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@ -75,7 +76,7 @@ static int tegra_powergate_set(int id, bool new_state)
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if (status == new_state) {
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spin_unlock_irqrestore(&tegra_powergate_lock, flags);
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return -EINVAL;
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return 0;
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}
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pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
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@ -168,6 +169,7 @@ err_clk:
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err_power:
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return ret;
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}
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EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
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int tegra_cpu_powergate_id(int cpuid)
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{
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|
|
|
@ -41,9 +41,6 @@
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*/
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ENTRY(tegra_resume)
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bl v7_invalidate_l1
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/* Enable coresight */
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mov32 r0, 0xC5ACCE55
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mcr p14, 0, r0, c7, c12, 6
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cpu_id r0
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cmp r0, #0 @ CPU0?
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@ -99,6 +96,8 @@ ENTRY(__tegra_cpu_reset_handler_start)
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*
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* Register usage within the reset handler:
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*
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* Others: scratch
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* R6 = SoC ID << 8
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* R7 = CPU present (to the OS) mask
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* R8 = CPU in LP1 state mask
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* R9 = CPU in LP2 state mask
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|
@ -114,6 +113,40 @@ ENTRY(__tegra_cpu_reset_handler_start)
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ENTRY(__tegra_cpu_reset_handler)
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cpsid aif, 0x13 @ SVC mode, interrupts disabled
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mov32 r6, TEGRA_APB_MISC_BASE
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ldr r6, [r6, #APB_MISC_GP_HIDREV]
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and r6, r6, #0xff00
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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t20_check:
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cmp r6, #(0x20 << 8)
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bne after_t20_check
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t20_errata:
|
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# Tegra20 is a Cortex-A9 r1p1
|
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mrc p15, 0, r0, c1, c0, 0 @ read system control register
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orr r0, r0, #1 << 14 @ erratum 716044
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mcr p15, 0, r0, c1, c0, 0 @ write system control register
|
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
|
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orr r0, r0, #1 << 4 @ erratum 742230
|
||||
orr r0, r0, #1 << 11 @ erratum 751472
|
||||
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
|
||||
b after_errata
|
||||
after_t20_check:
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
t30_check:
|
||||
cmp r6, #(0x30 << 8)
|
||||
bne after_t30_check
|
||||
t30_errata:
|
||||
# Tegra30 is a Cortex-A9 r2p9
|
||||
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
|
||||
orr r0, r0, #1 << 6 @ erratum 743622
|
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orr r0, r0, #1 << 11 @ erratum 751472
|
||||
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
|
||||
b after_errata
|
||||
after_t30_check:
|
||||
#endif
|
||||
after_errata:
|
||||
mrc p15, 0, r10, c0, c0, 5 @ MPIDR
|
||||
and r10, r10, #0x3 @ R10 = CPU number
|
||||
mov r11, #1
|
||||
|
@ -129,16 +162,13 @@ ENTRY(__tegra_cpu_reset_handler)
|
|||
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
/* Are we on Tegra20? */
|
||||
mov32 r6, TEGRA_APB_MISC_BASE
|
||||
ldr r0, [r6, #APB_MISC_GP_HIDREV]
|
||||
and r0, r0, #0xff00
|
||||
cmp r0, #(0x20 << 8)
|
||||
cmp r6, #(0x20 << 8)
|
||||
bne 1f
|
||||
/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
|
||||
mov32 r6, TEGRA_PMC_BASE
|
||||
mov32 r5, TEGRA_PMC_BASE
|
||||
mov r0, #0
|
||||
cmp r10, #0
|
||||
strne r0, [r6, #PMC_SCRATCH41]
|
||||
strne r0, [r5, #PMC_SCRATCH41]
|
||||
1:
|
||||
#endif
|
||||
|
||||
|
|
|
@ -711,8 +711,8 @@ static void tegra20_pll_init(void)
|
|||
}
|
||||
|
||||
static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
|
||||
"pll_p_cclk", "pll_p_out4_cclk",
|
||||
"pll_p_out3_cclk", "clk_d", "pll_x" };
|
||||
"pll_p", "pll_p_out4",
|
||||
"pll_p_out3", "clk_d", "pll_x" };
|
||||
static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
|
||||
"pll_p_out3", "pll_p_out2", "clk_d",
|
||||
"clk_32k", "pll_m_out1" };
|
||||
|
@ -721,38 +721,6 @@ static void tegra20_super_clk_init(void)
|
|||
{
|
||||
struct clk *clk;
|
||||
|
||||
/*
|
||||
* DIV_U71 dividers for CCLK, these dividers are used only
|
||||
* if parent clock is fixed rate.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Clock input to cclk divided from pll_p using
|
||||
* U71 divider of cclk.
|
||||
*/
|
||||
clk = tegra_clk_register_divider("pll_p_cclk", "pll_p",
|
||||
clk_base + SUPER_CCLK_DIVIDER, 0,
|
||||
TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
|
||||
clk_register_clkdev(clk, "pll_p_cclk", NULL);
|
||||
|
||||
/*
|
||||
* Clock input to cclk divided from pll_p_out3 using
|
||||
* U71 divider of cclk.
|
||||
*/
|
||||
clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3",
|
||||
clk_base + SUPER_CCLK_DIVIDER, 0,
|
||||
TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
|
||||
clk_register_clkdev(clk, "pll_p_out3_cclk", NULL);
|
||||
|
||||
/*
|
||||
* Clock input to cclk divided from pll_p_out4 using
|
||||
* U71 divider of cclk.
|
||||
*/
|
||||
clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4",
|
||||
clk_base + SUPER_CCLK_DIVIDER, 0,
|
||||
TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
|
||||
clk_register_clkdev(clk, "pll_p_out4_cclk", NULL);
|
||||
|
||||
/* CCLK */
|
||||
clk = tegra_clk_register_super_mux("cclk", cclk_parents,
|
||||
ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
|
||||
|
|
|
@ -268,6 +268,7 @@ static const u32 tegra30_mc_ctx[] = {
|
|||
MC_INTMASK,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int tegra30_mc_suspend(struct device *dev)
|
||||
{
|
||||
int i;
|
||||
|
@ -291,6 +292,7 @@ static int tegra30_mc_resume(struct device *dev)
|
|||
mc_readl(mc, MC_TIMING_CONTROL);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static UNIVERSAL_DEV_PM_OPS(tegra30_mc_pm,
|
||||
tegra30_mc_suspend,
|
||||
|
|
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