From 4bf04fc458dfd2a3301a1b76b0dfa4741f7e59fe Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 3 Oct 2018 17:11:03 +0200 Subject: [PATCH 001/506] ARM: dts: stm32: Add dmas to timer on stm32mp157c Add DMAs to enable PWM input capture using STM32 timers on stm32mp157c. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 58 ++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 8bf1c17f8cef..2e9df63f9997 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -98,6 +98,12 @@ reg = <0x40000000 0x400>; clocks = <&rcc TIM2_K>; clock-names = "int"; + dmas = <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; status = "disabled"; pwm { @@ -119,6 +125,13 @@ reg = <0x40001000 0x400>; clocks = <&rcc TIM3_K>; clock-names = "int"; + dmas = <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; status = "disabled"; pwm { @@ -140,6 +153,11 @@ reg = <0x40002000 0x400>; clocks = <&rcc TIM4_K>; clock-names = "int"; + dmas = <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4"; status = "disabled"; pwm { @@ -161,6 +179,13 @@ reg = <0x40003000 0x400>; clocks = <&rcc TIM5_K>; clock-names = "int"; + dmas = <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; status = "disabled"; pwm { @@ -182,6 +207,8 @@ reg = <0x40004000 0x400>; clocks = <&rcc TIM6_K>; clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; status = "disabled"; timer@5 { @@ -198,6 +225,8 @@ reg = <0x40005000 0x400>; clocks = <&rcc TIM7_K>; clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; status = "disabled"; timer@6 { @@ -465,6 +494,15 @@ reg = <0x44000000 0x400>; clocks = <&rcc TIM1_K>; clock-names = "int"; + dmas = <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; status = "disabled"; pwm { @@ -486,6 +524,15 @@ reg = <0x44001000 0x400>; clocks = <&rcc TIM8_K>; clock-names = "int"; + dmas = <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; status = "disabled"; pwm { @@ -543,6 +590,11 @@ reg = <0x44006000 0x400>; clocks = <&rcc TIM15_K>; clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; status = "disabled"; pwm { @@ -564,6 +616,9 @@ reg = <0x44007000 0x400>; clocks = <&rcc TIM16_K>; clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; status = "disabled"; pwm { @@ -584,6 +639,9 @@ reg = <0x44008000 0x400>; clocks = <&rcc TIM17_K>; clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; status = "disabled"; pwm { From 1f3250f397f683e713439d4ff6a524386646a328 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 3 Oct 2018 17:11:04 +0200 Subject: [PATCH 002/506] ARM: dts: stm32: don't use timers dmas on stm32mp157c-ed1 Spare dmas when using timer6 on stm32mp157c-ed1. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index f77bea49c079..c3ecb1e10d94 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -72,6 +72,9 @@ &timers6 { status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; timer@5 { status = "okay"; }; From 5ae71cea1aec476a115dcf931807548cd26160ec Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 3 Oct 2018 17:11:05 +0200 Subject: [PATCH 003/506] ARM: dts: stm32: don't use timers dmas on stm32mp157c-ev1 Spare dmas when using timers on stm32mp157c-ev1. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 063ee8ac5dcb..e911527c80d0 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -161,6 +161,9 @@ }; &timers2 { + /* spare dmas for other usage (un-delete to enable pwm capture) */ + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm2_pins_a>; @@ -173,6 +176,8 @@ }; &timers8 { + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm8_pins_a>; @@ -185,6 +190,8 @@ }; &timers12 { + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm12_pins_a>; From d44d6e021301b6a8d95bf6a92e8aae640de2770a Mon Sep 17 00:00:00 2001 From: Bich HEMON Date: Thu, 15 Nov 2018 08:52:29 +0000 Subject: [PATCH 004/506] ARM: dts: stm32: change CAN RAM mapping on stm32mp157c Split the 10Kbytes CAN message RAM to be able to use simultaneously FDCAN1 and FDCAN2 instances. First 5Kbytes are allocated to FDCAN1 and last 5Kbytes are used for FDCAN2. To do so, set the offset to 0x1400 in mram-cfg for FDCAN2. Signed-off-by: Bich Hemon Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 2e9df63f9997..b0961cccfd14 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -742,14 +742,14 @@ m_can1: can@4400e000 { compatible = "bosch,m_can"; - reg = <0x4400e000 0x400>, <0x44011000 0x2800>; + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; reg-names = "m_can", "message_ram"; interrupts = , ; interrupt-names = "int0", "int1"; clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; }; From bb4857cd0060b16cb3e84ad258c334717db94acd Mon Sep 17 00:00:00 2001 From: Bich HEMON Date: Thu, 15 Nov 2018 08:52:29 +0000 Subject: [PATCH 005/506] ARM: dts: stm32: add can1 sleep pins muxing Add can1 pinctrl definition for low-power mode Signed-off-by: Bich Hemon Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index c4851271e810..9ec4694e93a7 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -246,6 +246,13 @@ }; }; + m_can1_sleep_pins_a: m_can1-sleep@0 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + pwm2_pins_a: pwm2-0 { pins { pinmux = ; /* TIM2_CH4 */ From e3b3d0b19bd7b1eb7e5ab1c5d2b12c96fe0f5500 Mon Sep 17 00:00:00 2001 From: Bich HEMON Date: Thu, 15 Nov 2018 08:52:29 +0000 Subject: [PATCH 006/506] ARM: dts: stm32: add can1 sleep pins muxing on stm32mp157c-ev1 board Add pinctrl sleep state for can1 on stm32mp157c-ev1. Signed-off-by: Bich Hemon Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index e911527c80d0..b6aca40b9b90 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -124,8 +124,9 @@ }; &m_can1 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; status = "okay"; }; From 8914b63bab3c43a529316ba2858137bc57b74fa1 Mon Sep 17 00:00:00 2001 From: David Hernandez Sanchez Date: Mon, 3 Dec 2018 10:42:24 +0100 Subject: [PATCH 007/506] ARM: dts: stm32: add thermal sensor support on STM32MP157c Add configuration on DT for thermal sensor driver. Signed-off-by: David Hernandez Sanchez Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index b0961cccfd14..f8bbfff5950b 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -84,6 +84,31 @@ }; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&dts>; + + trips { + cpu_alert1: cpu-alert1 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu-crit { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -966,6 +991,16 @@ status = "disabled"; }; + dts: thermal@50028000 { + compatible = "st,stm32-thermal"; + reg = <0x50028000 0x100>; + interrupts = ; + clocks = <&rcc TMPSENS>; + clock-names = "pclk"; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + cryp1: cryp@54001000 { compatible = "st,stm32mp1-cryp"; reg = <0x54001000 0x400>; From e3b382c1075e967cf1a95db881f575eef3a8f007 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Wed, 21 Nov 2018 22:05:15 +0100 Subject: [PATCH 008/506] ARM: dts: am335x-chiliboard: Add stdout-path property Add stdout-path property in /chosen node so that earlycon can be used by just adding earlycon in bootargs. Signed-off-by: Marcin Niestroj Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-chiliboard.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts index 9c2a947aacf5..b50d5d2e71ff 100644 --- a/arch/arm/boot/dts/am335x-chiliboard.dts +++ b/arch/arm/boot/dts/am335x-chiliboard.dts @@ -14,6 +14,10 @@ compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom", "ti,am33xx"; + chosen { + stdout-path = &uart0; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; From c6e967ad5a04d307836c927ae6300f62e7603dd7 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 13 Dec 2018 15:02:45 -0800 Subject: [PATCH 009/506] ARM: dts: Add wlcore wakeirq for omap3-evm With wlcore supporting optional wakeirqs, let's configure it for omap3-evm and update the related pin muxing as some pins are left unmuxed. Let's configure a wakeirq both for the wlcore GPIO and the SDIO dat1 pin in case wlcore starts supporting SDIO dat1 interrupt at some point. Note that for off-mode, the wlcore reset GPIO will have a glitch meaning wlcore will reset. The only way to workaround for this currently is to configure the reset pin with SAFE_MODE + PULL. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-evm-common.dtsi | 7 +++++-- arch/arm/boot/dts/omap3-evm-processor-common.dtsi | 10 +++++++++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi index 4c1227d1e79b..17c89df6ce6b 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -122,6 +122,7 @@ }; &mmc2 { + interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>; vmmc-supply = <&wl12xx_vmmc>; non-removable; bus-width = <4>; @@ -132,8 +133,10 @@ wlcore: wlcore@2 { compatible = "ti,wl1271"; reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 149 */ + /* gpio_149 with uart1_rts pad as wakeirq */ + interrupts-extended = <&gpio5 21 IRQ_TYPE_EDGE_RISING>, + <&omap3_pmx_core 0x14e>; + interrupt-names = "irq", "wakeup"; ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi index ce7f42f9448c..b4109f48ec18 100644 --- a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi @@ -86,6 +86,10 @@ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ >; }; @@ -127,9 +131,13 @@ >; }; + /* + * Note that gpio_150 pulled high with internal pull to prevent wlcore + * reset on return from off mode in idle. + */ wl12xx_gpio: pinmux_wl12xx_gpio { pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ + OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */ OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ >; }; From 2f60f258e0f533013042f624fb8af4fca165b646 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 13 Dec 2018 15:03:04 -0800 Subject: [PATCH 010/506] ARM: dts: Configure wlcore wakeirq for pandaboard With wlcore supporting optional wakeirqs, we can configure it for pandaboard. This makes ssh connection usable with the SoC entering deeper idle states. Note that pandaboard already has a wakeirq configured for SDIO dat1 pin although that is not currently used by wlcore. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-panda-common.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 27895c1604b9..926f018823a4 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -485,8 +485,10 @@ wlcore: wlcore@2 { compatible = "ti,wl1271"; reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */ + /* gpio_53 with gpmc_ncs3 pad as wakeup */ + interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_RISING>, + <&omap4_pmx_core 0x3a>; + interrupt-names = "irq", "wakeup"; ref-clock-frequency = <38400000>; }; }; From 7c695e87bd7a88298d2c00b5e14cf71d0a2a8663 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 13 Dec 2018 15:03:21 -0800 Subject: [PATCH 011/506] ARM: dts: omap4-droid4: Configure wlcore wakeirq With wlcore supporting optional wakeirqs, we can configure it for droid 4. This makes ssh connection usable with the SoC entering deeper idle states. Let's configure a wakeirq both for the wlcore GPIO and the SDIO dat1 pin in case wlcore starts supporting SDIO dat1 interrupt at some point. And let's also add the missing keep-power-in-suspend while at it. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-droid4-xt894.dts | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 04758a2a87f0..838aa3445fbe 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -359,20 +359,24 @@ &mmc3 { vmmc-supply = <&wl12xx_vmmc>; + /* uart2_tx.sdmmc3_dat1 pad as wakeirq */ interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core 0xde>; - + interrupt-names = "irq", "wakeup"; non-removable; bus-width = <4>; cap-power-off-card; + keep-power-in-suspend; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1285", "ti,wl1283"; reg = <2>; - interrupt-parent = <&gpio4>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; /* gpio100 */ + /* gpio_100 with gpmc_wait2 pad as wakeirq */ + interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>, + <&omap4_pmx_core 0x4e>; + interrupt-names = "irq", "wakeup"; ref-clock-frequency = <26000000>; tcxo-clock-frequency = <26000000>; }; From 78720aceacf0932d8475ba249535ce8e4fbbdfda Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 24 Dec 2018 09:17:45 +0100 Subject: [PATCH 012/506] ARM: dts: rockchip: move rk3036 i2s sound-dail-cells into soc dtsi The Rockchip i2s controller always only has one output connection hence #sound-dai-cells is always 0. Therefore define it in the soc dtsi itself instead of in individual boards. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 1 - arch/arm/boot/dts/rk3036.dtsi | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 0fd19f9723df..0173eb11ec28 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -310,7 +310,6 @@ }; &i2s { - #sound-dai-cells = <0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index d560fc4051c5..59c90863b0e7 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -289,6 +289,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&i2s_bus>; + #sound-dai-cells = <0>; status = "disabled"; }; From 5286abda83afeed717971724365245fb1f42f50d Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 29 Dec 2018 14:33:12 +0100 Subject: [PATCH 013/506] ARM: dts: rockchip: add HCLK_HDMI to rk3066 vio power-domain A MK808 TV stick with rk3066 processor boots normal with logo and console, but after booting the monitor remains black. This patch fixes a vblank wait time out by adding HCLK_HDMI to the vio power-domain node. The HCLK_HDMI clock is now part of the logic that enables the RK3066_PD_VIO power domain. Signed-off-by: Johan Jonker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 30dc8af0bdcb..b6b3a77da50a 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -669,6 +669,7 @@ <&cru SCLK_CIF0>, <&cru ACLK_CIF0>, <&cru HCLK_CIF0>, + <&cru HCLK_HDMI>, <&cru ACLK_IPP>, <&cru HCLK_IPP>, <&cru ACLK_RGA>, From 95e50af34d47f7496fee72d35aaefe25e23878db Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 2 Jan 2019 20:41:02 +0100 Subject: [PATCH 014/506] ARM: dts: rockchip: fix cif1_pdn pin on rk3188-bqedison2qc The powerdown pin for the second camera is gpio3_b5 not b4, so fix that. We don't have a working camera setup yet, so this is not really critical, but nevertheless better to have fixed already. Fixes: 36ead9149916 ("ARM: dts: rockchip: add BQ Edison 2 QC devicetree") Reported-by: Johan Jonker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-bqedison2qc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index a7477a09fbe8..2b5abfb48dd0 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -526,7 +526,7 @@ }; cif1_pdn: cif1-pdn { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; cif_avdd_en: cif-avdd-en { From 321514a385fa531b08f8c555e8e63fe66bfeb146 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 21 Dec 2018 17:10:12 +0100 Subject: [PATCH 015/506] ARM: dts: rockchip: add focaltech touchscreen to rk3188-bqedison2qc The Edison tablet uses a Focaltech touchscreen, with one speciality that the touchscreen resolution doesn't match the display resolution (1024x768 vs. 1280x600) which userspace will have to compensate for. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-bqedison2qc.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index 2b5abfb48dd0..887d1aa8d0e1 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -408,6 +408,21 @@ &i2c2 { clock-frequency = <400000>; status = "okay"; + + ft5606: touchscreen@3e { + compatible = "edt,edt-ft5506"; + reg = <0x3e>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int &tp_rst>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + touchscreen-inverted-y; + /* hw ts resolution does not match display */ + touchscreen-size-y = <1024>; + touchscreen-size-x = <768>; + touchscreen-swapped-x-y; + }; }; &i2c3 { From c09757064329392dd0569493741729903fdfb4f8 Mon Sep 17 00:00:00 2001 From: Katsuhiro Suzuki Date: Sun, 23 Dec 2018 19:05:30 +0900 Subject: [PATCH 016/506] arm64: dts: rockchip: add rk3328 ACODEC node This patch adds audio codec (ACODEC) node that converts to analog audio signal from I2S for rk3328. Signed-off-by: Katsuhiro Suzuki Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index ecd7f19c3542..14ea0053e408 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -672,6 +672,16 @@ }; }; + codec: codec@ff410000 { + compatible = "rockchip,rk3328-codec"; + reg = <0x0 0xff410000 0x0 0x1000>; + clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; + clock-names = "pclk", "mclk"; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + hdmiphy: phy@ff430000 { compatible = "rockchip,rk3328-hdmi-phy"; reg = <0x0 0xff430000 0x0 0x10000>; From b78442b8a2e96f63a3b5a59f62ea58f23bf67b84 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 24 Dec 2018 07:06:29 +0100 Subject: [PATCH 017/506] arm64: dts: rockchip: move rk3328 #sound-dai-cells to the soc dtsi The rk3328 i2s and spdif controllers only ever have one output connection, so as with all implementations of the rk3066 i2s controllers we can keep the #sound-dai-cells in the main dtsi instead of having it repeated in each board. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 1 - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 4 ++++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index bd937d68ca3b..2dc0fad9efa7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -290,7 +290,6 @@ &spdif { pinctrl-0 = <&spdifm0_tx>; status = "okay"; - #sound-dai-cells = <0>; spdif_p0: port { spdif_p0_0: endpoint { diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 14ea0053e408..81cc3c996e2a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -184,6 +184,7 @@ clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac 11>, <&dmac 12>; dma-names = "tx", "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -195,6 +196,7 @@ clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac 14>, <&dmac 15>; dma-names = "tx", "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -206,6 +208,7 @@ clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac 0>, <&dmac 1>; dma-names = "tx", "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -219,6 +222,7 @@ dma-names = "tx"; pinctrl-names = "default"; pinctrl-0 = <&spdifm2_tx>; + #sound-dai-cells = <0>; status = "disabled"; }; From 87bf7c7fb9fe60d3fbb50a4ea4f46d24606fd626 Mon Sep 17 00:00:00 2001 From: Katsuhiro Suzuki Date: Sun, 23 Dec 2018 19:10:26 +0900 Subject: [PATCH 018/506] arm64: dts: rockchip: enable analog audio node for rock64 The Rock64 boards has analog audio jack on it. RK3328 can output analog audio signal using I2S1 and ACODEC core. This patch adds sound node for analog audio for Rock64. Signed-off-by: Katsuhiro Suzuki Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3328-rock64.dts | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index 2dc0fad9efa7..77db0dec2fdb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -66,7 +66,8 @@ sound { compatible = "audio-graph-card"; label = "rockchip,rk3328"; - dais = <&spdif_p0>; + dais = <&i2s1_p0 + &spdif_p0>; }; spdif-dit { @@ -81,6 +82,16 @@ }; }; +&codec { + status = "okay"; + + port@0 { + codec_p0_0: endpoint { + remote-endpoint = <&i2s1_p0_0>; + }; + }; +}; + &cpu0 { cpu-supply = <&vdd_arm>; }; @@ -243,6 +254,18 @@ }; }; +&i2s1 { + status = "okay"; + + i2s1_p0: port { + i2s1_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&codec_p0_0>; + }; + }; +}; + &io_domains { status = "okay"; From 34a97fcc71c26f492682e839a812e6e44da48cf7 Mon Sep 17 00:00:00 2001 From: Harald Geyer Date: Wed, 19 Dec 2018 15:40:17 +0000 Subject: [PATCH 019/506] arm64: dts: allwinner: a64: Add PMU node This is necessary to use 'perf' for cache profiling etc. Tested on Teres I Laptop. Signed-off-by: Harald Geyer Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 837a03dee875..bf9b719481c4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -142,6 +142,15 @@ clock-output-names = "ext-osc32k"; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + psci { compatible = "arm,psci-0.2"; method = "smc"; From 7e345d25c796abc8561786baaf59f30bc082ef1f Mon Sep 17 00:00:00 2001 From: Harald Geyer Date: Sun, 16 Dec 2018 09:25:24 +0000 Subject: [PATCH 020/506] ARM: dts: sun4i-a10: Add PMU node This is necessary to use 'perf' for cache profiling etc. Tested on cubieboard with 'perf stat echo foo'. Signed-off-by: Harald Geyer Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 5d46bb0139fa..a2fb473cbb9d 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -184,6 +184,11 @@ status = "disabled"; }; + pmu { + compatible = "arm,cortex-a8-pmu"; + interrupts = <3>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; From 09c6572290f018d73ec2e812e28bada34d41815f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 6 Dec 2018 15:02:04 +0100 Subject: [PATCH 021/506] ARM: dts: sun7i: bananapi: Add GPIO banks regulators The bananapi has all its bank regulators tied to the 3v3 static regulator. Make sure it's properly represented. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-bananapi.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts index 556b1b591c5d..81bc85d398c1 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -191,6 +191,11 @@ }; &pio { + vcc-pa-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pe-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; gpio-line-names = /* PA */ "ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3", From 7aa69a47ecedb5368d862d0d8a2d6537b48e5501 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 3 Dec 2018 16:12:41 +0100 Subject: [PATCH 022/506] ARM: dts: stout: Convert to new LVDS DT bindings As of commit 6d2ca85279becdff ("dt-bindings: display: renesas: Deprecate LVDS support in the DU bindings"), the internal LVDS encoder has DT bindings separate from the DU. The Lager device tree was ported over to the new model, but the Stout device tree was forgotten. Fixes: 15a1ff30d8f9bd83 ("ARM: dts: r8a7790: Convert to new LVDS DT bindings") Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Tested-by: Marek Vasut Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-stout.dts | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts index 629da4cee1b9..7a7d3b84d1a6 100644 --- a/arch/arm/boot/dts/r8a7790-stout.dts +++ b/arch/arm/boot/dts/r8a7790-stout.dts @@ -94,9 +94,8 @@ status = "okay"; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>, <&osc1_clk>; - clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0"; + clock-names = "du.0", "du.1", "du.2", "dclkin.0"; ports { port@0 { @@ -104,11 +103,21 @@ remote-endpoint = <&adv7511_in>; }; }; + }; +}; + +&lvds0 { + ports { port@1 { lvds_connector0: endpoint { }; }; - port@2 { + }; +}; + +&lvds1 { + ports { + port@1 { lvds_connector1: endpoint { }; }; From 55327bff832c9903a9133cdad56783b54bd8596a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 7 Dec 2018 11:27:46 +0000 Subject: [PATCH 023/506] ARM: dts: iwg23s-sbc: Enable RTC Enable NXP pcf85263 real time clock for the iWave SBC based on RZ/G1C. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index 40b7f98d6013..77d18242ef59 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -84,12 +84,30 @@ clock-frequency = <20000000>; }; +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + &pfc { avb_pins: avb { groups = "avb_mdio", "avb_gmii_tx_rx"; function = "avb"; }; + i2c3_pins: i2c3 { + groups = "i2c3_c"; + function = "i2c3"; + }; + mmc_pins_uhs: mmc_uhs { groups = "mmc_data8", "mmc_ctrl"; function = "mmc"; From 35713c782ef7c715eb0bc2f43d9f31cc7ec08063 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 5 Dec 2018 09:06:55 +0000 Subject: [PATCH 024/506] ARM: dts: r8a7744: Fix sorting of vsp and msiof nodes This patch fixes sorting of vsp and msiof nodes. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 150 ++++++++++++++++----------------- 1 file changed, 75 insertions(+), 75 deletions(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 04148d608fc4..8d25a0a0594a 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -998,6 +998,54 @@ status = "disabled"; }; + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7744", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 000>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7744", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 208>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7744", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 205>; + status = "disabled"; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; @@ -1068,54 +1116,6 @@ status = "disabled"; }; - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7744", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 000>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7744", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 208>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7744", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&cpg 205>; - status = "disabled"; - }; - can0: can@e6e80000 { compatible = "renesas,can-r8a7744", "renesas,rcar-gen2-can"; @@ -1589,33 +1589,6 @@ resets = <&cpg 408>; }; - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - pciec: pcie@fe000000 { compatible = "renesas,pcie-r8a7744", "renesas,pcie-rcar-gen2"; @@ -1644,6 +1617,33 @@ status = "disabled"; }; + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + du: display@feb00000 { reg = <0 0xfeb00000 0 0x40000>, <0 0xfeb90000 0 0x1c>; From 072b817589b17660ef19c31d89f7b981dbed3fd2 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 10 Dec 2018 11:57:57 +0000 Subject: [PATCH 025/506] ARM: dts: r8a7743: Remove generic compatible string from iic3 The iic3 block on RZ/G1M does not support automatic transmission, unlike other R-Car SoC's. So dropping the compatibility with the generic version. Fixes: f523405f2a22cc0c307 ("ARM: dts: r8a7743: Add IIC cores to dtsi") Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 3cc33f7ff7fe..169fddc33229 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -564,9 +564,7 @@ /* doesn't need pinmux */ #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,iic-r8a7743", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a7743"; reg = <0 0xe60b0000 0 0x425>; interrupts = ; clocks = <&cpg CPG_MOD 926>; From aeefe7394ca9a77b264963beaba01b4e85a9142c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 10 Dec 2018 12:07:03 +0000 Subject: [PATCH 026/506] ARM: dts: r8a7743: Remove aliases from SoC dtsi This patch removes aliases from SoC dtsi tree. Device aliases are board-specific, if needed define it in board dts rather than SoC dtsi. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 169fddc33229..19e96e2e2e55 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -15,25 +15,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &iic0; - i2c7 = &iic1; - i2c8 = &iic3; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - spi3 = &msiof2; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. From 383f6024981d32425fa453bf2e66b546fdbc1314 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 10 Dec 2018 11:52:30 +0000 Subject: [PATCH 027/506] ARM: dts: r8a7743: Fix sorting of rwdt node Watchdog node is incorrectly placed on r8a7743 SoC dtsi. This patch fixes the sorting order. Fixes: b5beb5d4c81c358f50a8310108 ("ARM: dts: r8a7743: Add watchdog support to SoC dtsi") Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 19e96e2e2e55..24e6c2b67473 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -135,6 +135,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7743-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7743", "renesas,rcar-gen2-gpio"; @@ -291,16 +301,6 @@ reg = <0 0xe6160000 0 0x100>; }; - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7743-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a7743-sysc"; reg = <0 0xe6180000 0 0x200>; From 9d16c4a10e072e6dd5ec526cd45b37ee7dca06c3 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 16 Dec 2018 13:47:44 +0200 Subject: [PATCH 028/506] arm64: dts: renesas: r8a77990: ebisu: Add backlight Add the backlight device for the LVDS1 output, in preparation for panel support. Signed-off-by: Laurent Pinchart Reviewed-by: Ulrich Hecht Signed-off-by: Simon Horman --- .../arm64/boot/dts/renesas/r8a77990-ebisu.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 62bdddcbbae7..24beb0e22cb0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -39,6 +39,16 @@ clock-frequency = <11289600>; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 50000>; + + brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>; + default-brightness-level = <10>; + + power-supply = <®_12p0v>; + }; + cvbs-in { compatible = "composite-video-connector"; label = "CVBS IN"; @@ -184,6 +194,15 @@ clock-frequency = <24576000>; }; + reg_12p0v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "D12.0V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + x13_clk: x13 { compatible = "fixed-clock"; #clock-cells = <0>; From a06ad4385f180b476ceca811a60ba00f3f65c12e Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 16 Dec 2018 13:32:17 +0200 Subject: [PATCH 029/506] arm64: dts: renesas: r8a77995: draak: Set better backlight levels The backlight levels provided in the Draak DT produce a perceived brightness very biased towards high brightness. Use better brightness levels based on the CIE 1931 formula. Signed-off-by: Laurent Pinchart Reviewed-by: Ulrich Hecht Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 89df9bc844c0..db2bed1751b8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -28,8 +28,8 @@ compatible = "pwm-backlight"; pwms = <&pwm1 0 50000>; - brightness-levels = <256 128 64 16 8 4 0>; - default-brightness-level = <6>; + brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>; + default-brightness-level = <10>; power-supply = <®_12p0v>; enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; From 12749350567c819d8a35a405743313bd869c95c0 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 5 Dec 2018 11:44:19 -0800 Subject: [PATCH 030/506] dt-bindings: arm: Convert Renesas board/soc bindings to json-schema Convert Renesas SoC bindings to DT schema format using json-schema. v2.1 [Simon Horman] - rebased on renesas-devel-20181204-v4.20-rc5 + Added r8a7744 development platform and SoM + Correct RZ/G2E part number - Update MAINTAINERS Signed-off-by: Rob Herring Signed-off-by: Simon Horman --- .../devicetree/bindings/arm/renesas.yaml | 228 ++++++++++++++++++ .../devicetree/bindings/arm/shmobile.txt | 155 ------------ MAINTAINERS | 4 +- 3 files changed, 230 insertions(+), 157 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/renesas.yaml delete mode 100644 Documentation/devicetree/bindings/arm/shmobile.txt diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml new file mode 100644 index 000000000000..5e9d4864a600 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -0,0 +1,228 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/shmobile.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings + +maintainers: + - Geert Uytterhoeven + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Emma Mobile EV2 + items: + - enum: + - renesas,kzm9d # Kyoto Microcomputer Co. KZM-A9-Dual + - const: renesas,emev2 + + - description: RZ/A1H (R7S72100) + items: + - enum: + - renesas,genmai # Genmai (RTK772100BC00000BR) + - renesas,gr-peach # GR-Peach (X28A-M01-E/F) + - renesas,rskrza1 # RSKRZA1 (YR0K77210C000BE) + - const: renesas,r7s72100 + + - description: RZ/A2 (R7S9210) + items: + - const: renesas,r7s9210 + + - description: SH-Mobile AG5 (R8A73A00/SH73A0) + items: + - enum: + - renesas,kzm9g # Kyoto Microcomputer Co. KZM-A9-GT + - const: renesas,sh73a0 + + - description: R-Mobile APE6 (R8A73A40) + items: + - enum: + - renesas,ape6evm + - const: renesas,r8a73a4 + + - description: R-Mobile A1 (R8A77400) + items: + - enum: + - renesas,armadillo800eva # Atmark Techno Armadillo-800 EVA + - const: renesas,r8a7740 + + - description: RZ/G1H (R8A77420) + items: + - const: renesas,r8a7742 + + - description: RZ/G1M (R8A77430) + items: + - enum: + # iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven) + - iwave,g20d + - const: iwave,g20m + - const: renesas,r8a7743 + + - items: + - enum: + # iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) + - iwave,g20m + - renesas,sk-rzg1m # SK-RZG1M (YR8A77430S000BE) + - const: renesas,r8a7743 + + - description: RZ/G1N (R8A77440) + items: + - enum: + # iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven) + - iwave,g20d + - const: iwave,g20m + - const: renesas,r8a7744 + + - items: + - enum: + # iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven) + - iwave,g20m + - const: renesas,r8a7744 + + - description: RZ/G1E (R8A77450) + items: + - enum: + - iwave,g22m # iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM) + - renesas,sk-rzg1e # SK-RZG1E (YR8A77450S000BE) + - const: renesas,r8a7745 + + - description: iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D) + items: + - const: iwave,g22d + - const: iwave,g22m + - const: renesas,r8a7745 + + - description: RZ/G1C (R8A77470) + items: + - enum: + - iwave,g23s #iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S) + - const: renesas,r8a77470 + + - description: RZ/G2M (R8A774A1) + items: + - const: renesas,r8a774a1 + + - description: RZ/G2E (R8A774C0) + items: + - const: renesas,r8a774c0 + + - description: R-Car M1A (R8A77781) + items: + - enum: + - renesas,bockw + - const: renesas,r8a7778 + + - description: R-Car H1 (R8A77790) + items: + - enum: + - renesas,marzen # Marzen (R0P7779A00010S) + - renesas,stout # Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) + - const: renesas,r8a7779 + + - description: R-Car H2 (R8A77900) + items: + - enum: + - renesas,lager # Lager (RTP0RC7790SEB00010S) + - const: renesas,r8a7790 + + - description: R-Car M2-W (R8A77910) + items: + - enum: + - renesas,henninger + - renesas,koelsch # Koelsch (RTP0RC7791SEB00010S) + - renesas,porter # Porter (M2-LCDP) + - const: renesas,r8a7791 + + - description: R-Car V2H (R8A77920) + items: + - enum: + - renesas,blanche # Blanche (RTP0RC7792SEB00010S) + - renesas,wheat # Wheat (RTP0RC7792ASKB0000JE) + - const: renesas,r8a7792 + + - description: R-Car M2-N (R8A77930) + items: + - enum: + - renesas,gose # Gose (RTP0RC7793SEB00010S) + - const: renesas,r8a7793 + + - description: R-Car E2 (R8A77940) + items: + - enum: + - renesas,alt # Alt (RTP0RC7794SEB00010S) + - renesas,silk # SILK (RTP0RC7794LCB00011S) + - const: renesas,r8a7794 + + - description: R-Car H3 (R8A77950) + items: + - enum: + # H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1)) + # H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0)) + - renesas,h3ulcb + - renesas,salvator-x # Salvator-X (RTP0RC7795SIPB0010S) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S) + - const: renesas,r8a7795 + + - description: R-Car M3-W (R8A77960) + items: + - enum: + - renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0)) + - renesas,salvator-x # Salvator-X (RTP0RC7796SIPB0011S) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S) + - const: renesas,r8a7796 + + - description: Kingfisher (SBEV-RCAR-KF-M03) + items: + - const: shimafuji,kingfisher + - enum: + - renesas,h3ulcb + - renesas,m3ulcb + - enum: + - renesas,r8a7795 + - renesas,r8a7796 + + - description: R-Car M3-N (R8A77965) + items: + - enum: + - renesas,m3nulcb # M3NULCB (R-Car Starter Kit Pro, RTP0RC77965SKBX010SA00 (M3-N ES1.1)) + - renesas,salvator-x # Salvator-X (RTP0RC7796SIPB0011S (M3-N)) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S) + - const: renesas,r8a77965 + + - description: R-Car V3M (R8A77970) + items: + - enum: + - renesas,eagle # Eagle (RTP0RC77970SEB0010S) + - renesas,v3msk # V3MSK (Y-ASK-RCAR-V3M-WS10) + - const: renesas,r8a77970 + + - description: R-Car V3H (R8A77980) + items: + - enum: + - renesas,condor # Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01) + - renesas,v3hsk # V3HSK (Y-ASK-RCAR-V3H-WS10) + - const: renesas,r8a77980 + + - description: R-Car E3 (R8A77990) + items: + - enum: + - renesas,ebisu # Ebisu (RTP0RC77990SEB0010S) + - const: renesas,r8a77990 + + - description: R-Car D3 (R8A77995) + items: + - enum: + - renesas,draak # Draak (RTP0RC77995SEB0010S) + - const: renesas,r8a77995 + + - description: RZ/N1D (R9A06G032) + items: + - enum: + - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) + - const: renesas,r9a06g032 + +... diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt deleted file mode 100644 index 7f91c2a8b54e..000000000000 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ /dev/null @@ -1,155 +0,0 @@ -Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings --------------------------------------------------------------------- - -SoCs: - - - Emma Mobile EV2 - compatible = "renesas,emev2" - - RZ/A1H (R7S72100) - compatible = "renesas,r7s72100" - - RZ/A2 (R7S9210) - compatible = "renesas,r7s9210" - - SH-Mobile AG5 (R8A73A00/SH73A0) - compatible = "renesas,sh73a0" - - R-Mobile APE6 (R8A73A40) - compatible = "renesas,r8a73a4" - - R-Mobile A1 (R8A77400) - compatible = "renesas,r8a7740" - - RZ/G1H (R8A77420) - compatible = "renesas,r8a7742" - - RZ/G1M (R8A77430) - compatible = "renesas,r8a7743" - - RZ/G1N (R8A77440) - compatible = "renesas,r8a7744" - - RZ/G1E (R8A77450) - compatible = "renesas,r8a7745" - - RZ/G1C (R8A77470) - compatible = "renesas,r8a77470" - - RZ/G2M (R8A774A1) - compatible = "renesas,r8a774a1" - - RZ/G2E (R8A774C0) - compatible = "renesas,r8a774c0" - - R-Car M1A (R8A77781) - compatible = "renesas,r8a7778" - - R-Car H1 (R8A77790) - compatible = "renesas,r8a7779" - - R-Car H2 (R8A77900) - compatible = "renesas,r8a7790" - - R-Car M2-W (R8A77910) - compatible = "renesas,r8a7791" - - R-Car V2H (R8A77920) - compatible = "renesas,r8a7792" - - R-Car M2-N (R8A77930) - compatible = "renesas,r8a7793" - - R-Car E2 (R8A77940) - compatible = "renesas,r8a7794" - - R-Car H3 (R8A77950) - compatible = "renesas,r8a7795" - - R-Car M3-W (R8A77960) - compatible = "renesas,r8a7796" - - R-Car M3-N (R8A77965) - compatible = "renesas,r8a77965" - - R-Car V3M (R8A77970) - compatible = "renesas,r8a77970" - - R-Car V3H (R8A77980) - compatible = "renesas,r8a77980" - - R-Car E3 (R8A77990) - compatible = "renesas,r8a77990" - - R-Car D3 (R8A77995) - compatible = "renesas,r8a77995" - - RZ/N1D (R9A06G032) - compatible = "renesas,r9a06g032" - -Boards: - - - Alt (RTP0RC7794SEB00010S) - compatible = "renesas,alt", "renesas,r8a7794" - - APE6-EVM - compatible = "renesas,ape6evm", "renesas,r8a73a4" - - Atmark Techno Armadillo-800 EVA - compatible = "renesas,armadillo800eva", "renesas,r8a7740" - - Blanche (RTP0RC7792SEB00010S) - compatible = "renesas,blanche", "renesas,r8a7792" - - BOCK-W - compatible = "renesas,bockw", "renesas,r8a7778" - - Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01) - compatible = "renesas,condor", "renesas,r8a77980" - - Draak (RTP0RC77995SEB0010S) - compatible = "renesas,draak", "renesas,r8a77995" - - Eagle (RTP0RC77970SEB0010S) - compatible = "renesas,eagle", "renesas,r8a77970" - - Ebisu (RTP0RC77990SEB0010S) - compatible = "renesas,ebisu", "renesas,r8a77990" - - Genmai (RTK772100BC00000BR) - compatible = "renesas,genmai", "renesas,r7s72100" - - GR-Peach (X28A-M01-E/F) - compatible = "renesas,gr-peach", "renesas,r7s72100" - - Gose (RTP0RC7793SEB00010S) - compatible = "renesas,gose", "renesas,r8a7793" - - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1)) - H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0)) - compatible = "renesas,h3ulcb", "renesas,r8a7795" - - Henninger - compatible = "renesas,henninger", "renesas,r8a7791" - - iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S) - compatible = "iwave,g23s", "renesas,r8a77470" - - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D) - compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745" - - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM) - compatible = "iwave,g22m", "renesas,r8a7745" - - iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven) - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743" - - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) - compatible = "iwave,g20m", "renesas,r8a7743" - - iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven) - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744" - - iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven) - compatible = "iwave,g20m", "renesas,r8a7744" - - Kingfisher (SBEV-RCAR-KF-M03) - compatible = "shimafuji,kingfisher" - - Koelsch (RTP0RC7791SEB00010S) - compatible = "renesas,koelsch", "renesas,r8a7791" - - Kyoto Microcomputer Co. KZM-A9-Dual - compatible = "renesas,kzm9d", "renesas,emev2" - - Kyoto Microcomputer Co. KZM-A9-GT - compatible = "renesas,kzm9g", "renesas,sh73a0" - - Lager (RTP0RC7790SEB00010S) - compatible = "renesas,lager", "renesas,r8a7790" - - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0)) - compatible = "renesas,m3ulcb", "renesas,r8a7796" - - M3NULCB (R-Car Starter Kit Pro, RTP0RC77965SKBX010SA00 (M3-N ES1.1)) - compatible = "renesas,m3nulcb", "renesas,r8a77965" - - Marzen (R0P7779A00010S) - compatible = "renesas,marzen", "renesas,r8a7779" - - Porter (M2-LCDP) - compatible = "renesas,porter", "renesas,r8a7791" - - RSKRZA1 (YR0K77210C000BE) - compatible = "renesas,rskrza1", "renesas,r7s72100" - - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) - compatible = "renesas,rzn1d400-db", "renesas,r9a06g032" - - Salvator-X (RTP0RC7795SIPB0010S) - compatible = "renesas,salvator-x", "renesas,r8a7795" - - Salvator-X (RTP0RC7796SIPB0011S) - compatible = "renesas,salvator-x", "renesas,r8a7796" - - Salvator-X (RTP0RC7796SIPB0011S (M3-N)) - compatible = "renesas,salvator-x", "renesas,r8a77965" - - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S) - compatible = "renesas,salvator-xs", "renesas,r8a7795" - - Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S) - compatible = "renesas,salvator-xs", "renesas,r8a7796" - - Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S) - compatible = "renesas,salvator-xs", "renesas,r8a77965" - - SILK (RTP0RC7794LCB00011S) - compatible = "renesas,silk", "renesas,r8a7794" - - SK-RZG1E (YR8A77450S000BE) - compatible = "renesas,sk-rzg1e", "renesas,r8a7745" - - SK-RZG1M (YR8A77430S000BE) - compatible = "renesas,sk-rzg1m", "renesas,r8a7743" - - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) - compatible = "renesas,stout", "renesas,r8a7790" - - V3HSK (Y-ASK-RCAR-V3H-WS10) - compatible = "renesas,v3hsk", "renesas,r8a77980" - - V3MSK (Y-ASK-RCAR-V3M-WS10) - compatible = "renesas,v3msk", "renesas,r8a77970" - - Wheat (RTP0RC7792ASKB0000JE) - compatible = "renesas,wheat", "renesas,r8a7792" diff --git a/MAINTAINERS b/MAINTAINERS index 32d444476a90..df275b4174dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1997,7 +1997,7 @@ Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next S: Supported F: arch/arm64/boot/dts/renesas/ -F: Documentation/devicetree/bindings/arm/shmobile.txt +F: Documentation/devicetree/bindings/arm/renesas.yaml F: drivers/soc/renesas/ F: include/linux/soc/renesas/ @@ -2116,7 +2116,7 @@ F: arch/arm/boot/dts/sh* F: arch/arm/configs/shmobile_defconfig F: arch/arm/include/debug/renesas-scif.S F: arch/arm/mach-shmobile/ -F: Documentation/devicetree/bindings/arm/shmobile.txt +F: Documentation/devicetree/bindings/arm/renesas.yaml F: drivers/soc/renesas/ F: include/linux/soc/renesas/ From ae3f46c8271ba735087ca9251095606788cb4be9 Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Fri, 4 Jan 2019 13:23:46 -0600 Subject: [PATCH 031/506] arm64: dts: stratix10: Add Stratix10 SMMU support Now there are device tree clocks for the ARM64 SMMU, add SMMU support to the Stratix10 Device Tree which includes adding the SMMU node and adding IOMMU stream ids to the SMMU peripherals. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen --- .../boot/dts/altera/socfpga_stratix10.dtsi | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index b2c9bb664595..e3f5eaa3657d 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -161,6 +161,7 @@ tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; + iommus = <&smmu 1>; status = "disabled"; }; @@ -177,6 +178,7 @@ tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; + iommus = <&smmu 2>; status = "disabled"; }; @@ -193,6 +195,7 @@ tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; + iommus = <&smmu 3>; status = "disabled"; }; @@ -303,6 +306,7 @@ clocks = <&clkmgr STRATIX10_L4_MP_CLK>, <&clkmgr STRATIX10_SDMMC_CLK>; clock-names = "biu", "ciu"; + iommus = <&smmu 5>; status = "disabled"; }; @@ -336,6 +340,29 @@ reg = <0xffd11000 0x1000>; }; + smmu: iommu@fa000000 { + compatible = "arm,mmu-500", "arm,smmu-v2"; + reg = <0xfa000000 0x40000>; + #global-interrupts = <2>; + #iommu-cells = <1>; + clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; + clock-names = "iommu"; + interrupt-parent = <&intc>; + interrupts = <0 128 4>, /* Global Secure Fault */ + <0 129 4>, /* Global Non-secure Fault */ + /* Non-secure Context Interrupts (32) */ + <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, + <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, + <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, + <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, + <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, + <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, + <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, + <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; + stream-match-mask = <0x7ff0>; + status = "disabled"; + }; + spi0: spi@ffda4000 { compatible = "snps,dw-apb-ssi"; #address-cells = <1>; @@ -445,6 +472,7 @@ resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; clocks = <&clkmgr STRATIX10_USB_CLK>; + iommus = <&smmu 6>; status = "disabled"; }; @@ -457,6 +485,7 @@ resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; clocks = <&clkmgr STRATIX10_USB_CLK>; + iommus = <&smmu 7>; status = "disabled"; }; From 0bb677d9e552533e8365892c7bd9426b5a6d5d54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Chmiel?= Date: Wed, 19 Dec 2018 16:57:04 +0100 Subject: [PATCH 032/506] ARM: dts: s5pv210: Add node for exynos-rotator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add node for Exynos Rorator device, so it can be used on all S5Pv210 based devices. Signed-off-by: Paweł Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 12eac8930eac..d715d184bc56 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -542,6 +542,15 @@ #dma-requests = <1>; }; + rotator: rotator@fa300000 { + compatible = "samsung,s5pv210-rotator"; + reg = <0xfa300000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <4>; + clocks = <&clocks CLK_ROTATOR>; + clock-names = "rotator"; + }; + i2c1: i2c@fab00000 { compatible = "samsung,s3c2440-i2c"; reg = <0xfab00000 0x1000>; From 9563793d15878f457aecf3dd30b19572809a1c34 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Chmiel?= Date: Fri, 28 Dec 2018 17:18:14 +0100 Subject: [PATCH 033/506] ARM: dts: s5pv210: Use correct fimd variant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since we have separate compatible for S5Pv210 FIMD, let's use it rather than using one from Exynos4210. Signed-off-by: Paweł Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index d715d184bc56..cc22c9db80d2 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -511,7 +511,7 @@ }; fimd: fimd@f8000000 { - compatible = "samsung,exynos4210-fimd"; + compatible = "samsung,s5pv210-fimd"; interrupt-parent = <&vic2>; reg = <0xf8000000 0x20000>; interrupt-names = "fifo", "vsync", "lcd_sys"; From f143f8d68077d8d363cabd7412ecc86cede25bdc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Chmiel?= Date: Fri, 28 Dec 2018 17:18:15 +0100 Subject: [PATCH 034/506] ARM: dts: s5pv210: Remove hardcoded bootargs on Galaxy S and Fascinate 4G MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since we have U-Boot (flashed in place of stock kernel), it's not needed anymore to hardcode bootargs on every Aries-family board. Signed-off-by: Paweł Chmiel [krzk: Squash changes to fascinate4g and galaxys into one commit] Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-fascinate4g.dts | 7 ------- arch/arm/boot/dts/s5pv210-galaxys.dts | 7 ------- 2 files changed, 14 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts index ccf761b1babf..07a8d9bbe5b8 100644 --- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -11,13 +11,6 @@ chosen { stdout-path = &uart2; - /* - * It's hard to change those parameters in stock bootloader, - * since it requires special hardware/cable. - * Let's hardocde bootargs for now, till u-boot port is finished, - * with which it should be easier. - */ - bootargs = "root=/dev/mmcblk1p1 rw rootwait ignore_loglevel earlyprintk"; }; gpio-keys { diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts index 842276749717..cf161bbfbacf 100644 --- a/arch/arm/boot/dts/s5pv210-galaxys.dts +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -11,13 +11,6 @@ chosen { stdout-path = &uart2; - /* - * It's hard to change those parameters in stock bootloader, - * since it requires special hardware/cable. - * Let's hardocde bootargs for now, till u-boot port is finished, - * with which it should be easier. - */ - bootargs = "root=/dev/mmcblk2p1 rw rootwait ignore_loglevel earlyprintk"; }; nand_pwrseq: nand-pwrseq { From 26b933b9436b9205787f9058683f3a1f09089876 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 12 Dec 2018 16:31:08 +0000 Subject: [PATCH 035/506] ARM: dts: at91: at91-sama5d27_som1: add QSPI1 + SPI NOR memory nodes Configure the QSPI1 controller pin muxing and declare the jedec,spi-nor memory (SST26VF064). Signed-off-by: Claudiu Beznea [tudor.ambarus@microchip.com: add spi-rx/tx-bus-width, drop partitions, reword commit.] Signed-off-by: Tudor Ambarus Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi index cf0087b4c9e1..33a159c0163f 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi @@ -62,6 +62,20 @@ ahb { apb { + qspi1: spi@f0024000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; + }; + macb0: ethernet@f8008000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_default>; @@ -78,6 +92,22 @@ pinctrl@fc038000 { + pinctrl_qspi1_default: qspi1_default { + sck_cs { + pinmux = , + ; + bias-disable; + }; + + data { + pinmux = , + , + , + ; + bias-pull-up; + }; + }; + pinctrl_macb0_default: macb0_default { pinmux = , , From c2dfab7e40095b29668a4022a5558549e544e3cd Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 12 Dec 2018 16:31:11 +0000 Subject: [PATCH 036/506] ARM: dts: at91: at91-sama5d27_som1_ek: enable qspi1 memory Enable qspi1. Signed-off-by: Claudiu Beznea Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 4a258867ddf1..a48180555ef5 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -109,6 +109,10 @@ status = "okay"; }; + qspi1: spi@f0024000 { + status = "okay"; + }; + spi0: spi@f8000000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; From 31f031f73a01fb83fd6f4abfff04a79b360219e1 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 21 Dec 2018 18:11:49 +0000 Subject: [PATCH 037/506] ARM: dts: at91: replace gpio-key,wakeup with wakeup-source property Most of the legacy "gpio-key,wakeup" property are already replaced with "wakeup-source". However few occurrences of old property has popped up again, probably from the remnants in downstream trees. Almost all of those were remove couple of years back. Replace the legacy properties with the unified "wakeup-source" property introduced in the commit 700a38b27eef ("Input: gpio_keys - switch to using generic device properties") Cc: Alexandre Belloni Cc: Peter Rosin Cc: Nicolas Ferre Signed-off-by: Sudeep Holla Acked-by: Peter Rosin Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-nattis-2-natte-2.dts | 2 +- arch/arm/boot/dts/at91-wb45n.dts | 2 +- arch/arm/boot/dts/at91-wb50n.dts | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts index 0f6d335125e2..f245944bd5d7 100644 --- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts +++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts @@ -22,7 +22,7 @@ wakeup { label = "Wakeup"; linux,code = <10>; - gpio-key,wakeup; + wakeup-source; gpios = <&pioB 27 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/at91-wb45n.dts b/arch/arm/boot/dts/at91-wb45n.dts index 5b9512a6c89c..54d130c92185 100644 --- a/arch/arm/boot/dts/at91-wb45n.dts +++ b/arch/arm/boot/dts/at91-wb45n.dts @@ -22,7 +22,7 @@ label = "IRQBTN"; linux,code = <99>; gpios = <&pioB 18 GPIO_ACTIVE_LOW>; - gpio-key,wakeup = <1>; + wakeup-source; }; }; }; diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/at91-wb50n.dts index 8cecc7051a86..a5e45bb95c04 100644 --- a/arch/arm/boot/dts/at91-wb50n.dts +++ b/arch/arm/boot/dts/at91-wb50n.dts @@ -23,7 +23,7 @@ label = "BTNESC"; linux,code = <1>; /* ESC button */ gpios = <&pioA 10 GPIO_ACTIVE_LOW>; - gpio-key,wakeup = <1>; + wakeup-source; }; irqbtn@31 { @@ -31,7 +31,7 @@ label = "IRQBTN"; linux,code = <99>; /* SysReq button */ gpios = <&pioE 31 GPIO_ACTIVE_LOW>; - gpio-key,wakeup = <1>; + wakeup-source; }; }; From 26e9ffeb2c04f0f577d0179e7eca8e1d54f9e050 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 9 Jan 2019 23:02:53 +0800 Subject: [PATCH 038/506] ARM: dts: sun8i: r40: Add pinmux settings for UART3 on PG pingroup UART3 on the PG pingroup on the R40 SoC is commonly used to connect the bluetooth controller in a WiFi+Bluetooth combo chip, with the WiFi bits also on the PG pingroup. This patch adds two device nodes for UART3 on PG pingroup, one for the RX/TX pins, and one for the RTS/CTS pins. Consumers can reference either just the RX/TX pinmux setting or both, depending on the application. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 89762dbefe42..f1fcfa0bdce0 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -389,6 +389,16 @@ pins = "PB22", "PB23"; function = "uart0"; }; + + uart3_pg_pins: uart3-pg-pins { + pins = "PG6", "PG7"; + function = "uart3"; + }; + + uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { + pins = "PG8", "PG9"; + function = "uart3"; + }; }; wdt: watchdog@1c20c90 { From a5a4bc14914faf219336d71c71595975b8112ff7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 9 Jan 2019 23:02:54 +0800 Subject: [PATCH 039/506] ARM: dts: sun8i: r40: Add pinmux setting for CLK_OUT_A CLK_OUT_A, an external clock output function driven from the clock control unit, on the R40 is sometimes used to provide a low rate low power clock to a WiFi or Bluetooth controller. This patch adds a pinmux setting for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index f1fcfa0bdce0..06b685869f52 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -342,6 +342,11 @@ #interrupt-cells = <3>; #gpio-cells = <3>; + clk_out_a_pin: clk-out-a-pin { + pins = "PI12"; + function = "clk_out_a"; + }; + gmac_rgmii_pins: gmac-rgmii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", From e5c6e693be831c1bba9b4f8f1da597fb5514deca Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 9 Jan 2019 23:02:55 +0800 Subject: [PATCH 040/506] ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix WiFi regulator definitions The design of the Bananapi M2 Ultra has both DLDO1 and DLDO2 regulators provide power to the WiFi+BT module, which is based on the Broadcom BCM43438 or BCM43430 chip. Each regulator output from the PMIC can supply up to 200 mA. The datasheet of the chip suggests a maximum power draw of up to 360 mA when transmitting, thus requiring two outputs from the PMIC to handle the load. However the device tree only references one of them, leaving the other unused and possibly turned off. This patch marks both as always-on, since we don't have a proper binding to specify two regulators as "bound together". The name and constraints of DLDO2 are also added. Fixes: da7ac948fa93 ("ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 438b7b44dab3..1a6794e63b90 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -250,12 +250,27 @@ regulator-name = "vcc-wifi-io"; }; +/* + * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same + * time, with the two being in sync, to be able to meet maximum power + * consumption during transmits. Since this is not really supported + * right now, just use the two as always on, and we will fix it later. + */ + ®_dldo2 { + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc-wifi"; }; +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; +}; + ®_dldo4 { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; From 1e5f1db4ccd8348a21da55bff82f4263000879ef Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 9 Jan 2019 23:02:56 +0800 Subject: [PATCH 041/506] ARM: dts: sun8i: r40: bananapi-m2-ultra: Add Bluetooth device node The AP6212 is based on the Broadcom BCM43430 or BCM43438. The WiFi side identifies as BCM43430, while the Bluetooth side identifies as BCM43438. The Bluetooth side is connected to UART3 in a 4 wire configuration. Same as the WiFi side, due to being the same chip and package, DLDO1 and DLDO2 regulator outputs from the PMIC provide overall power via VBAT and I/O power via VDDIO. The CLK_OUT_A clock output from the SoC provides the LPO low power clock at 32.768 kHz. This patch enables Bluetooth on this board, and also adds the missing LPO clock on the WiFi side. There is also a PCM connection for Bluetooth, but this is not covered here. The LPO clock is fed from CLK_OUT_A, which needs to be muxed on pin PI12. This can be represented in multiple ways. This patch puts the pinctrl property in the pin controller node. This is due to limitations in Linux, where pinmux settings, even the same one, can not be shared by multiple devices. Thus we cannot put it in both the WiFi and Bluetooth device nodes. Putting it the CCU node is another option, but Linux's CCU driver does not handle pinctrl. Also the pin controller is guaranteed to be initialized after the CCU, when clocks are available. And any other devices that use muxed pins are guaranteed to be initialized after the pin controller. Thus having the CLK_OUT_A pinmux reference be in the pin controller node is a good choice without having to deal with implementation issues. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- .../boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 1a6794e63b90..c488aaacbd68 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -102,6 +102,8 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ + clocks = <&ccu CLK_OUTA>; + clock-names = "ext_clock"; }; }; @@ -196,6 +198,11 @@ status = "okay"; }; +&pio { + pinctrl-names = "default"; + pinctrl-0 = <&clk_out_a_pin>; +}; + ®_aldo2 { regulator-always-on; regulator-min-microvolt = <2500000>; @@ -293,6 +300,25 @@ status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&ccu CLK_OUTA>; + clock-names = "lpo"; + vbat-supply = <®_dldo2>; + vddio-supply = <®_dldo1>; + device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + /* TODO host wake line connected to PMIC GPIO pins */ + shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ + max-speed = <1500000>; + }; +}; + &usbphy { usb1_vbus-supply = <®_vcc5v0>; usb2_vbus-supply = <®_vcc5v0>; From c322e85ad1d4c4459e0c722d6467772a39a7743d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 9 Jan 2019 23:02:57 +0800 Subject: [PATCH 042/506] ARM: dts: sunxi: bananapi-m2-plus: Add Bluetooth device node The AP6212 is based on the Broadcom BCM43430 or BCM43438. The WiFi side identifies as BCM43430, while the Bluetooth side identifies as BCM43438. The Bluetooth side is connected to UART1 in a 4 wire configuration. Same as the WiFi side, due to being the same chip and package, the board's fixed 3.3V power regulator provides overall power via VBAT and I/O power via VDDIO. The RTC clock output from the SoC provides the LPO low power clock at 32.768 kHz. This patch enables Bluetooth on this board, and also adds the missing LPO clock on the WiFi side. There is also a PCM connection for Bluetooth, but this is not covered here. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi index b3283aeb5b7d..3bed375b9c03 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi @@ -103,6 +103,8 @@ compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; }; }; @@ -215,7 +217,19 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; + vddio-supply = <®_vcc3v3>; + device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + }; }; &usb_otg { From 5885ca007e9a975d1749c388a7c84bffeef73cd6 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 15 Dec 2018 08:31:51 +0530 Subject: [PATCH 043/506] dt-bindings: vendor-prefixes: Add Novtech Vendor Prefix Add vendor prefix for NovTech, Inc. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..17c29009184a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -273,6 +273,7 @@ nintendo Nintendo nlt NLT Technologies, Ltd. nokia Nokia nordic Nordic Semiconductor +novtech NovTech, Inc. nutsboard NutsBoard nuvoton Nuvoton Technology Corporation nvd New Vision Display From d031ee5374b6eb66af7ef131d6bd7b1a9924c7af Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 15 Dec 2018 08:31:52 +0530 Subject: [PATCH 044/506] ARM: dts: Add support for 96Boards Chameleon96 board Add devicetree support for 96Boards Chameleon96 board from Novtech, Inc. based on Altera CycloneV SoC FPGA. This board is one of the Consumer Edition boards of the 96Boards family and has the following key features: * SoC - Intel Cyclone V SoC FPGA * GPU - Graphics based on Intel Video Suite for FPGA * RAM - 512MB DDR3L * USB - 2x USB2.0 Host, 1x USB2.0 OTG * Wireless - Wifi, BT More information about this board can be found in 96Boards product page: https://www.96boards.org/product/chameleon96/ Signed-off-by: Manivannan Sadhasivam Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/socfpga_cyclone5_chameleon96.dts | 130 ++++++++++++++++++ 2 files changed, 131 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..e21d4bb42494 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -919,6 +919,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ + socfpga_cyclone5_chameleon96.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_de0_nano_soc.dtb \ diff --git a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts new file mode 100644 index 000000000000..f6561766d83f --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for the Chameleon96 + * + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +#include + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Novetech Chameleon96"; + compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x20000000>; /* 512MB */ + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds { + compatible = "gpio-leds"; + + user_led1 { + label = "green:user1"; + gpios = <&porta 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + user_led2 { + label = "green:user2"; + gpios = <&porta 22 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + }; + + user_led3 { + label = "green:user3"; + gpios = <&porta 25 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + user_led4 { + label = "green:user4"; + gpios = <&portb 3 GPIO_ACTIVE_LOW>; + panic-indicator; + linux,default-trigger = "none"; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + /* On Low speed expansion */ + label = "LS-I2C0"; + status = "okay"; +}; + +&i2c1 { + /* On Low speed expansion */ + label = "LS-I2C1"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + /* On High speed expansion */ + label = "HS-I2C2"; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&spi0 { + /* On High speed expansion */ + label = "HS-SPI1"; + status = "okay"; +}; + +&spi1 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; +}; + +&uart0 { + /* On Low speed expansion */ + label = "LS-UART1"; + status = "okay"; +}; + +&uart1 { + /* On Low speed expansion */ + label = "LS-UART0"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; From 9539c0c13663da89bac378b032cb38e643e49bf2 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 7 Nov 2018 23:18:42 +0530 Subject: [PATCH 045/506] arm64: dts: mediatek: mt6797: Add pinctrl support Add pinctrl support for Mediatek MT6797 SoC. Signed-off-by: Manivannan Sadhasivam Acked-by: Linus Walleij Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6797.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 4beaa71107d7..231230d32d09 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { compatible = "mediatek,mt6797"; @@ -129,6 +130,19 @@ #clock-cells = <1>; }; + pio: pinctrl@10005000 { + compatible = "mediatek,mt6797-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x10002000 0 0x400>, + <0 0x10002400 0 0x400>, + <0 0x10002800 0 0x400>, + <0 0x10002C00 0 0x400>; + reg-names = "gpio", "iocfgl", "iocfgb", + "iocfgr", "iocfgt"; + gpio-controller; + #gpio-cells = <2>; + }; + scpsys: scpsys@10006000 { compatible = "mediatek,mt6797-scpsys"; #power-domain-cells = <1>; From 58bef10e47fe7126ee6e6e1548c95ccb3258e6ce Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 7 Nov 2018 23:18:43 +0530 Subject: [PATCH 046/506] arm64: dts: mediatek: x20: Add pinmux support for UART1 Add pinmux support for UART1 on MediatekX20 Development board based on Mediatek MT6797 SoC. Signed-off-by: Manivannan Sadhasivam Acked-by: Linus Walleij Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts | 2 ++ arch/arm64/boot/dts/mediatek/mt6797.dtsi | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts index 742938a1a548..13939d55b85b 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts +++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts @@ -30,4 +30,6 @@ &uart1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 231230d32d09..a64bb84bdec3 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -141,6 +141,13 @@ "iocfgr", "iocfgt"; gpio-controller; #gpio-cells = <2>; + + uart1_pins_a: uart1 { + pins1 { + pinmux = , + ; + }; + }; }; scpsys: scpsys@10006000 { From e8c165fec90ba6ef63bc8bdcea3f8e481c00743c Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 16 Nov 2018 19:30:40 +0100 Subject: [PATCH 047/506] arm64: dts: Add uart for mt6797 EVB This patch adds the pinctrl configuration for the mt6797 EVB. Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6797-evb.dts | 2 ++ arch/arm64/boot/dts/mediatek/mt6797.dtsi | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts index c79109c65409..237e869a5fa1 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts @@ -33,4 +33,6 @@ &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index a64bb84bdec3..2b2a69c7567f 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -142,6 +142,13 @@ gpio-controller; #gpio-cells = <2>; + uart0_pins_a: uart0 { + pins0 { + pinmux = , + ; + }; + }; + uart1_pins_a: uart1 { pins1 { pinmux = , From 398ed2922527358d20fea1459005442370637e24 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:34:29 +0530 Subject: [PATCH 048/506] ARM64: dts: mediatek: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 9 ++++++--- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 ++++-- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 8fc4aa77f012..22435d21f4a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -170,17 +170,20 @@ cooling-maps { map0 { trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu_active>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map2 { trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 412ffd4d426b..c3c360161c5d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -276,12 +276,14 @@ cooling-maps { map@0 { trip = <&target>; - cooling-device = <&cpu0 0 0>; + cooling-device = <&cpu0 0 0>, + <&cpu1 0 0>; contribution = <3072>; }; map@1 { trip = <&target>; - cooling-device = <&cpu2 0 0>; + cooling-device = <&cpu2 0 0>, + <&cpu3 0 0>; contribution = <1024>; }; }; From 1724f4cc5133f0d841a1cf9c2fec89a20289a844 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Mon, 3 Dec 2018 19:35:55 +0800 Subject: [PATCH 049/506] arm64: dts: Add USB3 related nodes for MT2712 This patch adds USB3 related nodes for mt2712m1 platform. Signed-off-by: Chunfeng Yun Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 98 +++++++++++++++ arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 126 ++++++++++++++++++++ 2 files changed, 224 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index 4ce9d6ca0bf7..2b91daf5c1a6 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -6,6 +6,7 @@ */ /dts-v1/; +#include #include "mt2712e.dtsi" / { @@ -39,6 +40,53 @@ regulator-max-microvolt = <1000000>; }; + extcon_usb: extcon_iddig { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pio 12 GPIO_ACTIVE_HIGH>; + }; + + extcon_usb1: extcon_iddig1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>; + }; + + usb_p0_vbus: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "p0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p1_vbus: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "p1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p2_vbus: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "p2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p3_vbus: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "p3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + }; &auxadc { @@ -57,7 +105,57 @@ proc-supply = <&cpus_fixed_vproc1>; }; +&pio { + usb0_id_pins_float: usb0_iddig { + pins_iddig { + pinmux = ; + bias-pull-up; + }; + }; + + usb1_id_pins_float: usb1_iddig { + pins_iddig { + pinmux = ; + bias-pull-up; + }; + }; +}; + +&ssusb { + vbus-supply = <&usb_p0_vbus>; + extcon = <&extcon_usb>; + dr_mode = "otg"; + wakeup-source; + mediatek,u3p-dis-msk = <0x1>; + //enable-manual-drd; + //maximum-speed = "full-speed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_pins_float>; + status = "okay"; +}; + +&ssusb1 { + vbus-supply = <&usb_p1_vbus>; + extcon = <&extcon_usb1>; + dr_mode = "otg"; + //mediatek,u3p-dis-msk = <0x1>; + enable-manual-drd; + wakeup-source; + //maximum-speed = "full-speed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_id_pins_float>; + status = "okay"; +}; + &uart0 { status = "okay"; }; +&usb_host0 { + vbus-supply = <&usb_p2_vbus>; + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index ee627a7c7b45..6c228a24ef54 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "mt2712-pinfunc.h" @@ -405,6 +406,131 @@ status = "disabled"; }; + ssusb: usb@11271000 { + compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; + reg = <0 0x11271000 0 0x3000>, + <0 0x11280700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u2port1 PHY_TYPE_USB2>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; + clocks = <&topckgen CLK_TOP_USB30_SEL>; + clock-names = "sys_ck"; + mediatek,syscon-wakeup = <&pericfg 0x510 2>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host0: xhci@11270000 { + compatible = "mediatek,mt2712-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11270000 0 0x1000>; + reg-names = "mac"; + interrupts = ; + power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; + clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; + clock-names = "sys_ck", "ref_ck"; + status = "disabled"; + }; + }; + + u3phy0: usb-phy@11290000 { + compatible = "mediatek,mt2712-u3phy"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + u2port0: usb-phy@11290000 { + reg = <0 0x11290000 0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u2port1: usb-phy@11298000 { + reg = <0 0x11298000 0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@11298700 { + reg = <0 0x11298700 0 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + ssusb1: usb@112c1000 { + compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; + reg = <0 0x112c1000 0 0x3000>, + <0 0x112d0700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port2 PHY_TYPE_USB2>, + <&u2port3 PHY_TYPE_USB2>, + <&u3port1 PHY_TYPE_USB3>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; + clocks = <&topckgen CLK_TOP_USB30_SEL>; + clock-names = "sys_ck"; + mediatek,syscon-wakeup = <&pericfg 0x514 2>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host1: xhci@112c0000 { + compatible = "mediatek,mt2712-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112c0000 0 0x1000>; + reg-names = "mac"; + interrupts = ; + power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; + clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; + clock-names = "sys_ck", "ref_ck"; + status = "disabled"; + }; + }; + + u3phy1: usb-phy@112e0000 { + compatible = "mediatek,mt2712-u3phy"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + u2port2: usb-phy@112e0000 { + reg = <0 0x112e0000 0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u2port3: usb-phy@112e8000 { + reg = <0 0x112e8000 0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@112e8700 { + reg = <0 0x112e8700 0 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + mfgcfg: syscon@13000000 { compatible = "mediatek,mt2712-mfgcfg", "syscon"; reg = <0 0x13000000 0 0x1000>; From e82aa7991c193d5d90d9c74d41372f4fcb0d24f9 Mon Sep 17 00:00:00 2001 From: YT Shen Date: Mon, 3 Dec 2018 19:35:56 +0800 Subject: [PATCH 050/506] arm64: dts: add iommu/smi nodes for MT2712 Signed-off-by: YT Shen Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 128 ++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 6c228a24ef54..d429770e32f4 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include "mt2712-pinfunc.h" @@ -313,12 +314,33 @@ status = "disabled"; }; + iommu0: iommu@10205000 { + compatible = "mediatek,mt2712-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,larbs = <&larb0 &larb1 &larb2 + &larb3 &larb6>; + #iommu-cells = <1>; + }; + apmixedsys: syscon@10209000 { compatible = "mediatek,mt2712-apmixedsys", "syscon"; reg = <0 0x10209000 0 0x1000>; #clock-cells = <1>; }; + iommu1: iommu@1020a000 { + compatible = "mediatek,mt2712-m4u"; + reg = <0 0x1020a000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,larbs = <&larb4 &larb5 &larb7>; + #iommu-cells = <1>; + }; + mcucfg: syscon@10220000 { compatible = "mediatek,mt2712-mcucfg", "syscon"; reg = <0 0x10220000 0 0x1000>; @@ -543,12 +565,85 @@ #clock-cells = <1>; }; + larb0: larb@14021000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x14021000 0 0x1000>; + mediatek,smi = <&smi_common0>; + mediatek,larb-id = <0>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + }; + + smi_common0: smi@14022000 { + compatible = "mediatek,mt2712-smi-common"; + reg = <0 0x14022000 0 0x1000>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + }; + + larb4: larb@14027000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x14027000 0 0x1000>; + mediatek,smi = <&smi_common1>; + mediatek,larb-id = <4>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_LARB4>, + <&mmsys CLK_MM_SMI_LARB4>; + clock-names = "apb", "smi"; + }; + + larb5: larb@14030000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x14030000 0 0x1000>; + mediatek,smi = <&smi_common1>; + mediatek,larb-id = <5>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_LARB5>, + <&mmsys CLK_MM_SMI_LARB5>; + clock-names = "apb", "smi"; + }; + + smi_common1: smi@14031000 { + compatible = "mediatek,mt2712-smi-common"; + reg = <0 0x14031000 0 0x1000>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_COMMON1>, + <&mmsys CLK_MM_SMI_COMMON1>; + clock-names = "apb", "smi"; + }; + + larb7: larb@14032000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x14032000 0 0x1000>; + mediatek,smi = <&smi_common1>; + mediatek,larb-id = <7>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_LARB7>, + <&mmsys CLK_MM_SMI_LARB7>; + clock-names = "apb", "smi"; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt2712-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; }; + larb2: larb@15001000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common0>; + mediatek,larb-id = <2>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; + clocks = <&imgsys CLK_IMG_SMI_LARB2>, + <&imgsys CLK_IMG_SMI_LARB2>; + clock-names = "apb", "smi"; + }; + bdpsys: syscon@15010000 { compatible = "mediatek,mt2712-bdpsys", "syscon"; reg = <0 0x15010000 0 0x1000>; @@ -561,12 +656,45 @@ #clock-cells = <1>; }; + larb1: larb@16010000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common0>; + mediatek,larb-id = <1>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>; + clocks = <&vdecsys CLK_VDEC_CKEN>, + <&vdecsys CLK_VDEC_LARB1_CKEN>; + clock-names = "apb", "smi"; + }; + vencsys: syscon@18000000 { compatible = "mediatek,mt2712-vencsys", "syscon"; reg = <0 0x18000000 0 0x1000>; #clock-cells = <1>; }; + larb3: larb@18001000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x18001000 0 0x1000>; + mediatek,smi = <&smi_common0>; + mediatek,larb-id = <3>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, + <&vencsys CLK_VENC_VENC>; + clock-names = "apb", "smi"; + }; + + larb6: larb@18002000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x18002000 0 0x1000>; + mediatek,smi = <&smi_common0>; + mediatek,larb-id = <6>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, + <&vencsys CLK_VENC_VENC>; + clock-names = "apb", "smi"; + }; + jpgdecsys: syscon@19000000 { compatible = "mediatek,mt2712-jpgdecsys", "syscon"; reg = <0 0x19000000 0 0x1000>; From dd00ecfad9cacde6830113f6f4b4b913820ac626 Mon Sep 17 00:00:00 2001 From: YT Shen Date: Mon, 3 Dec 2018 19:35:57 +0800 Subject: [PATCH 051/506] arm64: dts: add i2c nodes for MT2712 Signed-off-by: YT Shen Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 90 +++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index d429770e32f4..7bac8b67ebdf 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -418,6 +418,96 @@ status = "disabled"; }; + i2c0: i2c@11007000 { + compatible = "mediatek,mt2712-i2c"; + reg = <0 0x11007000 0 0x90>, + <0 0x11000180 0 0x80>; + interrupts = ; + clock-div = <4>; + clocks = <&pericfg CLK_PERI_I2C0>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", + "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt2712-i2c"; + reg = <0 0x11008000 0 0x90>, + <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <4>; + clocks = <&pericfg CLK_PERI_I2C1>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", + "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt2712-i2c"; + reg = <0 0x11009000 0 0x90>, + <0 0x11000280 0 0x80>; + interrupts = ; + clock-div = <4>; + clocks = <&pericfg CLK_PERI_I2C2>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", + "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@11010000 { + compatible = "mediatek,mt2712-i2c"; + reg = <0 0x11010000 0 0x90>, + <0 0x11000300 0 0x80>; + interrupts = ; + clock-div = <4>; + clocks = <&pericfg CLK_PERI_I2C3>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", + "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11011000 { + compatible = "mediatek,mt2712-i2c"; + reg = <0 0x11011000 0 0x90>, + <0 0x11000380 0 0x80>; + interrupts = ; + clock-div = <4>; + clocks = <&pericfg CLK_PERI_I2C4>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", + "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@11013000 { + compatible = "mediatek,mt2712-i2c"; + reg = <0 0x11013000 0 0x90>, + <0 0x11000100 0 0x80>; + interrupts = ; + clock-div = <4>; + clocks = <&pericfg CLK_PERI_I2C5>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", + "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart4: serial@11019000 { compatible = "mediatek,mt2712-uart", "mediatek,mt6577-uart"; From 9d66740cecbdfb7dca65af4ba6ae5f70df8d9c07 Mon Sep 17 00:00:00 2001 From: YT Shen Date: Mon, 3 Dec 2018 19:35:58 +0800 Subject: [PATCH 052/506] arm64: dts: add spi nodes for MT2712 Signed-off-by: YT Shen Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 65 +++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 7bac8b67ebdf..4843376fd827 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -463,6 +463,19 @@ status = "disabled"; }; + spi0: spi@1100a000 { + compatible = "mediatek,mt2712-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&pericfg CLK_PERI_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + i2c3: i2c@11010000 { compatible = "mediatek,mt2712-i2c"; reg = <0 0x11010000 0 0x90>, @@ -508,6 +521,58 @@ status = "disabled"; }; + spi2: spi@11015000 { + compatible = "mediatek,mt2712-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11015000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&pericfg CLK_PERI_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11016000 { + compatible = "mediatek,mt2712-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11016000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&pericfg CLK_PERI_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@10012000 { + compatible = "mediatek,mt2712-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10012000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_AO_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11018000 { + compatible = "mediatek,mt2712-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11018000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&pericfg CLK_PERI_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + uart4: serial@11019000 { compatible = "mediatek,mt2712-uart", "mediatek,mt6577-uart"; From d85b9774c8bda4589db7e82d9e347522b82ef57d Mon Sep 17 00:00:00 2001 From: YT Shen Date: Mon, 3 Dec 2018 19:35:59 +0800 Subject: [PATCH 053/506] arm64: dts: add pwm nodes for MT2712 Signed-off-by: YT Shen Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28 +++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 4843376fd827..e9856fef3e72 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -418,6 +418,34 @@ status = "disabled"; }; + pwm: pwm@11006000 { + compatible = "mediatek,mt2712-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM>, + <&pericfg CLK_PERI_PWM0>, + <&pericfg CLK_PERI_PWM1>, + <&pericfg CLK_PERI_PWM2>, + <&pericfg CLK_PERI_PWM3>, + <&pericfg CLK_PERI_PWM4>, + <&pericfg CLK_PERI_PWM5>, + <&pericfg CLK_PERI_PWM6>, + <&pericfg CLK_PERI_PWM7>; + clock-names = "top", + "main", + "pwm1", + "pwm2", + "pwm3", + "pwm4", + "pwm5", + "pwm6", + "pwm7", + "pwm8"; + status = "disabled"; + }; + i2c0: i2c@11007000 { compatible = "mediatek,mt2712-i2c"; reg = <0 0x11007000 0 0x90>, From db0b58d88d7d1af5ce3e454e397eb461565675c5 Mon Sep 17 00:00:00 2001 From: YT Shen Date: Mon, 3 Dec 2018 19:36:00 +0800 Subject: [PATCH 054/506] arm64: dts: add mmc nodes for MT2712 Signed-off-by: YT Shen Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 34 +++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index e9856fef3e72..4f0aa65f1625 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -611,6 +611,40 @@ status = "disabled"; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt2712-mmc"; + reg = <0 0x11230000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>, + <&pericfg CLK_PERI_MSDC30_0_QTR_EN>, + <&pericfg CLK_PERI_MSDC50_0_EN>; + clock-names = "source", "hclk", "bus_clk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt2712-mmc"; + reg = <0 0x11240000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_1>, + <&topckgen CLK_TOP_AXI_SEL>, + <&pericfg CLK_PERI_MSDC30_1_EN>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt2712-mmc"; + reg = <0 0x11250000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_2>, + <&topckgen CLK_TOP_AXI_SEL>, + <&pericfg CLK_PERI_MSDC30_2_EN>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + ssusb: usb@11271000 { compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; reg = <0 0x11271000 0 0x3000>, From a9386c5366a7657fbddec91e0ed04c54b24e145d Mon Sep 17 00:00:00 2001 From: YT Shen Date: Mon, 3 Dec 2018 19:36:01 +0800 Subject: [PATCH 055/506] arm64: dts: add nand nodes for MT2712 Signed-off-by: YT Shen Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 4f0aa65f1625..e8afb5431fcb 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -504,6 +504,27 @@ status = "disabled"; }; + nandc: nfi@1100e000 { + compatible = "mediatek,mt2712-nfc"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>; + clock-names = "nfi_clk", "pad_clk"; + ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + bch: ecc@1100f000 { + compatible = "mediatek,mt2712-ecc"; + reg = <0 0x1100f000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>; + clock-names = "nfiecc_clk"; + status = "disabled"; + }; + i2c3: i2c@11010000 { compatible = "mediatek,mt2712-i2c"; reg = <0 0x11010000 0 0x90>, From a807d5d7c4f385eb5fb6be528dfaf77f560ff0c8 Mon Sep 17 00:00:00 2001 From: Honghui Zhang Date: Mon, 3 Dec 2018 19:36:02 +0800 Subject: [PATCH 056/506] arm64: dts: add pcie nodes for MT2712 This patch add device node for mt2712 pcie. Signed-off-by: Honghui Zhang Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 63 +++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index e8afb5431fcb..976d92a94738 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -791,6 +791,69 @@ }; }; + pcie: pcie@11700000 { + compatible = "mediatek,mt2712-pcie"; + device_type = "pci"; + reg = <0 0x11700000 0 0x1000>, + <0 0x112ff000 0 0x1000>; + reg-names = "port0", "port1"; + #address-cells = <3>; + #size-cells = <2>; + interrupts = , + ; + clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, + <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, + <&pericfg CLK_PERI_PCIE0>, + <&pericfg CLK_PERI_PCIE1>; + clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; + phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; + + pcie0: pcie@0,0 { + device_type = "pci"; + status = "disabled"; + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + num-lanes = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@1,0 { + device_type = "pci"; + status = "disabled"; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + num-lanes = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + mfgcfg: syscon@13000000 { compatible = "mediatek,mt2712-mfgcfg", "syscon"; reg = <0 0x13000000 0 0x1000>; From 34948b77bb09b8ad3b3365c3b2b87278ce4473de Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:31:12 +0530 Subject: [PATCH 057/506] ARM: dts: mt7623: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 98f115966391..a79f0b6c3429 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -187,17 +187,26 @@ cooling-maps { map0 { trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu_active>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map2 { trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; From 13c033bc630a2df51931d16ea5fb81710ad2e0b2 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 7 Dec 2018 10:03:39 +0000 Subject: [PATCH 058/506] ARM: dts: imx7ulp: add HSRUN mode clocks i.MX7ULP can switch CPU between RUN mode and HSRUN mode by programming SMC1 register, different clock sources will be used for CPU in different modes, so SMC1 can be abstracted as a clock controller for CPU clock switch, this patch adds support for it. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7ulp.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index 931b2754b099..b86daf73bb89 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -199,9 +199,13 @@ assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; }; - smc1: smc1@40410000 { + smc1: clock-controller@40410000 { compatible = "fsl,imx7ulp-smc1"; reg = <0x40410000 0x1000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>, + <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>; + clock-names = "divcore", "hsrun_divcore"; }; pcc3: clock-controller@40b30000 { From 02f95c355122d5a93d2663df867aa8e2bde5480a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 11 Dec 2018 10:03:47 -0200 Subject: [PATCH 059/506] ARM: dts: vf610-zii-cfu1: Run I2C0 at 400 kHz All the I2C devices connected to the I2C0 bus are capable of running at 400kHz, so run it at a higher frequency. Signed-off-by: Fabio Estevam Tested-by: Chris Healy Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 7cdcc5fe8282..445c7dc306b2 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -207,7 +207,7 @@ }; &i2c0 { - clock-frequency = <100000>; + clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; From cd8281acdf91379dfa001e2e523ca192360c1d02 Mon Sep 17 00:00:00 2001 From: Patrick Havelange Date: Tue, 11 Dec 2018 16:48:34 +0100 Subject: [PATCH 060/506] ARM: dts: ls1021a: Add memory controller The LS1021A has a memory controller that supports EDAC. This commit adds an entry for it. Signed-off-by: Patrick Havelange Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index ed0941292172..6df6a291f4d0 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -125,6 +125,13 @@ interrupt-parent = <&gic>; ranges; + ddr: memory-controller@1080000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1080000 0x0 0x1000>; + interrupts = ; + big-endian; + }; + gic: interrupt-controller@1400000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; From 65441e1ffc21b950d7bcb697e7cc2424fc14fa8d Mon Sep 17 00:00:00 2001 From: Soeren Moch Date: Tue, 11 Dec 2018 17:40:10 +0100 Subject: [PATCH 061/506] ARM: dts: imx6q-tbs2910: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Soeren Moch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-tbs2910.dts | 49 ++--------------------------- 1 file changed, 3 insertions(+), 46 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts index 279b15e9ae2e..2ce8399a10ba 100644 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -1,49 +1,6 @@ -/* - * Copyright 2014 Soeren Moch - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2014 Soeren Moch /dts-v1/; From 7dd2e8f8a5dc6266a4df4ed6f269ab7bacae596c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 19 Dec 2018 13:47:27 +0200 Subject: [PATCH 062/506] ARM: dts: da850-lcdk: Enable the analog mic input The LCDK board have additional analog mic jack. Signed-off-by: Peter Ujfalusi Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850-lcdk.dts | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts index 0177e3ed20fe..320ae9d13f6f 100644 --- a/arch/arm/boot/dts/da850-lcdk.dts +++ b/arch/arm/boot/dts/da850-lcdk.dts @@ -44,12 +44,16 @@ simple-audio-card,name = "DA850/OMAP-L138 LCDK"; simple-audio-card,widgets = "Line", "Line In", - "Line", "Line Out"; + "Line", "Line Out", + "Microphone", "Mic Jack"; simple-audio-card,routing = "LINE1L", "Line In", "LINE1R", "Line In", "Line Out", "LLOUT", - "Line Out", "RLOUT"; + "Line Out", "RLOUT", + "MIC3L", "Mic Jack", + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias"; simple-audio-card,format = "dsp_b"; simple-audio-card,bitclock-master = <&link0_codec>; simple-audio-card,frame-master = <&link0_codec>; @@ -220,6 +224,8 @@ #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x18>; + adc-settle-ms = <40>; + ai3x-micbias-vg = <1>; /* 2.0V */ status = "okay"; }; }; From b724cad74c7a122a8496518a157c548f97f1821b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 29 Jan 2018 14:28:59 +0100 Subject: [PATCH 063/506] ARM: dts: Augment panel setting for Integrator/CP This adds the actual VGA DAC bridge that is used in the Versatile AB, and sets the mode to 640x480 VGA and routes the CLCD pads appropriately. Cc: Liviu Dudau Cc: Mali DP Maintainers Signed-off-by: Linus Walleij --- arch/arm/boot/dts/integratorcp.dts | 89 +++++++++++++++++++----------- 1 file changed, 57 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index a185ab8759fa..01fa229e1bd0 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts @@ -192,6 +192,43 @@ interrupts = <27>; }; + bridge { + compatible = "ti,ths8134a", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads_vga_dac>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + fpga { /* * These PrimeCells are at the same location and using @@ -254,39 +291,27 @@ interrupts = <22>; clocks = <&auxosc>, <&pclk>; clock-names = "clcdclk", "apb_pclk"; + /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ + max-memory-bandwidth = <40000000>; - port { - /* - * The VGA connected is implemented with a - * THS8134A triple DAC that can be run in 24bit - * or 16bit RGB mode. - */ - clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; - arm,pl11x,tft-r0g0b0-pads = <1 7 13>; - }; - }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - /* Standard 640x480 VGA timings */ - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <48>; - hfront-porch = <16>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <33>; - vfront-porch = <10>; - vsync-len = <2>; + /* + * This port is routed through a PLD (Programmable + * Logic Device) that routes the output from the CLCD + * (after transformations) to the VGA DAC and also an + * external panel connector. The PLD is essential for + * supporting RGB565/BGR565. + * + * The signals from the port thus reaches two endpoints. + * The PLD is managed through a few special bits in the + * FPGA "sysreg". + * + * This arrangement can be clearly seen in + * ARM DUI 0225D, page 3-41, figure 3-19. + */ + port@0 { + clcd_pads_vga_dac: endpoint { + remote-endpoint = <&vga_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; }; }; }; From cf91ce9696a019de74135b7a2ee21466c680ff4e Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Sun, 9 Dec 2018 22:50:56 +0100 Subject: [PATCH 064/506] ARM: dts: vf610-bk4: Provide support for reading ID code from MVB device The procedure to read this ID value is as follows: rmmod spi_fsl_dspi insmod spi-gpio.ko echo 504 > /sys/class/gpio/export cat /sys/class/gpio/gpio504/value ... echo 511 > /sys/class/gpio/export cat /sys/class/gpio/gpio511/value rmmod spi-gpio.ko insmod spi_fsl_dspi Signed-off-by: Lukasz Majewski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-bk4.dts | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/vf610-bk4.dts b/arch/arm/boot/dts/vf610-bk4.dts index 689c8930dce3..fe496f220871 100644 --- a/arch/arm/boot/dts/vf610-bk4.dts +++ b/arch/arm/boot/dts/vf610-bk4.dts @@ -60,6 +60,29 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + spi-gpio { + compatible = "spi-gpio"; + pinctrl-0 = <&pinctrl_gpio_spi>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + /* PTD12 ->RPIO[91] */ + sck-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + /* PTD10 ->RPIO[89] */ + miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + num-chipselects = <0>; + + gpio@0 { + compatible = "pisosr-gpio"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + /* PTB18 -> RGPIO[40] */ + load-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + spi-max-frequency = <100000>; + }; + }; }; &adc0 { @@ -431,6 +454,14 @@ >; }; + pinctrl_gpio_spi: pinctrl-gpio-spi { + fsl,pins = < + VF610_PAD_PTB18__GPIO_40 0x1183 + VF610_PAD_PTD10__GPIO_89 0x1183 + VF610_PAD_PTD12__GPIO_91 0x1183 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < VF610_PAD_PTA22__I2C2_SCL 0x34df From e7a095908227fb3ccc86d001d9e13c9ae2bef8e6 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Tue, 8 Jan 2019 21:57:23 +0000 Subject: [PATCH 065/506] arm64: dts: rockchip: Add devicetree for NanoPC-T4 This adds a device tree for the NanoPC-T4 SBC, which is based on the Rockchip RK3399 SoC and marketed by FriendlyELEC. Known working: - Serial - Ethernet - HDMI - USB 2.0 All of the interesting stuff is in a .dtsi because there are at least two other boards that share most of it: NanoPi M4 and NanoPi NEO4. Signed-off-by: Tomeu Vizoso Reviewed-by: Rob Herring [rm: various further cleanup] Signed-off-by: Robin Murphy Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/arm/rockchip.yaml | 5 + arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3399-nanopc-t4.dts | 17 + .../boot/dts/rockchip/rk3399-nanopi4.dtsi | 725 ++++++++++++++++++ 4 files changed, 748 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index b12958bda09c..bcc60c492a12 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -87,6 +87,11 @@ properties: - const: firefly,roc-rk3399-pc - const: rockchip,rk3399 + - description: FriendlyElec NanoPC-T4 + items: + - const: friendlyarm,nanopc-t4 + - const: rockchip,rk3399 + - description: GeekBuying GeekBox items: - const: geekbuying,geekbox diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index de0c406c20cc..1c7406111dfd 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts new file mode 100644 index 000000000000..af0bb2544709 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPC-T4 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPC-T4"; + compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi new file mode 100644 index 000000000000..3e8f1c10ba4f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -0,0 +1,725 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RK3399-based FriendlyElec boards device tree source + * + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd_5v"; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_core"; + vin-supply = <&vdd_5v>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + vin-supply = <&vcc5v0_core>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_usb1"; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2: vcc5v0-usb2 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_usb2"; + vin-supply = <&vcc5v0_sys>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_s3"; + vin-supply = <&vcc_1v8>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vbus_typec: vbus-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vbus_typec"; + vin-supply = <&vdd_5v>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <18000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&power_key>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_gpio>; + + status { + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clock-parents = <&clkin_gmac>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-supply = <&vcc3v3_s3>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c7>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu_b_sleep>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu_b"; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpu_sleep>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_gpu"; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + clock-output-names = "xin32k", "rk808-clkout2"; + #clock-cells = <1>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_center"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_cpu_l"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_cam: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_cam"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_touch"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmupll"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <3000000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sdio"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <200000>; + i2c-scl-rising-time-ns = <150>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vbus_typec>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc_1v8>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pcie_phy { + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; + assigned-clock-rates = <100000000>; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; + num-lanes = <4>; + status = "okay"; +}; + +&pinctrl { + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + cpu_b_sleep: cpu-b-sleep { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + gpu_sleep: gpu-sleep { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + power_key: power-key { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_reg_on_h: wifi-reg_on-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_cd &sdmmc_clk &sdmmc_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_usb2>; + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; From a1a38e1f4d1d79dfbedb66148d611827c23c7c44 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 3 Dec 2018 15:32:07 -0600 Subject: [PATCH 066/506] dt-bindings: arm: Convert FSL board/soc bindings to json-schema Convert Freescale SoC bindings to DT schema format using json-schema. Cc: Shawn Guo Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/armadeus.txt | 6 - Documentation/devicetree/bindings/arm/bhf.txt | 6 - .../bindings/arm/compulab-boards.txt | 25 -- Documentation/devicetree/bindings/arm/fsl.txt | 237 ------------------ .../devicetree/bindings/arm/fsl.yaml | 214 ++++++++++++++++ .../devicetree/bindings/arm/i2se.txt | 22 -- .../devicetree/bindings/arm/olimex.txt | 10 - .../devicetree/bindings/arm/technologic.txt | 23 -- 8 files changed, 214 insertions(+), 329 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/armadeus.txt delete mode 100644 Documentation/devicetree/bindings/arm/bhf.txt delete mode 100644 Documentation/devicetree/bindings/arm/compulab-boards.txt delete mode 100644 Documentation/devicetree/bindings/arm/fsl.txt create mode 100644 Documentation/devicetree/bindings/arm/fsl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/i2se.txt delete mode 100644 Documentation/devicetree/bindings/arm/olimex.txt delete mode 100644 Documentation/devicetree/bindings/arm/technologic.txt diff --git a/Documentation/devicetree/bindings/arm/armadeus.txt b/Documentation/devicetree/bindings/arm/armadeus.txt deleted file mode 100644 index 9821283ff516..000000000000 --- a/Documentation/devicetree/bindings/arm/armadeus.txt +++ /dev/null @@ -1,6 +0,0 @@ -Armadeus i.MX Platforms Device Tree Bindings ------------------------------------------------ - -APF51: i.MX51 based module. -Required root node properties: - - compatible = "armadeus,imx51-apf51", "fsl,imx51"; diff --git a/Documentation/devicetree/bindings/arm/bhf.txt b/Documentation/devicetree/bindings/arm/bhf.txt deleted file mode 100644 index 886b503caf9c..000000000000 --- a/Documentation/devicetree/bindings/arm/bhf.txt +++ /dev/null @@ -1,6 +0,0 @@ -Beckhoff Automation Platforms Device Tree Bindings --------------------------------------------------- - -CX9020 Embedded PC -Required root node properties: - - compatible = "bhf,cx9020", "fsl,imx53"; diff --git a/Documentation/devicetree/bindings/arm/compulab-boards.txt b/Documentation/devicetree/bindings/arm/compulab-boards.txt deleted file mode 100644 index 42a10285af9c..000000000000 --- a/Documentation/devicetree/bindings/arm/compulab-boards.txt +++ /dev/null @@ -1,25 +0,0 @@ -CompuLab SB-SOM is a multi-module baseboard capable of carrying: - - CM-T43 - - CM-T54 - - CM-QS600 - - CL-SOM-AM57x - - CL-SOM-iMX7 -modules with minor modifications to the SB-SOM assembly. - -Required root node properties: - - compatible = should be "compulab,sb-som" - -Compulab CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on -Freescale i.MX7 ARM Cortex-A7 System-on-Chip. - -Required root node properties: - - compatible = "compulab,cl-som-imx7", "fsl,imx7d"; - -Compulab SBC-iMX7 is a single board computer based on the -Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with -the CL-SOM-iMX7 System-on-Module providing most of the functions, -and SB-SOM-iMX7 carrier board providing additional peripheral -functions and connectors. - -Required root node properties: - - compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d"; diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt deleted file mode 100644 index 7fbc42484001..000000000000 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ /dev/null @@ -1,237 +0,0 @@ -Freescale i.MX Platforms Device Tree Bindings ------------------------------------------------ - -i.MX23 Evaluation Kit -Required root node properties: - - compatible = "fsl,imx23-evk", "fsl,imx23"; - -i.MX25 Product Development Kit -Required root node properties: - - compatible = "fsl,imx25-pdk", "fsl,imx25"; - -i.MX27 Product Development Kit -Required root node properties: - - compatible = "fsl,imx27-pdk", "fsl,imx27"; - -i.MX28 Evaluation Kit -Required root node properties: - - compatible = "fsl,imx28-evk", "fsl,imx28"; - -i.MX51 Babbage Board -Required root node properties: - - compatible = "fsl,imx51-babbage", "fsl,imx51"; - -i.MX53 Automotive Reference Design Board -Required root node properties: - - compatible = "fsl,imx53-ard", "fsl,imx53"; - -i.MX53 Evaluation Kit -Required root node properties: - - compatible = "fsl,imx53-evk", "fsl,imx53"; - -i.MX53 Quick Start Board -Required root node properties: - - compatible = "fsl,imx53-qsb", "fsl,imx53"; - -i.MX53 Smart Mobile Reference Design Board -Required root node properties: - - compatible = "fsl,imx53-smd", "fsl,imx53"; - -i.MX6 Quad Armadillo2 Board -Required root node properties: - - compatible = "fsl,imx6q-arm2", "fsl,imx6q"; - -i.MX6 Quad SABRE Lite Board -Required root node properties: - - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; - -i.MX6 Quad SABRE Smart Device Board -Required root node properties: - - compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; - -i.MX6 Quad SABRE Automotive Board -Required root node properties: - - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; - -i.MX6SLL EVK board -Required root node properties: - - compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; - -i.MX6 Quad Plus SABRE Smart Device Board -Required root node properties: - - compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp"; - -i.MX6 Quad Plus SABRE Automotive Board -Required root node properties: - - compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; - -i.MX6 DualLite SABRE Smart Device Board -Required root node properties: - - compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; - -i.MX6 DualLite/Solo SABRE Automotive Board -Required root node properties: - - compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; - -i.MX6 SoloLite EVK Board -Required root node properties: - - compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; - -i.MX6 UltraLite 14x14 EVK Board -Required root node properties: - - compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; - -i.MX6 UltraLiteLite 14x14 EVK Board -Required root node properties: - - compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; - -i.MX6 ULZ 14x14 EVK Board -Required root node properties: - - compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz"; - -i.MX6 SoloX SDB Board -Required root node properties: - - compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; - -i.MX6 SoloX Sabre Auto Board -Required root node properties: - - compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; - -i.MX7 SabreSD Board -Required root node properties: - - compatible = "fsl,imx7d-sdb", "fsl,imx7d"; - -i.MX7ULP Evaluation Kit -Required root node properties: - - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; - -Generic i.MX boards -------------------- - -No iomux setup is done for these boards, so this must have been configured -by the bootloader for boards to work with the generic bindings. - -i.MX27 generic board -Required root node properties: - - compatible = "fsl,imx27"; - -i.MX51 generic board -Required root node properties: - - compatible = "fsl,imx51"; - -i.MX53 generic board -Required root node properties: - - compatible = "fsl,imx53"; - -i.MX6q generic board -Required root node properties: - - compatible = "fsl,imx6q"; - -i.MX7ULP generic board -Required root node properties: - - compatible = "fsl,imx7ulp"; - -Freescale Vybrid Platform Device Tree Bindings ----------------------------------------------- - -For the Vybrid SoC familiy all variants with DDR controller are supported, -which is the VF5xx and VF6xx series. Out of historical reasons, in most -places the kernel uses vf610 to refer to the whole familiy. -The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4 -core support. - -Required root node compatible property (one of them): - - compatible = "fsl,vf500"; - - compatible = "fsl,vf510"; - - compatible = "fsl,vf600"; - - compatible = "fsl,vf610"; - - compatible = "fsl,vf610m4"; - -Freescale LS1021A Platform Device Tree Bindings ------------------------------------------------- - -Required root node compatible properties: - - compatible = "fsl,ls1021a"; - -Freescale ARMv8 based Layerscape SoC family Device Tree Bindings ----------------------------------------------------------------- - -LS1012A SoC -Required root node properties: - - compatible = "fsl,ls1012a"; - -LS1012A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; - -LS1012A ARMv8 based FRDM Board -Required root node properties: - - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; - -LS1012A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; - -LS1043A SoC -Required root node properties: - - compatible = "fsl,ls1043a"; - -LS1043A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; - -LS1043A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1043a-qds", "fsl,ls1043a"; - -LS1046A SoC -Required root node properties: - - compatible = "fsl,ls1046a"; - -LS1046A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; - -LS1046A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; - -LS1088A SoC -Required root node properties: - - compatible = "fsl,ls1088a"; - -LS1088A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; - -LS1088A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; - -LS2080A SoC -Required root node properties: - - compatible = "fsl,ls2080a"; - -LS2080A ARMv8 based Simulator model -Required root node properties: - - compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; - -LS2080A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; - -LS2080A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; - -LS2088A SoC -Required root node properties: - - compatible = "fsl,ls2088a"; - -LS2088A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; - -LS2088A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml new file mode 100644 index 000000000000..a4d625d7ff4d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -0,0 +1,214 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/fsl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX Platforms Device Tree Bindings + +maintainers: + - Shawn Guo + - Li Yang + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: i.MX23 based Boards + items: + - enum: + - fsl,imx23-evk + - olimex,imx23-olinuxino + - const: fsl,imx23 + + - description: i.MX25 Product Development Kit + items: + - enum: + - fsl,imx25-pdk + - const: fsl,imx25 + + - description: i.MX27 Product Development Kit + items: + - enum: + - fsl,imx27-pdk + - const: fsl,imx27 + + - description: i.MX28 based Boards + items: + - enum: + - fsl,imx28-evk + - i2se,duckbill + - i2se,duckbill-2 + - technologic,imx28-ts4600 + - const: fsl,imx28 + - description: i.MX28 Duckbill 2 based Boards + items: + - enum: + - i2se,duckbill-2-485 + - i2se,duckbill-2-enocean + - i2se,duckbill-2-spi + - const: i2se,duckbill-2 + - const: fsl,imx28 + + - description: i.MX51 Babbage Board + items: + - enum: + - armadeus,imx51-apf51 + - fsl,imx51-babbage + - technologic,imx51-ts4800 + - const: fsl,imx51 + + - description: i.MX53 based Boards + items: + - enum: + - bhf,cx9020 + - fsl,imx53-ard + - fsl,imx53-evk + - fsl,imx53-qsb + - fsl,imx53-smd + - const: fsl,imx53 + + - description: i.MX6Q based Boards + items: + - enum: + - fsl,imx6q-arm2 + - fsl,imx6q-sabreauto + - fsl,imx6q-sabrelite + - fsl,imx6q-sabresd + - technologic,imx6q-ts4900 + - technologic,imx6q-ts7970 + - const: fsl,imx6q + + - description: i.MX6QP based Boards + items: + - enum: + - fsl,imx6qp-sabreauto # i.MX6 Quad Plus SABRE Automotive Board + - fsl,imx6qp-sabresd # i.MX6 Quad Plus SABRE Smart Device Board + - const: fsl,imx6qp + + - description: i.MX6DL based Boards + items: + - enum: + - fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board + - fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board + - technologic,imx6dl-ts4900 + - technologic,imx6dl-ts7970 + - const: fsl,imx6dl + + - description: i.MX6SL based Boards + items: + - enum: + - fsl,imx6sl-evk # i.MX6 SoloLite EVK Board + - const: fsl,imx6sl + + - description: i.MX6SLL based Boards + items: + - enum: + - fsl,imx6sll-evk + - const: fsl,imx6sll + + - description: i.MX6SX based Boards + items: + - enum: + - fsl,imx6sx-sabreauto # i.MX6 SoloX Sabre Auto Board + - fsl,imx6sx-sdb # i.MX6 SoloX SDB Board + - const: fsl,imx6sx + + - description: i.MX6UL based Boards + items: + - enum: + - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board + - const: fsl,imx6ul + + - description: i.MX6ULL based Boards + items: + - enum: + - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board + - const: fsl,imx6ull + + - description: i.MX6ULZ based Boards + items: + - enum: + - fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board + - const: fsl,imx6ull # This seems odd. Should be last? + - const: fsl,imx6ulz + + - description: i.MX7D based Boards + items: + - enum: + - fsl,imx7d-sdb # i.MX7 SabreSD Board + - const: fsl,imx7d + + - description: + Compulab SBC-iMX7 is a single board computer based on the + Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with + the CL-SOM-iMX7 System-on-Module providing most of the functions, + and SB-SOM-iMX7 carrier board providing additional peripheral + functions and connectors. + items: + - const: compulab,sbc-imx7 + - const: compulab,cl-som-imx7 + - const: fsl,imx7d + + - description: + Freescale Vybrid Platform Device Tree Bindings + + For the Vybrid SoC familiy all variants with DDR controller are supported, + which is the VF5xx and VF6xx series. Out of historical reasons, in most + places the kernel uses vf610 to refer to the whole familiy. + The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4 + core support. + items: + - enum: + - fsl,vf500 + - fsl,vf510 + - fsl,vf600 + - fsl,vf610 + - fsl,vf610m4 + + - description: LS1021A based Boards + items: + - enum: + - fsl,ls1012a-rdb + - fsl,ls1012a-frdm + - fsl,ls1012a-qds + - const: fsl,ls1021a + + - description: LS1043A based Boards + items: + - enum: + - fsl,ls1043a-rdb + - fsl,ls1043a-qds + - const: fsl,ls1043a + + - description: LS1046A based Boards + items: + - enum: + - fsl,ls1046a-qds + - fsl,ls1046a-rdb + - const: fsl,ls1046a + + - description: LS1088A based Boards + items: + - enum: + - fsl,ls1088a-qds + - fsl,ls1088a-rdb + - const: fsl,ls1088a + + - description: LS2080A based Boards + items: + - enum: + - fsl,ls2080a-simu + - fsl,ls2080a-qds + - fsl,ls2080a-rdb + - const: fsl,ls2080a + + - description: LS2088A based Boards + items: + - enum: + - fsl,ls2088a-qds + - fsl,ls2088a-rdb + - const: fsl,ls2088a + +... diff --git a/Documentation/devicetree/bindings/arm/i2se.txt b/Documentation/devicetree/bindings/arm/i2se.txt deleted file mode 100644 index dbd54a3aa07d..000000000000 --- a/Documentation/devicetree/bindings/arm/i2se.txt +++ /dev/null @@ -1,22 +0,0 @@ -I2SE Device Tree Bindings -------------------------- - -Duckbill Board -Required root node properties: - - compatible = "i2se,duckbill", "fsl,imx28"; - -Duckbill 2 Board -Required root node properties: - - compatible = "i2se,duckbill-2", "fsl,imx28"; - -Duckbill 2 485 Board -Required root node properties: - - compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28"; - -Duckbill 2 EnOcean Board -Required root node properties: - - compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28"; - -Duckbill 2 SPI Board -Required root node properties: - - compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28"; diff --git a/Documentation/devicetree/bindings/arm/olimex.txt b/Documentation/devicetree/bindings/arm/olimex.txt deleted file mode 100644 index d726aeca56be..000000000000 --- a/Documentation/devicetree/bindings/arm/olimex.txt +++ /dev/null @@ -1,10 +0,0 @@ -Olimex Device Tree Bindings ---------------------------- - -SAM9-L9260 Board -Required root node properties: - - compatible = "olimex,sam9-l9260", "atmel,at91sam9260"; - -i.MX23 Olinuxino Low Cost Board -Required root node properties: - - compatible = "olimex,imx23-olinuxino", "fsl,imx23"; diff --git a/Documentation/devicetree/bindings/arm/technologic.txt b/Documentation/devicetree/bindings/arm/technologic.txt deleted file mode 100644 index f1cedc00dcab..000000000000 --- a/Documentation/devicetree/bindings/arm/technologic.txt +++ /dev/null @@ -1,23 +0,0 @@ -Technologic Systems Platforms Device Tree Bindings --------------------------------------------------- - -TS-4600 is a System-on-Module based on the Freescale i.MX28 System-on-Chip. -It can be mounted on a carrier board providing additional peripheral connectors. -Required root node properties: - - compatible = "technologic,imx28-ts4600", "fsl,imx28" - -TS-4800 board -Required root node properties: - - compatible = "technologic,imx51-ts4800", "fsl,imx51"; - -TS-4900 is a System-on-Module based on the Freescale i.MX6 System-on-Chip. -It can be mounted on a carrier board providing additional peripheral connectors. -Required root node properties: - - compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl" - - compatible = "technologic,imx6q-ts4900", "fsl,imx6q" - -TS-7970 is a System-on-Module based on the Freescale i.MX6 System-on-Chip. -It can be mounted on a carrier board providing additional peripheral connectors. -Required root node properties: - - compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl" - - compatible = "technologic,imx6q-ts7970", "fsl,imx6q" From 657846f75670cb895672e48c61040c7d24d7361e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Chmiel?= Date: Tue, 8 Jan 2019 17:55:58 +0100 Subject: [PATCH 067/506] ARM: dts: s5pv210: Add reserved memory for MFC on Aries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit THis commit adds memory reservation required by MFC (Multi Format Codec) to run. On S5PV210 both regions needs to be on separate memory banks. Size of both regions is taken from vendor Linux kernel sources. Signed-off-by: Paweł Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 575094ea7024..89525e56cc7c 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -23,6 +23,24 @@ 0x50000000 0x08000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mfc_left: region@43000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x43000000 0x2000000>; + }; + + mfc_right: region@51000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x51000000 0x2000000>; + }; + }; + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>; @@ -329,6 +347,10 @@ status = "okay"; }; +&mfc { + memory-region = <&mfc_left>, <&mfc_right>; +}; + &pinctrl0 { wlan_bt_en: wlan-bt-en { samsung,pins = "gpb-5"; From c7985d8cb4c28390a95992f20c99e6d2ca0e9126 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Tue, 8 Jan 2019 17:55:59 +0100 Subject: [PATCH 068/506] ARM: dts: s5pv210: Add support for more devices present on Aries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit enables following devices present on Aries based phones: - pwm-vibrator attached to PWM 1 - poweroff support - Atmel maXTouch touchscreen, connected to I2C-2 - Broadcom BCM4329 Bluetooth over UART-0 Signed-off-by: Jonathan Bakker Signed-off-by: Paweł Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 68 ++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 89525e56cc7c..8ff70b856334 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -41,6 +41,13 @@ }; }; + vibrator_pwr: regulator-fixed-0 { + compatible = "regulator-fixed"; + regulator-name = "vibrator-en"; + enable-active-high; + gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>; + }; + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>; @@ -314,6 +321,22 @@ reg = <0x36>; }; }; + + vibrator: pwm-vibrator { + compatible = "pwm-vibrator"; + pwms = <&pwm 1 44642 0>; + pwm-names = "enable"; + vcc-supply = <&vibrator_pwr>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; + }; + + poweroff: syscon-poweroff { + compatible = "syscon-poweroff"; + regmap = <&pmu_syscon>; + offset = <0x681c>; /* PS_HOLD_CONTROL */ + value = <0x5200>; + }; }; &fimd { @@ -347,6 +370,23 @@ status = "okay"; }; +&i2c2 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <400000>; + samsung,i2c-slave-addr = <0x10>; + status = "okay"; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&gpj0>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_irq>; + reset-gpios = <&gpj1 3 GPIO_ACTIVE_HIGH>; + }; +}; + &mfc { memory-region = <&mfc_left>, <&mfc_right>; }; @@ -372,6 +412,13 @@ samsung,pin-drv = ; }; + bt_host_wake: bt-host-wake { + samsung,pins = "gph2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + tf_detect: tf-detect { samsung,pins = "gph3-4"; samsung,pin-function = ; @@ -384,6 +431,17 @@ samsung,pin-function = ; samsung,pin-pud = ; }; + + ts_irq: ts-irq { + samsung,pins = "gpj0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pwm { + samsung,pwm-outputs = <1>; }; &sdhci1 { @@ -421,6 +479,16 @@ &uart0 { status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <115200>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_data &uart0_fctl &bt_host_wake>; + shutdown-gpios = <&gpb 3 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpg3 4 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gph2 5 GPIO_ACTIVE_HIGH>; + }; }; &uart1 { From b99f1870b689183ce3674ebc1a32d57ba925d5fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Chmiel?= Date: Tue, 8 Jan 2019 21:05:06 +0100 Subject: [PATCH 069/506] ARM: dts: s5pv210: Add DMC nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds DMC (Dynamic Memory Controller) nodes, which are needed by S5Pv210 cpufreq driver to work. Signed-off-by: Paweł Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index cc22c9db80d2..b2ecbe6f4453 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -25,6 +25,8 @@ aliases { csis0 = &csis0; + dmc0 = &dmc0; + dmc1 = &dmc1; fimc0 = &fimc0; fimc1 = &fimc1; fimc2 = &fimc2; @@ -521,6 +523,16 @@ status = "disabled"; }; + dmc0: dmc@f0000000 { + compatible = "samsung,s5pv210-dmc"; + reg = <0xf0000000 0x1000>; + }; + + dmc1: dmc@f1400000 { + compatible = "samsung,s5pv210-dmc"; + reg = <0xf1400000 0x1000>; + }; + g2d: g2d@fa000000 { compatible = "samsung,s5pv210-g2d"; reg = <0xfa000000 0x1000>; From be6a95a55a095686455307d9437a9a25cf0233ef Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 9 Jan 2019 14:43:03 +0100 Subject: [PATCH 070/506] ARM: dts: s5pv210: Fix onenand's unit address format warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to Devicetree specification, the unit-address must match the first address specified in the reg property of the node. Fix the DTC warning onenand node: arch/arm/boot/dts/s5pv210.dtsi:81.29-93.5: Warning (simple_bus_reg): /soc/onenand@b0000000: simple-bus unit address format error, expected "b0600000" Signed-off-by: Krzysztof Kozlowski Tested-by: Paweł Chmiel --- arch/arm/boot/dts/s5pv210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index b2ecbe6f4453..a44d5eb56bed 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -80,7 +80,7 @@ }; }; - onenand: onenand@b0000000 { + onenand: onenand@b0600000 { compatible = "samsung,s5pv210-onenand"; reg = <0xb0600000 0x2000>, <0xb0000000 0x20000>, From 4de3f59c51f990b99691923c9e5c11928aea196d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 9 Jan 2019 14:52:48 +0100 Subject: [PATCH 071/506] ARM: dts: s3c2416: Fix xti node's missing reg property warning Fix the DTC warning for xti node: arch/arm/boot/dts/s3c2416-smdk2416.dts:23.12-28.5: Warning (simple_bus_reg): /clocks/xti: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s3c2416-smdk2416.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts index 5164386aff3a..cb371bf72f64 100644 --- a/arch/arm/boot/dts/s3c2416-smdk2416.dts +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts @@ -19,9 +19,12 @@ clocks { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - xti: xti { + xti: xti@0 { compatible = "fixed-clock"; + reg = <0>; clock-frequency = <12000000>; clock-output-names = "xti"; #clock-cells = <0>; From 04aacc64ca38ab63863c2798c2fc3fc52718aae6 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 9 Jan 2019 10:48:23 +0100 Subject: [PATCH 072/506] ARM: dts: exynos: Fix conflicting fixed-regulator GPIO flags and properties Bindings of the fixed-regulator, which precedes support for GPIO flags passed via phandle descriptor, introduced its own method annotating that the given GPIO line is active low or high - by using 'enable-active-high' property. The driver always ignored flags passed via GPIO descriptor. Fix the conflicting GPIO flags to match the status forced by the 'enable-active-high' property to avoid future confusion. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroidx.dts | 2 +- arch/arm/boot/dts/exynos5250-arndale.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 348556fcdd9d..a2251581f6b6 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -53,7 +53,7 @@ regulator-name = "p3v3_en"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpa1 1 GPIO_ACTIVE_LOW>; + gpio = <&gpa1 1 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 2ca9319f48f2..b44f03ef3b27 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -100,7 +100,7 @@ regulator-name = "VDD_33ON_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_LOW>; + gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; enable-active-high; }; From 0b94260ac1e11e37f546d06bfae5c5bf13e0ad33 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 9 Jan 2019 10:55:57 +0100 Subject: [PATCH 073/506] ARM: dts: exynos: Fix eMMC regulator properties on Odroid U3 boards LDO20 regulator provides power for the MMC card on Odroid U3 boards. That regulator has been marked as 'boot-on' since the beginning of Odroid X/U3 support, but such flag is not really needed for it. That regulator is correctly described as supply for eMMC card and controlled by its driver. Commit 05f224ca6693 ("regulator: core: Clean enabling always-on regulators + their supplies") changed the way the boot-on regulators are handled and since then regulators marked as 'boot-on' got increased reference count and are not turned off for the system suspend time. The new approach turned out to break suspend/resume support on Odroid U3 with eMMC card, because the card is not properly shutdown due to missing of power cycle. Fix this by removing excessive 'boot-on' flag and let MMC driver to control turning power on and off. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 3a9eb1e91c45..24bcad3dfba9 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -390,7 +390,6 @@ regulator-name = "LDO20_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-boot-on; }; ldo21_reg: LDO21 { From 2fc6f3773733f2a6322ede65abbbe76c9f1908fa Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 17:50:23 +0100 Subject: [PATCH 074/506] ARM: dts: meson6: add the APB2 bus The Mali GPU and the DVB demulator are located in the APB2 bus. Describe this bus so we can add devices to it. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson6.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index ca978ab952cd..65585255910a 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -70,6 +70,14 @@ }; }; + apb2: bus@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x40000>; + }; + xtal: xtal-clk { compatible = "fixed-clock"; clock-frequency = <24000000>; From 7e22d72834870af1396f90d31cbff38f36bbfa3d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 17:50:24 +0100 Subject: [PATCH 075/506] ARM: dts: meson8: add the APB bus Various peripherals (Mali GPU, NAND controller, VPU, etc.) are located in the APB bus. Describe this bus so we can add devices to it. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index e5cd325d7ea8..3fd8260eba92 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -201,6 +201,14 @@ no-map; }; }; + + apb: bus@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x200000>; + }; }; /* end of / */ &aobus { From e402d24d884130ed308ff1d04fdababffcf0fa86 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 17:50:25 +0100 Subject: [PATCH 076/506] ARM: dts: meson8b: add the APB bus Various peripherals (Mali GPU, NAND controller, VPU; etc.) are located in the APB bus. Describe this bus so we can add devices to it. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 22d775460767..5d036842c355 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -178,6 +178,14 @@ no-map; }; }; + + apb: bus@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x200000>; + }; }; /* end of / */ &aobus { From 5938f2c8c8bbdef7cf7746a723f98623a599a0ca Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 18:12:43 +0100 Subject: [PATCH 077/506] dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b compatible Add a compatible string for the Mali-450 GPU on Amlogic Meson8 and Meson8b SoCs. Meson8 uses an "MP6" variant with six pixel processors while Meson8b (as cost-reduced SoC) uses an "MP2" variant with two pixel processors. Both have a reset line to bring the GPU into a well-defined state. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 3f128e4f95c6..ae63f09fda7d 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -13,6 +13,8 @@ Required properties: + allwinner,sun8i-h3-mali + allwinner,sun50i-a64-mali + allwinner,sun50i-h5-mali + + amlogic,meson8-mali + + amlogic,meson8b-mali + amlogic,meson-gxbb-mali + amlogic,meson-gxl-mali + rockchip,rk3036-mali @@ -82,6 +84,10 @@ to specify one more vendor-specific compatible, among: Required properties: * resets: phandle to the reset line for the GPU + - amlogic,meson8-mali and amlogic,meson8b-mali + Required properties: + * resets: phandle to the reset line for the GPU + - Rockchip variants: Required properties: * resets: phandle to the reset line for the GPU From 7d3f6b536e72c94bd19585a3283e8d141614fee0 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 18:12:46 +0100 Subject: [PATCH 078/506] ARM: dts: meson8: add the Mali-450 MP6 GPU Add the Mali-450 GPU and it's OPP table for the Meson8 and Meson8m2 (the latter inherits meson8.dtsi). These SoCs have a Mali-450 GPU with six pixel processors. The OPP table is taken from the 3.10 vendor kernel which uses the following table: FCLK_DEV7 | 1, /* 182.1 Mhz */ FCLK_DEV4 | 1, /* 318.7 Mhz */ FCLK_DEV3 | 1, /* 425 Mhz */ FCLK_DEV5 | 0, /* 510 Mhz */ FCLK_DEV4 | 0, /* 637.5 Mhz */ This describes the mux (FCLK_DEVx) and a 0-based divider in the clock controller. "FCLK" is "fixed_pll" which is running at 2550MHz. The "turbo" setting is described by "turbo_clock = 4" where 4 is the index of the table above. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 58 +++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 3fd8260eba92..1ea5a36c5040 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -166,6 +166,32 @@ }; }; + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-182150000 { + opp-hz = /bits/ 64 <182150000>; + opp-microvolt = <1150000>; + }; + opp-318750000 { + opp-hz = /bits/ 64 <318750000>; + opp-microvolt = <1150000>; + }; + opp-425000000 { + opp-hz = /bits/ 64 <425000000>; + opp-microvolt = <1150000>; + }; + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-microvolt = <1150000>; + }; + opp-637500000 { + opp-hz = /bits/ 64 <637500000>; + opp-microvolt = <1150000>; + turbo-mode; + }; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = , @@ -208,6 +234,38 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd0000000 0x200000>; + + mali: gpu@c0000 { + compatible = "amlogic,meson8-mali", "arm,mali-450"; + reg = <0xc0000 0x40000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2", "pp4", "ppmmu4", + "pp5", "ppmmu5", "pp6", "ppmmu6"; + resets = <&reset RESET_MALI>; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + operating-points-v2 = <&gpu_opp_table>; + switch-delay = <0xffff>; + }; }; }; /* end of / */ From c3ea80b6138caea8a6010fe37c6c3e57cb805b7d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Dec 2018 18:12:47 +0100 Subject: [PATCH 079/506] ARM: dts: meson8b: add the Mali-450 MP2 GPU Add the Mali-450 GPU and it's OPP table for Meson8. The GPU uses two pixel processors in this configuration. The OPP table is taken from the 3.10 vendor kernel which uses the following table: FCLK_DEV5 | 1, /* 255 Mhz */ FCLK_DEV7 | 0, /* 364 Mhz */ FCLK_DEV3 | 1, /* 425 Mhz */ FCLK_DEV5 | 0, /* 510 Mhz */ FCLK_DEV4 | 0, /* 637.5 Mhz */ This describes the mux (FCLK_DEVx) and a 0-based divider in the clock controller. "FCLK" is "fixed_pll" which is running at 2550MHz. The "turbo" setting is described by "turbo_clock = 4" where 4 is the index of the table above. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 46 ++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 5d036842c355..dd498e681939 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -158,6 +158,32 @@ }; }; + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-255000000 { + opp-hz = /bits/ 64 <255000000>; + opp-microvolt = <1150000>; + }; + opp-364300000 { + opp-hz = /bits/ 64 <364300000>; + opp-microvolt = <1150000>; + }; + opp-425000000 { + opp-hz = /bits/ 64 <425000000>; + opp-microvolt = <1150000>; + }; + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-microvolt = <1150000>; + }; + opp-637500000 { + opp-hz = /bits/ 64 <637500000>; + opp-microvolt = <1150000>; + turbo-mode; + }; + }; + pmu { compatible = "arm,cortex-a5-pmu"; interrupts = , @@ -185,6 +211,26 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd0000000 0x200000>; + + mali: gpu@c0000 { + compatible = "amlogic,meson8b-mali", "arm,mali-450"; + reg = <0xc0000 0x40000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1"; + resets = <&reset RESET_MALI>; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + operating-points-v2 = <&gpu_opp_table>; + switch-delay = <0xffff>; + }; }; }; /* end of / */ From 5e6a18ac6caa782fc05cf092e67418110fff27b5 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 13 Dec 2018 15:36:29 +0100 Subject: [PATCH 080/506] arm64: dts: meson-axg: add spdifin Add the SPDIF input device of the axg audio subsystem Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index fffd55787981..781632bd60ed 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1260,6 +1260,18 @@ status = "disabled"; }; + spdifin: audio-controller@400 { + compatible = "amlogic,axg-spdifin"; + reg = <0x0 0x400 0x0 0x30>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFIN"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, + <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; + clock-names = "pclk", "refclk"; + status = "disabled"; + }; + spdifout: audio-controller@480 { compatible = "amlogic,axg-spdifout"; reg = <0x0 0x480 0x0 0x50>; From e6a5539799ab453aee71d41ae003a5559f460364 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 13 Dec 2018 15:36:30 +0100 Subject: [PATCH 081/506] arm64: dts: meson-axg: s400: add spdif-dir codec Add the SPDIF capture codec to the axg s400 board Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 824eba98db2c..14e1fdc73e45 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -95,6 +95,13 @@ sound-name-prefix = "MIC"; }; + spdif_dir: audio-codec-4 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dir"; + status = "okay"; + sound-name-prefix = "DIR"; + }; + emmc_pwrseq: emmc-pwrseq { compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; From 99e322cc512f1c5350b9a1de56980f99a88edb4f Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 13 Dec 2018 15:36:31 +0100 Subject: [PATCH 082/506] arm64: dts: meson-axg: s400: add spdifin to the sound card Enable spdif input device on the S400 and add it to the card Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 14e1fdc73e45..2e1dcf1c26bf 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -256,6 +256,9 @@ "TODDR_A IN 2", "TDMIN_C OUT", "TODDR_B IN 2", "TDMIN_C OUT", "TODDR_C IN 2", "TDMIN_C OUT", + "TODDR_A IN 3", "SPDIFIN Capture", + "TODDR_B IN 3", "SPDIFIN Capture", + "TODDR_C IN 3", "SPDIFIN Capture", "TODDR_A IN 4", "PDM Capture", "TODDR_B IN 4", "PDM Capture", "TODDR_C IN 4", "PDM Capture", @@ -333,6 +336,14 @@ }; dai-link-8 { + sound-dai = <&spdifin>; + + codec { + sound-dai = <&spdif_dir>; + }; + }; + + dai-link-9 { sound-dai = <&pdm>; codec { @@ -490,6 +501,12 @@ vqmmc-supply = <&vddio_boot>; }; +&spdifin { + pinctrl-0 = <&spdif_in_a19_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &spdifout { pinctrl-0 = <&spdif_out_a20_pins>; pinctrl-names = "default"; From a2b91efd30eb7fb77608c3d3e6acaafdf3a8efc4 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 14 Dec 2018 11:55:09 +0100 Subject: [PATCH 083/506] arm64: dts: imx8mq: move watchdog nodes to correct location The were added at the end of the AIPS1 address space, while they are in fact in the middle. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 48 +++++++++++------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 8e9d6d5ed7b2..a55b9329376b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -199,6 +199,30 @@ #interrupt-cells = <2>; }; + wdog1: watchdog@30280000 { + compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; + status = "disabled"; + }; + + wdog2: watchdog@30290000 { + compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; + reg = <0x30290000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; + status = "disabled"; + }; + + wdog3: watchdog@302a0000 { + compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; + reg = <0x302a0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; + status = "disabled"; + }; + iomuxc: iomuxc@30330000 { compatible = "fsl,imx8mq-iomuxc"; reg = <0x30330000 0x10000>; @@ -228,30 +252,6 @@ "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; }; - - wdog1: watchdog@30280000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; - status = "disabled"; - }; - - wdog2: watchdog@30290000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; - status = "disabled"; - }; - - wdog3: watchdog@302a0000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; - status = "disabled"; - }; }; bus@30400000 { /* AIPS2 */ From 5ddb78d6b14954b677436f6acf802303d4414d57 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 18 Dec 2018 04:19:26 +0000 Subject: [PATCH 084/506] ARM: dts: ls1021a: add num-viewport property for PCIe DT nodes Add num-viewport property for PCIe DT nodes to specify how many viewports are implemented. Signed-off-by: Hou Zhiqiang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 6df6a291f4d0..424700061fa0 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -831,6 +831,7 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <4>; + num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ @@ -855,6 +856,7 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <4>; + num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ From 881e90d27a07f723b5c02bc04f2a63f7517c1068 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 18 Dec 2018 04:19:32 +0000 Subject: [PATCH 085/506] arm64: dts: layerscape: add num-viewport property for PCIe DT nodes Add num-viewport property for PCIe DT nodes to specify how many viewports are implemented. Signed-off-by: Hou Zhiqiang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++ arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 3 +++ arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 4 ++++ 5 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 816f3a4537e3..93031798998a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -486,6 +486,7 @@ #size-cells = <2>; device_type = "pci"; num-lanes = <4>; + num-viewport = <2>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 70057b4e46e8..75b7aaa65d21 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -675,6 +675,7 @@ device_type = "pci"; dma-coherent; num-lanes = <4>; + num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ @@ -701,6 +702,7 @@ device_type = "pci"; dma-coherent; num-lanes = <2>; + num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ @@ -727,6 +729,7 @@ device_type = "pci"; dma-coherent; num-lanes = <2>; + num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 9a2106e60e19..3df0ef93a9bf 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -644,6 +644,7 @@ device_type = "pci"; dma-coherent; num-lanes = <4>; + num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ @@ -670,6 +671,7 @@ device_type = "pci"; dma-coherent; num-lanes = <2>; + num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ @@ -696,6 +698,7 @@ device_type = "pci"; dma-coherent; num-lanes = <2>; + num-viewport = <8>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index de93b42b1f51..5556a756bbfe 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -452,6 +452,7 @@ device_type = "pci"; dma-coherent; num-lanes = <4>; + num-viewport = <256>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ @@ -477,6 +478,7 @@ device_type = "pci"; dma-coherent; num-lanes = <4>; + num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ @@ -502,6 +504,7 @@ device_type = "pci"; dma-coherent; num-lanes = <8>; + num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 6d6ca166f86b..5ea0d7710c06 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -627,6 +627,7 @@ device_type = "pci"; dma-coherent; num-lanes = <4>; + num-viewport = <6>; bus-range = <0x0 0xff>; msi-parent = <&its>; #interrupt-cells = <1>; @@ -648,6 +649,7 @@ device_type = "pci"; dma-coherent; num-lanes = <4>; + num-viewport = <6>; bus-range = <0x0 0xff>; msi-parent = <&its>; #interrupt-cells = <1>; @@ -669,6 +671,7 @@ device_type = "pci"; dma-coherent; num-lanes = <8>; + num-viewport = <256>; bus-range = <0x0 0xff>; msi-parent = <&its>; #interrupt-cells = <1>; @@ -690,6 +693,7 @@ device_type = "pci"; dma-coherent; num-lanes = <4>; + num-viewport = <6>; bus-range = <0x0 0xff>; msi-parent = <&its>; #interrupt-cells = <1>; From 83c58a55ce789d9aa3755c9c0e6aa94e35ae1512 Mon Sep 17 00:00:00 2001 From: Nipun Gupta Date: Tue, 18 Dec 2018 04:51:58 +0000 Subject: [PATCH 086/506] arm64: dts: ls1088: add smmu device node This patch also adds the iommu-map property in fsl-mc node, so that fsl-mc can use iommu. Signed-off-by: Nipun Gupta Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 92 ++++++++++++++++++- 1 file changed, 91 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 5556a756bbfe..0fd8909758d8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -518,6 +518,96 @@ status = "disabled"; }; + smmu: iommu@5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #iommu-cells = <1>; + stream-match-mask = <0x7C00>; + #global-interrupts = <12>; + // global secure fault + interrupts = , + // combined secure + , + // global non-secure fault + , + // combined non-secure + , + // performance counter interrupts 0-7 + , + , + , + , + , + , + , + , + // per context interrupt, 64 interrupts + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + cluster1_core0_watchdog: wdt@c000000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; @@ -579,6 +669,7 @@ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ msi-parent = <&its>; + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ #address-cells = <3>; #size-cells = <1>; @@ -652,5 +743,4 @@ method = "smc"; }; }; - }; From 859873fb12baf83009521b1408201c83fc3a2f36 Mon Sep 17 00:00:00 2001 From: Nipun Gupta Date: Tue, 18 Dec 2018 04:52:02 +0000 Subject: [PATCH 087/506] arm64: dts: ls1088: add missing dma-coherent property in fsl-mc Signed-off-by: Nipun Gupta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 0fd8909758d8..ae2fdd22390b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -670,6 +670,7 @@ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ msi-parent = <&its>; iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ + dma-coherent; #address-cells = <3>; #size-cells = <1>; From 1ba67dafb3fd7c0af07c64f3cf984004a5cc497f Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 18 Dec 2018 17:07:46 +0100 Subject: [PATCH 088/506] arm64: dts: fsl: use a generic node name for m25p80 flashes Use a generic node name for the m25p80 flashes on ls1043 and ls1046 boards. Signed-off-by: Alexandre Belloni Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts index 8a500940f124..1aac81da7e37 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts @@ -137,7 +137,7 @@ &qspi { status = "okay"; - qflash0: s25fl128s@0 { + qflash0: flash@0 { compatible = "spansion,m25p80"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts index 2f220ec4947b..eec62c63dafe 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts @@ -165,7 +165,7 @@ &qspi { status = "okay"; - qflash0: s25fl128s@0 { + qflash0: flash@0 { compatible = "spansion,m25p80"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts index 07c665c6e0dc..6a6514d0e5a9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -101,7 +101,7 @@ &qspi { status = "okay"; - qflash0: s25fs512s@0 { + qflash0: flash@0 { compatible = "spansion,m25p80"; #address-cells = <1>; #size-cells = <1>; @@ -111,7 +111,7 @@ reg = <0>; }; - qflash1: s25fs512s@1 { + qflash1: flash@1 { compatible = "spansion,m25p80"; #address-cells = <1>; #size-cells = <1>; From bc3e457072aa9aa830be47556b6a61db27a221c7 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 18 Dec 2018 17:07:48 +0100 Subject: [PATCH 089/506] arm64: dts: fsl: ls1046a: disable the flash controller by default Set the Integrated Flash Controller status to disabled so each board has the option to enable it. All the existing users have status = "okay" so there is no functional change. Signed-off-by: Alexandre Belloni Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 3df0ef93a9bf..cba0eacd18c2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -202,6 +202,7 @@ compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = ; + status = "disabled"; }; qspi: spi@1550000 { From 3ffe6c9621cd9eed35df9f60ee2d68c9ebd39411 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 18 Dec 2018 17:07:49 +0100 Subject: [PATCH 090/506] arm64: dts: fsl: ls1046a: disable uarts by default Disable the UARTs by defaultto avoid registering unused UARTs. This effectively change the number of registered UARTS for the RDB and QDS from 4 to 2 but this seems the right thing to do. It is especially useful when connecting other 8250 uart on PCIe for example as the default maximum number of 8250 UARTs that can be registered is 4. Signed-off-by: Alexandre Belloni Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index cba0eacd18c2..d0ee696e0466 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -425,6 +425,7 @@ reg = <0x00 0x21c0500 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; + status = "disabled"; }; duart1: serial@21c0600 { @@ -432,6 +433,7 @@ reg = <0x00 0x21c0600 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; + status = "disabled"; }; duart2: serial@21d0500 { @@ -439,6 +441,7 @@ reg = <0x0 0x21d0500 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; + status = "disabled"; }; duart3: serial@21d0600 { @@ -446,6 +449,7 @@ reg = <0x0 0x21d0600 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; + status = "disabled"; }; gpio0: gpio@2300000 { From 0ce7b4a7741218465e492d30e4cf90a835fb7dfa Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 19 Dec 2018 05:41:31 +0000 Subject: [PATCH 091/506] ARM: dts: imx6sl: correct PWM ipg clock source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From i.MX6SL Reference Manual, the PWMx's ipg clock for registers access is from perclk, correct them. Signed-off-by: Anson Huang Acked-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index e7524e73efb4..4b4813f176cd 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -338,7 +338,7 @@ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PWM1>, + clocks = <&clks IMX6SL_CLK_PERCLK>, <&clks IMX6SL_CLK_PWM1>; clock-names = "ipg", "per"; }; @@ -348,7 +348,7 @@ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PWM2>, + clocks = <&clks IMX6SL_CLK_PERCLK>, <&clks IMX6SL_CLK_PWM2>; clock-names = "ipg", "per"; }; @@ -358,7 +358,7 @@ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PWM3>, + clocks = <&clks IMX6SL_CLK_PERCLK>, <&clks IMX6SL_CLK_PWM3>; clock-names = "ipg", "per"; }; @@ -368,7 +368,7 @@ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PWM4>, + clocks = <&clks IMX6SL_CLK_PERCLK>, <&clks IMX6SL_CLK_PWM4>; clock-names = "ipg", "per"; }; From cffbb02dafa374fea7adf9f79b009fa1d14c2531 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 21 Jun 2018 20:21:06 +0200 Subject: [PATCH 092/506] ARM: dts: nomadik: Augment NHK15 panel setting The NHK15 panel is specified inside the display controller, which works for the DPI-type DT parsing the old fbdev code used, but for the DRM driver it needs to be spawn as its own device, so we move it out of the display controller. We also drop the panel timings: this should be determined by the hardware or a device-specific compatible string, not by this type of encoding into the device tree. It turns out that this hardware is strapped to the right configuration at boot already and we the driver just reads out the hardware-specified resolution and timings. Drop the "panel,dpi" compatible string altogether. Fix a comment error in the DTS file while we're at it. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-nomadik-nhk15.dts | 85 +++++++++++++++---------- 1 file changed, 51 insertions(+), 34 deletions(-) diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts index 12afdc7467e7..04066f9cb8a3 100644 --- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree for the ST-Ericsson Nomadik S8815 board - * Produced by Calao Systems + * Device Tree for the ST Microelectronics Nomadik NHK8815 board */ /dts-v1/; @@ -182,43 +181,12 @@ pinctrl-names = "default"; pinctrl-0 = <&clcd_24bit_mux>; port { - nomadik_clcd_pads: endpoint { + nomadik_clcd: endpoint { remote-endpoint = <&nomadik_clcd_panel>; arm,pl11x,tft-r0g0b0-pads = <16 8 0>; }; }; - /* - * WVGA connector 21 - * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB - * with TPO touch screen. - */ - panel { - compatible = "tpo,tpg110", "panel-dpi"; - grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; - scen-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - scl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - backlight = <&bl>; - - port { - nomadik_clcd_panel: endpoint { - remote-endpoint = <&nomadik_clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <33200000>; - hactive = <800>; - hback-porch = <216>; - hfront-porch = <40>; - hsync-len = <1>; - vactive = <480>; - vback-porch = <35>; - vfront-porch = <10>; - vsync-len = <1>; - }; - }; }; /* Activate RX/TX and CTS/RTS on UART 0 */ @@ -233,6 +201,55 @@ }; }; + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + /* + * As we're dealing with 3wire SPI, we only define SCK + * and MOSI (in the spec MOSI is called "SDA"). + */ + gpio-sck = <&gpio0 5 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio0 4 GPIO_ACTIVE_HIGH>; + /* + * It's not actually active high, but the frameworks assume + * the polarity of the passed-in GPIO is "normal" (active + * high) then actively drives the line low to select the + * chip. + */ + cs-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + /* + * WVGA connector 21 + * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB + * with TPO touch screen. + */ + panel: display@0 { + /* + * The TPO display driver is connected to a + * 5.7" OSD OSD057VA01CT TFT display. + */ + compatible = "tpo,tpg110"; + reg = <0>; + spi-3wire; + /* 320 ns min period ~= 3 MHz */ + spi-max-frequency = <3000000>; + /* Width and height from the OSD data sheet */ + width-mm = <116>; + height-mm = <87>; + grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; + backlight = <&bl>; + + port { + nomadik_clcd_panel: endpoint { + remote-endpoint = <&nomadik_clcd>; + }; + }; + }; + }; + bl: backlight { compatible = "pwm-backlight"; pwms = <&stmpe0_pwm 0 500000>; From 1000ae68e00f6e6736e38ce1f12a427972b7fd43 Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Wed, 19 Dec 2018 17:41:08 +0800 Subject: [PATCH 093/506] arm64: dts: layerscape: Add incr-burst-type-adjustment property to USB3 node Add this property to all layerscape platforms to improve USB read write performance. Signed-off-by: Ran Wang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++ arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 ++ arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 ++ 6 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 93031798998a..1ce0042b2a14 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -446,6 +446,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; sata: sata@3200000 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 75b7aaa65d21..6fd6116509cc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -611,6 +611,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; usb1: usb3@3000000 { @@ -620,6 +621,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; usb2: usb3@3100000 { @@ -629,6 +631,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; sata: sata@3200000 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index d0ee696e0466..0e762ca92558 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -577,6 +577,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; usb1: usb@3000000 { @@ -586,6 +587,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; usb2: usb@3100000 { @@ -595,6 +597,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; sata: sata@3200000 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index ae2fdd22390b..661137ffa319 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -377,6 +377,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 5ea0d7710c06..d7e78dcd153d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -731,6 +731,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; usb1: usb3@3110000 { @@ -741,6 +742,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; ccn@4000000 { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index a79f5c1ea56d..14e6eb7ec80c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -658,6 +658,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; }; @@ -668,6 +669,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; }; From 703c5e40fd8e69efe3ed4e8a856a43eb841feb99 Mon Sep 17 00:00:00 2001 From: Ioana Ciocoi Radulescu Date: Thu, 20 Dec 2018 17:02:03 +0000 Subject: [PATCH 094/506] arm64: dts: lx2160a: Add fsl-mc node Add the fsl-mc node in the LX2160A device tree. Signed-off-by: Ioana Radulescu Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 117 ++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 14e6eb7ec80c..a373018d225a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -764,5 +764,122 @@ ; dma-coherent; }; + + fsl_mc: fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc"; + reg = <0x00000008 0x0c000000 0 0x40>, + <0x00000000 0x08340000 0 0x40000>; + msi-parent = <&its>; + /* iommu-map property is fixed up by u-boot */ + iommu-map = <0 &smmu 0 0>; + dma-coherent; + #address-cells = <3>; + #size-cells = <1>; + + /* + * Region type 0x0 - MC portals + * Region type 0x1 - QBMAN portals + */ + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; + + /* + * Define the maximum number of MACs present on the SoC. + */ + dpmacs { + #address-cells = <1>; + #size-cells = <0>; + + dpmac1: dpmac@1 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x1>; + }; + + dpmac2: dpmac@2 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x2>; + }; + + dpmac3: dpmac@3 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x3>; + }; + + dpmac4: dpmac@4 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x4>; + }; + + dpmac5: dpmac@5 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x5>; + }; + + dpmac6: dpmac@6 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x6>; + }; + + dpmac7: dpmac@7 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x7>; + }; + + dpmac8: dpmac@8 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x8>; + }; + + dpmac9: dpmac@9 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x9>; + }; + + dpmac10: dpmac@a { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xa>; + }; + + dpmac11: dpmac@b { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xb>; + }; + + dpmac12: dpmac@c { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xc>; + }; + + dpmac13: dpmac@d { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xd>; + }; + + dpmac14: dpmac@e { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xe>; + }; + + dpmac15: dpmac@f { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xf>; + }; + + dpmac16: dpmac@10 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x10>; + }; + + dpmac17: dpmac@11 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x11>; + }; + + dpmac18: dpmac@12 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x12>; + }; + }; + }; }; }; From 0154878dec5cbcc7265783756778a0bee616cff9 Mon Sep 17 00:00:00 2001 From: Ioana Ciocoi Radulescu Date: Thu, 20 Dec 2018 17:02:04 +0000 Subject: [PATCH 095/506] arm64: dts: lx2160a: Add dma-ranges property Add missing property from the soc node in LX2160A dts. Signed-off-by: Ioana Radulescu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index a373018d225a..3f6521c47f51 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -398,6 +398,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; crypto: crypto@8000000 { compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; From c4f70b4f93b092703eae1dc67ef262fb0112fbf5 Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Wed, 19 Dec 2018 17:41:09 +0800 Subject: [PATCH 096/506] ARM: dts: ls1021a: Add incr-burst-byte-adjustment property to USB3 node Add this property to improve USB read write performance. Signed-off-by: Ran Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 424700061fa0..c93971e721bc 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -818,6 +818,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; pcie@3400000 { From e0b22fa041a6d5aad20650fe284e4b96cd32d05c Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 19 Dec 2018 18:56:39 +0300 Subject: [PATCH 097/506] ARM: dts: imx: Change i.MX27 interrupt controller unit name The interrupt controller is located at the physical address 0x10040000. This patch changes the unit name of the controller to reflect the actual address. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 26ff5d419bfc..3652f5556b29 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -40,7 +40,7 @@ spi2 = &cspi3; }; - aitc: aitc-interrupt-controller@e0000000 { + aitc: aitc-interrupt-controller@10040000 { compatible = "fsl,imx27-aitc", "fsl,avic"; interrupt-controller; #interrupt-cells = <1>; From 1fded78a67cb4fb371be02195369f1552a51c6ea Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sun, 23 Dec 2018 09:03:40 +0300 Subject: [PATCH 098/506] ARM: dts: i.MX51: digi-connectcore: Move RTC from SOM to JSK In fact, the RTC battery can only be connected outside the module, so this patch moves the PMIC RTC property and its power from SOM dts to JSK. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts | 12 ++++++++++++ arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 7 ------- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts index 2967a748d859..a5010e9e343b 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts +++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts @@ -27,6 +27,18 @@ status = "okay"; }; +&pmic { + fsl,mc13xxx-uses-rtc; + + regulators { + vcoincell_reg: vcoincell { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 82d8df097ef1..e9421b851ad5 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -37,7 +37,6 @@ reg = <0>; interrupt-parent = <&gpio1>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - fsl,mc13xxx-uses-rtc; regulators { sw1_reg: sw1 { @@ -142,12 +141,6 @@ pwgt2spi_reg: pwgt2spi { regulator-always-on; }; - - vcoincell_reg: vcoincell { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; }; }; }; From 526f56a359c5f7681ba640e8c797d97c98b1b259 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sun, 23 Dec 2018 09:03:41 +0300 Subject: [PATCH 099/506] ARM: dts: i.MX51: imx51-digi-connectcore: Enable ESDHC1 This patch adds definitions for ESDHC1 for Digi Connectore SOM & JSK. This interface can be used to boot a module. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts | 4 ++++ arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 15 +++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts index a5010e9e343b..a2eea58510dc 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts +++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts @@ -21,6 +21,10 @@ }; }; +&esdhc1 { + status = "okay"; +}; + &owire { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_owire>; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index e9421b851ad5..a2a6408203e3 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -145,6 +145,13 @@ }; }; +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + max-frequency = <50000000>; + bus-width = <1>; +}; + &esdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc2>; @@ -234,6 +241,14 @@ >; }; + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5 + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5 + >; + }; + pinctrl_esdhc2: esdhc2grp { fsl,pins = < MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 From 0d422e670b6f9c26a2ef54700a6baa03230a4283 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sun, 23 Dec 2018 09:03:42 +0300 Subject: [PATCH 100/506] ARM: dts: i.MX51: digi-connectcore-som: Add support for I2C bus recovery Define the required properties to enable I2C bus recovery supported by the I2C subsystem. This patch adds GPIO based I2C fault injector for Digi Connectcore SOM. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index a2a6408203e3..d90ba5fe4f1b 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -174,9 +174,12 @@ }; &i2c2 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; clock-frequency = <400000>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; status = "okay"; mma7455l@1d { @@ -290,6 +293,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed + MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed + >; + }; + pinctrl_nfc: nfcgrp { fsl,pins = < MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 From 58bcc8d95545b5300a693d039516e45003e7455d Mon Sep 17 00:00:00 2001 From: Mark Yao Date: Sat, 29 Dec 2018 14:33:16 +0100 Subject: [PATCH 101/506] ARM: dts: rockchip: add rk3066 vop display nodes This patch adds the core display subsystem and vop nodes to rk3066. Signed-off-by: Mark Yao Signed-off-by: Johan Jonker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 47 ++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index b6b3a77da50a..653127a377fa 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -44,6 +44,11 @@ }; }; + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop0_out>, <&vop1_out>; + }; + sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x10000>; @@ -57,6 +62,48 @@ }; }; + vop0: vop@1010c000 { + compatible = "rockchip,rk3066-vop"; + reg = <0x1010c000 0x19c>; + interrupts = ; + clocks = <&cru ACLK_LCDC0>, + <&cru DCLK_LCDC0>, + <&cru HCLK_LCDC0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3066_PD_VIO>; + resets = <&cru SRST_LCDC0_AXI>, + <&cru SRST_LCDC0_AHB>, + <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop0_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + vop1: vop@1010e000 { + compatible = "rockchip,rk3066-vop"; + reg = <0x1010e000 0x19c>; + interrupts = ; + clocks = <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3066_PD_VIO>; + resets = <&cru SRST_LCDC1_AXI>, + <&cru SRST_LCDC1_AHB>, + <&cru SRST_LCDC1_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop1_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + i2s0: i2s@10118000 { compatible = "rockchip,rk3066-i2s"; reg = <0x10118000 0x2000>; From a4b0e36d694d0e9bc4c064e3a597294a84f5dca8 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 3 Jan 2019 23:40:20 -0200 Subject: [PATCH 102/506] ARM: dts: rockchip: Add missing dma-names SPI support for rv1108 Pass the 'dma-names' property to the SPI ports so that DMA can be supported. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index d31370ff28f4..cb26d9d98c34 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -207,6 +207,7 @@ clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; clock-names = "spiclk", "apb_pclk"; dmas = <&pdma 8>, <&pdma 9>; + dma-names = "tx", "rx"; #dma-cells = <2>; #address-cells = <1>; #size-cells = <0>; From fa2b56e7af4682d58bf609f5d655a390195e7c96 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 3 Jan 2019 23:40:21 -0200 Subject: [PATCH 103/506] ARM: dts: rockchip: rv1108: Add spim0 and spim1 pinctrl groups Add the pin settings for the SPI pins so they can be used across multiple boards. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108.dtsi | 36 +++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index cb26d9d98c34..f47ac86d2852 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -834,6 +834,42 @@ }; }; + spim0 { + spim0_clk: spim0-clk { + rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_up>; + }; + + spim0_cs0: spim0-cs0 { + rockchip,pins = <1 RK_PD1 RK_FUNC_2 &pcfg_pull_up>; + }; + + spim0_tx: spim0-tx { + rockchip,pins = <1 RK_PD3 RK_FUNC_2 &pcfg_pull_up>; + }; + + spim0_rx: spim0-rx { + rockchip,pins = <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spim1 { + spim1_clk: spim1-clk { + rockchip,pins = <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; + }; + + spim1_cs0: spim1-cs0 { + rockchip,pins = <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; + }; + + spim1_rx: spim1-rx { + rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; + }; + + spim1_tx: spim1-tx { + rockchip,pins = <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + tsadc { otp_out: otp-out { rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; From d4c03ebe7c035a42c9ba462c7f7e051fd2bb0f73 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 3 Jan 2019 23:40:22 -0200 Subject: [PATCH 104/506] dt-bindings: Add vendor prefix for elgin Add elgin vendor definition as 'Elgin S/A.' Signed-off-by: Otavio Salvador Reviewed-by: Rob Herring Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..0ba5150a8f2e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -113,6 +113,7 @@ eckelmann Eckelmann AG edt Emerging Display Technologies eeti eGalax_eMPIA Technology Inc elan Elan Microelectronic Corp. +elgin Elgin S/A. embest Shenzhen Embest Technology Co., Ltd. emlid Emlid, Ltd. emmicro EM Microelectronic From 4a26c1602927c79dba91de195c3908d786addf64 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 3 Jan 2019 23:40:23 -0200 Subject: [PATCH 105/506] ARM: dts: rv1108: Add support for rv1108-elgin-r1 board rv1108-elgin-r1 board is based on Rockchip RV1108 SoC. Signed-off-by: Otavio Salvador Reviewed-by: Rob Herring Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/arm/rockchip.yaml | 5 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rv1108-elgin-r1.dts | 206 ++++++++++++++++++ 3 files changed, 212 insertions(+) create mode 100644 arch/arm/boot/dts/rv1108-elgin-r1.dts diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index b12958bda09c..d30fff4b4676 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -60,6 +60,11 @@ properties: - const: chipspark,rayeager-px2 - const: rockchip,rk3066a + - description: Elgin RV1108 R1 + items: + - const: elgin,rv1108-r1 + - const: rockchip,rv1108 + - description: Firefly Firefly-RK3288 items: - enum: diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..d9a5649b322b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -868,6 +868,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r9a06g032-rzn1d400-db.dtb \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rv1108-elgin-r1.dtb \ rv1108-evb.dtb \ rk3036-evb.dtb \ rk3036-kylin.dtb \ diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts new file mode 100644 index 000000000000..658057d871af --- /dev/null +++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/* + * Copyright (C) 2018 O.S. Systems Software LTDA. + */ + +/dts-v1/; + +#include "rv1108.dtsi" + +/ { + model = "Elgin RV1108 R1 board"; + compatible = "elgin,rv1108-r1", "rockchip,rv1108"; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x08000000>; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + no-sd; + no-sdio; + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac { + clock_in_out = "output"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <275>; + i2c-scl-falling-time-ns = <16>; + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio0>; + interrupts = ; + rockchip,system-power-controller; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_core: DCDC_REG1 { + regulator-name= "vdd_core"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-state-enabled; + regulator-state-uv = <900000>; + }; + }; + + vdd_cam: DCDC_REG2 { + regulator-name= "vdd_cam"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <2000000>; + regulator-state-mem { + regulator-state-disabled; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name= "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-state-enabled; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name= "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-state-enabled; + regulator-state-uv = <3300000>; + }; + }; + + vdd_10: LDO_REG1 { + regulator-name= "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-state-disabled; + }; + }; + + vcc_18: LDO_REG2 { + regulator-name= "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-state-disabled; + }; + }; + + vdd10_pmu: LDO_REG3 { + regulator-name= "vdd10_pmu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-state-enabled; + regulator-state-uv = <1000000>; + }; + }; + }; + }; +}; + +&spi { + pinctrl-names = "default"; + pinctrl-0 = <&spim1_clk &spim1_cs0 &spim1_tx &spim1_rx>; + status = "okay"; + + dh2228fv: dac@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-cpha; + spi-cpol; + }; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; From 1b5715c602fda7b812af0e190eddcce2812e5417 Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Sun, 6 Jan 2019 10:10:10 +0530 Subject: [PATCH 106/506] arm64: dts: rockchip: add ROCK Pi 4 DTS support ROCK Pi 4 is RK3399 based SBC from radxa.com. board has a 1G/2G/4G lpddr4, CSI, DSI, HDMI, OTG, USB 2.0, USB 3.0, 10/100/1000 RGMII Ethernet Phy, es8316 codec, POE, WIFI (for Model B only), PCIE M.2 support on board. This patch enables - HDMI Display - Console - MMC, EMMC - USB 2.0, USB-3.0 - Ethernet Signed-off-by: Akash Gajjar Signed-off-by: Pragnesh Patel Reviewed-by: Rob Herring Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/arm/rockchip.yaml | 5 + arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3399-rock-pi-4.dts | 606 ++++++++++++++++++ 3 files changed, 612 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index bcc60c492a12..21d09a78869d 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -322,6 +322,11 @@ properties: - const: radxa,rock - const: rockchip,rk3188 + - description: Radxa ROCK Pi 4 + items: + - const: radxa,rockpi4 + - const: rockchip,rk3399 + - description: Radxa Rock2 Square items: - const: radxa,rock2-square diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 1c7406111dfd..899f4a75b058 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -19,6 +19,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts new file mode 100644 index 000000000000..4a543f2117d4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts @@ -0,0 +1,606 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Akash Gajjar + * Copyright (c) 2019 Pragnesh Patel + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Radxa ROCK Pi 4"; + compatible = "radxa,rockpi4", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc12v_dcin: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr_en>; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_lan: vcc3v3-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_lan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_codec: LDO_REG1 { + regulator-name = "vcc1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_hdmi: LDO_REG2 { + regulator-name = "vcc1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc0v9_hdmi: LDO_REG7 { + regulator-name = "vcc0v9_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_cam: SWITCH_REG1 { + regulator-name = "vcc_cam"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_mipi: SWITCH_REG2 { + regulator-name = "vcc_mipi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc_3v0>; + audio-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + status = "okay"; + + pmu1830-supply = <&vcc_3v0>; +}; + +&pinctrl { + pcie { + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0-typec-en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + status = "okay"; + + vref-supply = <&vcc_1v8>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + status = "okay"; + + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; From 839eb8c7738ba835f6cf1a2190ffbb7108024160 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Fri, 11 Jan 2019 11:37:24 +0000 Subject: [PATCH 107/506] dt-bindings: arm: imx: add imx8qxp mek support i.MX 8QuadXPlus is a quad (4x) Cortex-A35 proccessor with powerful graphic and multimedia features. This patch adds imx8qxp mek board support. Cc: Shawn Guo Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a4d625d7ff4d..d34fe0749199 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -151,6 +151,12 @@ properties: - const: compulab,cl-som-imx7 - const: fsl,imx7d + - description: i.MX8QXP based Boards + items: + - enum: + - fsl,imx8qxp-mek # i.MX8QXP MEK Board + - const: fsl,imx8qxp + - description: Freescale Vybrid Platform Device Tree Bindings From 67d62e5a3b55d470101eff378f5cb7437de0f26a Mon Sep 17 00:00:00 2001 From: Evan Green Date: Thu, 6 Dec 2018 10:45:21 -0800 Subject: [PATCH 108/506] arm64: dts: qcom: sdm845: Add SD node Add one of the two SD controllers to SDM845. Reviewed-by: Douglas Anderson Reviewed-by: Bjorn Andersson Signed-off-by: Evan Green Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index c27cbd3bcb0a..5e5544cb80ab 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1348,6 +1348,21 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + status = "disabled"; + }; + usb_1_hsphy: phy@88e2000 { compatible = "qcom,sdm845-qusb2-phy"; reg = <0x88e2000 0x400>; From b454dbdb8f067288bee409c5e9f3101004b83125 Mon Sep 17 00:00:00 2001 From: Evan Green Date: Thu, 6 Dec 2018 10:45:22 -0800 Subject: [PATCH 109/506] arm64: dts: qcom: sdm845: Add SD nodes for sdm845-mtp Enable support for one of the micro SD slots on the MTP. Reviewed-by: Douglas Anderson Reviewed-by: Bjorn Andersson Signed-off-by: Evan Green Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 58 ++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index b3def0358177..cde76da42cbb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include #include #include "sdm845.dtsi" @@ -358,8 +359,16 @@ status = "okay"; }; -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vddpx_2>; + + cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; }; &uart9 { @@ -450,3 +459,48 @@ bias-pull-up; }; }; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + sdc2_clk: sdc2-clk { + pinconf { + pins = "sdc2_clk"; + bias-disable; + + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + */ + drive-strength = <16>; + }; + }; + + sdc2_cmd: sdc2-cmd { + pinconf { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + sdc2_data: sdc2-data { + pinconf { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + sd_card_det_n: sd-card-det-n { + pinmux { + pins = "gpio126"; + function = "gpio"; + }; + + pinconf { + pins = "gpio126"; + bias-pull-up; + }; + }; +}; From 4429e57567bb728ba1c81332e7e68d898e510d1c Mon Sep 17 00:00:00 2001 From: Vivek Gautam Date: Thu, 11 Oct 2018 15:19:30 +0530 Subject: [PATCH 110/506] arm64: dts: sdm845: Add node for arm,mmu-500 Add device node for arm,mmu-500 available on sdm845. This MMU-500 with single TCU and multiple TBU architecture is shared among all the peripherals except gpu. Signed-off-by: Vivek Gautam Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 72 ++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5e5544cb80ab..0f3d84af949d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1590,6 +1590,78 @@ cell-index = <0>; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; + reg = <0x15000000 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + apss_shared: mailbox@17990000 { compatible = "qcom,sdm845-apss-shared"; reg = <0x17990000 0x1000>; From cc16687fbd740431d9f9ebbfb64ace51676b9d3b Mon Sep 17 00:00:00 2001 From: Evan Green Date: Mon, 10 Dec 2018 11:28:24 -0800 Subject: [PATCH 111/506] arm64: dts: qcom: sdm845: add UFS controller Add the UFS controller and PHY to SDM845. Reviewed-by: Bjorn Andersson Signed-off-by: Evan Green Signed-off-by: Douglas Anderson [bjorn: Add iommu context for the host controller] Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 66 ++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0f3d84af949d..d92dd49ed2c3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -981,6 +981,72 @@ }; }; + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sdm845-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x1d84000 0x2500>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0x100 0xf>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sdm845-qmp-ufs-phy"; + reg = <0x1d87000 0x18c>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + + ufs_mem_phy_lanes: lanes@1d87400 { + reg = <0x1d87400 0x108>, + <0x1d87600 0x1e0>, + <0x1d87c00 0x1dc>, + <0x1d87800 0x108>, + <0x1d87a00 0x1e0>; + #phy-cells = <0>; + }; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x40000>; From b010fdb4ea58fb1a0c59c550ef5692745b1e4dc2 Mon Sep 17 00:00:00 2001 From: Can Guo Date: Mon, 10 Dec 2018 11:28:25 -0800 Subject: [PATCH 112/506] arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp Enable the UFS host controller and PHY on sdm845-mtp. Reviewed-by: Vivek Gautam Reviewed-by: Douglas Anderson Signed-off-by: Can Guo Signed-off-by: Evan Green Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index cde76da42cbb..55292f2f1552 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -375,6 +375,20 @@ status = "okay"; }; +&ufs_mem_hc { + status = "okay"; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; +}; + &usb_1 { status = "okay"; }; From 9ebfcba1ac46841a60813b4e172108215b4f1525 Mon Sep 17 00:00:00 2001 From: Evan Green Date: Mon, 10 Dec 2018 11:28:26 -0800 Subject: [PATCH 113/506] arm64: dts: qcom: sdm845: Add USB PHY lane two Add the second lane registers for the USB PHY, now that the QMP phy bindings have been updated. This way the driver can stop reaching beyond its register region to get at the second lane. Reviewed-by: Douglas Anderson Reviewed-by: Bjorn Andersson Signed-off-by: Evan Green Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d92dd49ed2c3..738345e27d36 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1480,10 +1480,12 @@ <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: lane@88e9200 { + usb_1_ssphy: lanes@88e9200 { reg = <0x88e9200 0x128>, <0x88e9400 0x200>, <0x88e9c00 0x218>, + <0x88e9600 0x128>, + <0x88e9800 0x200>, <0x88e9a00 0x100>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; From c604b82a09ce3244add85064f8538d45f879a980 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 21 Dec 2018 23:44:23 +0530 Subject: [PATCH 114/506] arm64: dts: sdm845: Add cpufreq device node This change adds the cpufreq node as per the bindings example for SDM845. Reviewed-by: Matthias Kaehlcke Signed-off-by: Taniya Das Tested-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 738345e27d36..d9be5bba62c4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -99,6 +99,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x0>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -114,6 +115,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x100>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_100>; L2_100: l2-cache { compatible = "cache"; @@ -126,6 +128,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x200>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_200>; L2_200: l2-cache { compatible = "cache"; @@ -138,6 +141,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x300>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_300>; L2_300: l2-cache { compatible = "cache"; @@ -150,6 +154,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x400>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_400>; L2_400: l2-cache { compatible = "cache"; @@ -162,6 +167,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x500>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_500>; L2_500: l2-cache { compatible = "cache"; @@ -174,6 +180,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x600>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_600>; L2_600: l2-cache { compatible = "cache"; @@ -186,6 +193,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x700>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_700>; L2_700: l2-cache { compatible = "cache"; @@ -1836,6 +1844,17 @@ status = "disabled"; }; }; + + cpufreq_hw: cpufreq@17d43000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; thermal-zones { From f72281126815389f63e88fb8916fdf64631d1caf Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Thu, 3 Jan 2019 21:34:55 +0100 Subject: [PATCH 115/506] arm64: dts: qcom: qcs404: sdcc1: enable HS400 The controller can support EXT_CSD_CARD_TYPE_HS400_1_8V cards. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index a39924efebe4..2c2c9b00c022 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -127,6 +127,7 @@ status = "ok"; mmc-ddr-1_8v; + mmc-hs400-1_8v; bus-width = <8>; non-removable; From 4bbbca1e7fea961084eaa0a58cd126f969dd3901 Mon Sep 17 00:00:00 2001 From: Govind Singh Date: Tue, 27 Nov 2018 20:47:16 +0530 Subject: [PATCH 116/506] arm64: dts: qcom: qcs404: Add WCN3990 WLAN module device node Add device node for the ath10k SNOC platform driver probe and add resources required for WCN3990 on qcs404 soc. Optional clock and regulator controls are not yet available in upstream, hence add them once available. Reviewed-by: Vinod Koul Signed-off-by: Govind Singh Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/qcs404.dtsi | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 2c2c9b00c022..ba4152318854 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -187,3 +187,7 @@ }; }; }; + +&wifi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 9b5c16562bbe..f3d77e7ee0d2 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -346,6 +346,26 @@ status = "okay"; }; + wifi: wifi@a000000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0xa000000 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_msa_mem>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; From 041b9a7b9fdbe4f12c2e48ead3d45ef67d830cd6 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Wed, 12 Dec 2018 15:47:55 +0530 Subject: [PATCH 117/506] arm64: dts: pms405: Export PMIC temperature to thermal framework The PMS405 PMIC has an ADC that exposes the on-die temperature that we wire up to spmi-temp-alarm thermal driver. This allows the PMIC temperature to be exposed to Linux through the thermal framework. Signed-off-by: Amit Kucheria Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pms405.dtsi | 79 ++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index ad2b62dfc9f6..1bb836d1e8aa 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -3,6 +3,32 @@ #include #include +#include +#include + +/ { + thermal-zones { + pms405 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&pms405_temp>; + + trips { + pms405_alert0: pms405-alert0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + pms405_crit: pms405-crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; &spmi_bus { pms405_0: pms405@0 { @@ -45,6 +71,59 @@ }; }; + pms405_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pms405_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pms405_adc: adc@3100 { + compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + ref_gnd { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + qcom,pre-scaling = <1 3>; + }; + + die_temp { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + xo_therm_100k_pu { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + amux_thm1_100k_pu { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + amux_thm3_100k_pu { + reg = ; + qcom,pre-scaling = <1 1>; + }; + }; + rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>; From af61bef513ba179559e56908b8c465e587bc3890 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 14 Dec 2018 12:01:02 +0100 Subject: [PATCH 118/506] arm64: dts: apq8016-sbc: Increase load on l11 for SDCARD In the same way as for msm8974-hammerhead, l11 load, used for SDCARD VMMC, needs to be increased in order to prevent any voltage drop issues (due to limited current) happening with some SDCARDS or during specific operations (e.g. write). Tested on Dragonboard-410c and DART-SD410 boards. Fixes: 4c7d53d16d77 (arm64: dts: apq8016-sbc: add regulators support) Reported-by: Manabu Igusa Signed-off-by: Loic Poulain Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 46feedf7c989..134617d87a1a 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -644,6 +644,8 @@ l11 { regulator-min-microvolt = <1750000>; regulator-max-microvolt = <3337000>; + regulator-allow-set-load; + regulator-system-load = <200000>; }; l12 { From ff10032fb309d0baa0b79e28009bf154de08d341 Mon Sep 17 00:00:00 2001 From: Jakob Wuhrer Date: Fri, 14 Dec 2018 18:01:30 +0100 Subject: [PATCH 119/506] arm64: dts: qcom: Correct "gpiio" typo in msm8996-pins gpiio5 is missspelt in msm8996-pins.dtsi, fix that. Signed-off-by: Jakob Wuhrer Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996-pins.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 8d5114d16d09..131878db9852 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -139,7 +139,7 @@ }; pinconf { - pins = "gpio4", "gpiio5", "gpio6", "gpio7"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; drive-strength = <2>; bias-disable; }; From 0f60e6fb54fb2d749e701d910de7f39f67c0020c Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 23 Nov 2018 09:44:38 +0100 Subject: [PATCH 120/506] arm64: dts: qcom: pm8916: Add PON watchdog node Add watchdog child node to the PM8916 PON device. Signed-off-by: Loic Poulain Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 15a37cbcd216..9dd2df1cbf47 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -32,6 +32,12 @@ bias-pull-up; linux,code = ; }; + + watchdog { + compatible = "qcom,pm8916-wdt"; + interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>; + timeout-sec = <60>; + }; }; pm8916_gpios: gpios@c000 { From b7f264fa496eb2a6dd1d67dc91dbe8ffcb142487 Mon Sep 17 00:00:00 2001 From: Dan Haab Date: Sun, 2 Dec 2018 17:00:15 -0700 Subject: [PATCH 121/506] ARM: dts: BCM53573: Relicense Luxul files to the GPL 2.0+ / MIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches licensing used by other BCM53573 files and BCM5301X. Signed-off-by: Dan Haab Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts | 3 +-- arch/arm/boot/dts/bcm47189-luxul-xap-810.dts | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts index 74c83b0ca54e..3902f69f7f1a 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright 2017 Luxul Inc. - * - * Licensed under the ISC license. */ /dts-v1/; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts index 214df18f3a75..4a522deb2d52 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright 2017 Luxul Inc. - * - * Licensed under the ISC license. */ /dts-v1/; From 37f7453a4b7aa3e1d1608edeb500b105257ee945 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 14 Jan 2019 17:52:50 -0600 Subject: [PATCH 122/506] ARM: dts: socfpga: update missing reset property peripherals Add reset property for gpio, i2c, sdmmc, nand, qspi, spi, uart, and watchdog on base socfpga and socfpga_arria10. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 12 ++++++++++++ arch/arm/boot/dts/socfpga_arria10.dtsi | 18 ++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index dcb8fba3d709..f365003f0102 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -585,6 +585,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff708000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO0_RESET>; status = "disabled"; porta: gpio-controller@0 { @@ -605,6 +606,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff709000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO1_RESET>; status = "disabled"; portb: gpio-controller@0 { @@ -625,6 +627,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff70a000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO2_RESET>; status = "disabled"; portc: gpio-controller@0 { @@ -735,6 +738,7 @@ #size-cells = <0>; clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; + resets = <&rst SDMMC_RESET>; status = "disabled"; }; @@ -748,6 +752,7 @@ interrupts = <0x0 0x90 0x4>; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; + resets = <&rst NAND_RESET>; status = "disabled"; }; @@ -767,6 +772,7 @@ cdns,fifo-width = <4>; cdns,trigger-address = <0x00000000>; clocks = <&qspi_clk>; + resets = <&rst QSPI_RESET>; status = "disabled"; }; @@ -801,6 +807,7 @@ interrupts = <0 154 4>; num-cs = <4>; clocks = <&spi_m_clk>; + resets = <&rst SPIM0_RESET>; status = "disabled"; }; @@ -812,6 +819,7 @@ interrupts = <0 155 4>; num-cs = <4>; clocks = <&spi_m_clk>; + resets = <&rst SPIM1_RESET>; status = "disabled"; }; @@ -878,6 +886,7 @@ dmas = <&pdma 28>, <&pdma 29>; dma-names = "tx", "rx"; + resets = <&rst UART0_RESET>; }; uart1: serial1@ffc03000 { @@ -890,6 +899,7 @@ dmas = <&pdma 30>, <&pdma 31>; dma-names = "tx", "rx"; + resets = <&rst UART1_RESET>; }; usbphy0: usbphy { @@ -929,6 +939,7 @@ reg = <0xffd02000 0x1000>; interrupts = <0 171 4>; clocks = <&osc1>; + resets = <&rst L4WD0_RESET>; status = "disabled"; }; @@ -937,6 +948,7 @@ reg = <0xffd03000 0x1000>; interrupts = <0 172 4>; clocks = <&osc1>; + resets = <&rst L4WD1_RESET>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index e41fa23481c3..ae24599d5829 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -470,6 +470,7 @@ tx-fifo-depth = <4096>; rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; + resets = <&rst EMAC2_RESET>; clock-names = "stmmaceth"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; @@ -480,6 +481,7 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xffc02900 0x100>; + resets = <&rst GPIO0_RESET>; status = "disabled"; porta: gpio-controller@0 { @@ -499,6 +501,7 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xffc02a00 0x100>; + resets = <&rst GPIO1_RESET>; status = "disabled"; portb: gpio-controller@0 { @@ -518,6 +521,7 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xffc02b00 0x100>; + resets = <&rst GPIO2_RESET>; status = "disabled"; portc: gpio-controller@0 { @@ -548,6 +552,7 @@ reg = <0xffc02200 0x100>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C0_RESET>; status = "disabled"; }; @@ -558,6 +563,7 @@ reg = <0xffc02300 0x100>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C1_RESET>; status = "disabled"; }; @@ -568,6 +574,7 @@ reg = <0xffc02400 0x100>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C2_RESET>; status = "disabled"; }; @@ -578,6 +585,7 @@ reg = <0xffc02500 0x100>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C3_RESET>; status = "disabled"; }; @@ -588,6 +596,7 @@ reg = <0xffc02600 0x100>; interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; + resets = <&rst I2C4_RESET>; status = "disabled"; }; @@ -600,6 +609,7 @@ num-cs = <4>; /*32bit_access;*/ clocks = <&spi_m_clk>; + resets = <&rst SPIM0_RESET>; status = "disabled"; }; @@ -614,6 +624,7 @@ tx-dma-channel = <&pdma 16>; rx-dma-channel = <&pdma 17>; clocks = <&spi_m_clk>; + resets = <&rst SPIM1_RESET>; status = "disabled"; }; @@ -642,6 +653,7 @@ fifo-depth = <0x400>; clocks = <&l4_mp_clk>, <&sdmmc_clk>; clock-names = "biu", "ciu"; + resets = <&rst SDMMC_RESET>; status = "disabled"; }; @@ -655,6 +667,7 @@ interrupts = <0 99 4>; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; + resets = <&rst NAND_RESET>; status = "disabled"; }; @@ -739,6 +752,7 @@ cdns,fifo-width = <4>; cdns,trigger-address = <0x00000000>; clocks = <&qspi_clk>; + resets = <&rst QSPI_RESET>; status = "disabled"; }; @@ -815,6 +829,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + resets = <&rst UART0_RESET>; status = "disabled"; }; @@ -825,6 +840,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + resets = <&rst UART1_RESET>; status = "disabled"; }; @@ -865,6 +881,7 @@ reg = <0xffd00200 0x100>; interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sys_free_clk>; + resets = <&rst L4WD0_RESET>; status = "disabled"; }; @@ -873,6 +890,7 @@ reg = <0xffd00300 0x100>; interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sys_free_clk>; + resets = <&rst L4WD1_RESET>; status = "disabled"; }; }; From 062904f2bccf6b841a7d6989394975c3740c399c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sun, 13 Jan 2019 17:14:13 +0100 Subject: [PATCH 123/506] arm64: dts: allwinner: a64: Fix a typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This typo inverted the meaning of the comment, but the rest of the comment and the code reveal that the regulator in question needs to be on at all times. Signed-off-by: Jonathan Neuschäfer Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index c455b24dd079..f9eede0a8bd3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -239,7 +239,7 @@ }; /* - * The A64 chip cannot work without this regulator off, although + * The A64 chip cannot work with this regulator off, although * it seems to be only driving the AR100 core. * Maybe we don't still know well about CPUs domain. */ From 3d91ba65fecdcfd3353514c4d53a66e2080f4eb0 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Fri, 11 Jan 2019 11:37:29 +0000 Subject: [PATCH 124/506] arm64: dts: imx: add imx8qxp support i.MX 8QuadXPlus is a quad (4x) Cortex-A35 proccessor with powerful graphic and multimedia features. This patch adds the core SoC dtsi file support. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 442 +++++++++++++++++++++ 1 file changed, 442 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi new file mode 100644 index 000000000000..c312697ebb9c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Dong Aisheng + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &adma_lpuart0; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* We have 1 clusters with 4 Cortex-A35 cores */ + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3"; + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 0 1 + &lsio_mu1 0 2 + &lsio_mu1 0 3 + &lsio_mu1 1 0 + &lsio_mu1 1 1 + &lsio_mu1 1 2 + &lsio_mu1 1 3>; + + clk: clock-controller { + compatible = "fsl,imx8qxp-clk"; + #clock-cells = <1>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qxp-iomuxc"; + }; + + pd: imx8qx-pd { + compatible = "fsl,imx8qxp-scu-pd"; + #power-domain-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + adma_subsys: bus@59000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x59000000 0x0 0x59000000 0x2000000>; + + adma_lpcg: clock-controller@59000000 { + compatible = "fsl,imx8qxp-lpcg-adma"; + reg = <0x59000000 0x2000000>; + #clock-cells = <1>; + }; + + adma_lpuart0: serial@5a060000 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x5a060000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_UART_0>; + status = "disabled"; + }; + + adma_i2c0: i2c@5a800000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x5a800000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_0>; + status = "disabled"; + }; + + adma_i2c1: i2c@5a810000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x5a810000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_1>; + status = "disabled"; + }; + + adma_i2c2: i2c@5a820000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x5a820000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_2>; + status = "disabled"; + }; + + adma_i2c3: i2c@5a830000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x5a830000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_3>; + status = "disabled"; + }; + }; + + conn_subsys: bus@5b000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; + + conn_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg-conn"; + reg = <0x5b200000 0xb0000>; + #clock-cells = <1>; + }; + + usdhc1: mmc@5b010000 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x5b010000 0x10000>; + clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_SDHC_0>; + status = "disabled"; + }; + + usdhc2: mmc@5b020000 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x5b020000 0x10000>; + clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_SDHC_1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: mmc@5b030000 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x5b030000 0x10000>; + clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_SDHC_2>; + status = "disabled"; + }; + + fec1: ethernet@5b040000 { + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; + reg = <0x5b040000 0x10000>; + interrupts = , + , + , + ; + clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd IMX_SC_R_ENET_0>; + status = "disabled"; + }; + + fec2: ethernet@5b050000 { + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; + reg = <0x5b050000 0x10000>; + interrupts = , + , + , + ; + clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd IMX_SC_R_ENET_1>; + status = "disabled"; + }; + }; + + lsio_subsys: bus@5d000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; + + lsio_lpcg: clock-controller@5d400000 { + compatible = "fsl,imx8qxp-lpcg-lsio"; + reg = <0x5d400000 0x400000>; + #clock-cells = <1>; + }; + + lsio_mu0: mailbox@5d1b0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1b0000 0x10000>; + interrupts = ; + #mbox-cells = <0>; + status = "disabled"; + }; + + lsio_mu1: mailbox@5d1c0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1c0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + lsio_mu3: mailbox@5d1e0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1e0000 0x10000>; + interrupts = ; + #mbox-cells = <0>; + status = "disabled"; + }; + + lsio_mu4: mailbox@5d1f0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1f0000 0x10000>; + interrupts = ; + #mbox-cells = <0>; + status = "disabled"; + }; + + lsio_gpio0: gpio@5d080000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d080000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_0>; + }; + + lsio_gpio1: gpio@5d090000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d090000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_1>; + }; + + lsio_gpio2: gpio@5d0a0000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d0a0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_2>; + }; + + lsio_gpio3: gpio@5d0b0000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d0b0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_3>; + }; + + lsio_gpio4: gpio@5d0c0000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d0c0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_4>; + }; + + lsio_gpio5: gpio@5d0d0000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d0d0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_5>; + }; + + lsio_gpio6: gpio@5d0e0000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d0e0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_6>; + }; + + lsio_gpio7: gpio@5d0f0000 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + reg = <0x5d0f0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_7>; + }; + }; +}; From fdea904e85e1c20568d56b66e65d1f5e0e821597 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Fri, 11 Jan 2019 11:37:33 +0000 Subject: [PATCH 125/506] arm64: dts: imx: add imx8qxp mek support i.MX 8QuadXPlus is a quad (4x) Cortex-A35 proccessor with powerful graphic and multimedia features. This patch adds imx8qxp mek board support. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 137 ++++++++++++++++++ 2 files changed, 138 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f9be2426f83c..0db6e37a0dab 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -20,3 +20,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts new file mode 100644 index 000000000000..03aad66545c5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2018 NXP + */ + +/dts-v1/; + +#include "imx8qxp.dtsi" + +/ { + model = "Freescale i.MX8QXP MEK"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + + chosen { + stdout-path = &adma_lpuart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adma_lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; +}; From 6334f879bf9321b1a36cd5a884cca5a4014e6eaa Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 14 Jan 2019 09:48:42 +0800 Subject: [PATCH 126/506] arm64: dts: imx: add i.MX8QXP system controller RTC support Add i.MX8QXP system controller RTC support. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index c312697ebb9c..bb877cf25edc 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -112,6 +112,10 @@ compatible = "fsl,imx8qxp-scu-pd"; #power-domain-cells = <1>; }; + + rtc: rtc { + compatible = "fsl,imx8qxp-sc-rtc"; + }; }; timer { From 35d6808221bd22005839ded36ddae381fe08e381 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 11 Jan 2019 06:22:40 +0000 Subject: [PATCH 127/506] dt-bindings: fsl: add imx7ulp system integration module binding Add i.MX7ULP system integration module (SIM) binding. Signed-off-by: Anson Huang Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../bindings/arm/freescale/fsl,imx7ulp-sim.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt new file mode 100644 index 000000000000..7d0c7f002401 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt @@ -0,0 +1,16 @@ +Freescale i.MX7ULP System Integration Module +---------------------------------------------- +The system integration module (SIM) provides system control and chip configuration +registers. In this module, chip revision information is located in JTAG ID register, +and a set of registers have been made available in DGO domain for SW use, with the +objective to maintain its value between system resets. + +Required properties: +- compatible: Should be "fsl,imx7ulp-sim". +- reg: Specifies base physical address and size of the register sets. + +Example: +sim: sim@410a3000 { + compatible = "fsl,imx7ulp-sim", "syscon"; + reg = <0x410a3000 0x1000>; +}; From a0e046e642b1f0a64da6d78d9fdc42d9845b07f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Mon, 14 Jan 2019 18:03:16 +0100 Subject: [PATCH 128/506] arm64: dts: imx8mq: Add pwm device nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We can reuse the pwm from fsl,imx27-pwm as with other imx SOCs. Signed-off-by: Guido Günther Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index a55b9329376b..0225eae2216e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -259,6 +259,50 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x30400000 0x30400000 0x400000>; + + pwm1: pwm@30660000 { + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, + <&clk IMX8MQ_CLK_PWM1_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, + <&clk IMX8MQ_CLK_PWM2_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, + <&clk IMX8MQ_CLK_PWM3_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, + <&clk IMX8MQ_CLK_PWM4_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; }; bus@30800000 { /* AIPS3 */ From fdbcc04da246876290e11e89d987cc46c237050b Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 15 Jan 2019 12:01:44 +0100 Subject: [PATCH 129/506] arm64: dts: imx8mq: add GPC power domains This adds support for the power domain controller found on the i.MX8MQ SoC. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 70 +++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 0225eae2216e..892063a7c26c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include #include #include "imx8mq-pinfunc.h" @@ -252,6 +253,75 @@ "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mq-gpc"; + reg = <0x303a0000 0x10000>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_mipi: power-domain@0 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_pcie1: power-domain@1 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_otg1: power-domain@2 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_otg2: power-domain@3 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_ddr1: power-domain@4 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_gpu: power-domain@5 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, + <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, + <&clk IMX8MQ_CLK_GPU_AXI>, + <&clk IMX8MQ_CLK_GPU_AHB>; + }; + + pgc_vpu: power-domain@6 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_disp: power-domain@7 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_mipi_csi1: power-domain@8 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_mipi_csi2: power-domain@9 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_pcie2: power-domain@a { + #power-domain-cells = <0>; + reg = ; + }; + }; + }; }; bus@30400000 { /* AIPS2 */ From 24ef3b6e22fe7268603ac435868e9c99dae12cda Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vok=C3=A1=C4=8D=20Michal?= Date: Tue, 15 Jan 2019 14:22:44 +0000 Subject: [PATCH 130/506] dt-bindings: arm: Add Y Soft IOTA Draco, Hydra and Ursa boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are i.MX6DualLite/Solo based single board computers used in various Y Soft products. Cc: Andrew Lunn Signed-off-by: Michal Vokáč Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index d34fe0749199..8a571c7dc11a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -94,6 +94,9 @@ properties: - fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 + - ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board + - ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board + - ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board - const: fsl,imx6dl - description: i.MX6SL based Boards From 869d1375a495e6217fdfda6a59b13812d2f3a569 Mon Sep 17 00:00:00 2001 From: Xiaoting Liu Date: Thu, 10 Jan 2019 10:29:13 +0800 Subject: [PATCH 131/506] ARM: dts: aspeed: stardragon4800: Add power supply Add Delta Electronics power supply DPS-650-AB. Signed-off-by: Xiaoting Liu Signed-off-by: Joel Stanley --- .../boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts index bdfd8c9f3a7c..521afbea2c5b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts @@ -173,6 +173,16 @@ }; }; }; + + dps650ab@58 { + compatible = "delta,dps650ab"; + reg = <0x58>; + }; + + dps650ab@59 { + compatible = "delta,dps650ab"; + reg = <0x59>; + }; }; &i2c9 { From 80baf890da963782f0d84f45a44700fb3530a03c Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 27 Aug 2018 16:16:01 -0700 Subject: [PATCH 132/506] ARM: dts: aspeed-palmetto: Add i2c OCC hwmon node Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index 9aa1d4467453..b854ac0bae9a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -169,6 +169,11 @@ &i2c3 { status = "okay"; + + occ-hwmon@50 { + compatible = "ibm,p8-occ-hwmon"; + reg = <0x50>; + }; }; &i2c4 { From 8b88029380af76f1bdb1d0534c789ad150c32efa Mon Sep 17 00:00:00 2001 From: Mark Walton Date: Fri, 14 Dec 2018 12:07:07 +0000 Subject: [PATCH 133/506] ARM: dts: aspeed: Add #interrupt-cells property to gpio controllers Allows the GPIO controller to be used as an interrupt parent. of_irq_find_parent() skips interrupt controller nodes that do not have the #interrupt-cells property. Signed-off-by: Mark Walton Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 1 + arch/arm/boot/dts/aspeed-g5.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 69f6b9d2e7e7..9549f867aa1e 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -197,6 +197,7 @@ gpio-ranges = <&pinctrl 0 0 220>; clocks = <&syscon ASPEED_CLK_APB>; interrupt-controller; + #interrupt-cells = <2>; }; timer: timer@1e782000 { diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index d107459fc0f8..a1999f3fe330 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -250,6 +250,7 @@ gpio-ranges = <&pinctrl 0 0 220>; clocks = <&syscon ASPEED_CLK_APB>; interrupt-controller; + #interrupt-cells = <2>; }; timer: timer@1e782000 { From 9e9a6ad1d7f2f70be80388308d10a09aa985edc5 Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Mon, 17 Dec 2018 12:04:03 -0800 Subject: [PATCH 134/506] ARM: dts: aspeed: Add KCS support for LPC BMC This adds the description of the four Keyboard Controller Style (KCS) IPMI communication channels present in the ASPEED BMC. They are disabled by default. Signed-off-by: Vijay Khemka Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 33 +++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index a1999f3fe330..3e4ed081505c 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -331,8 +331,32 @@ ranges = <0x0 0x1e789000 0x1000>; lpc_bmc: lpc-bmc@0 { - compatible = "aspeed,ast2500-lpc-bmc"; + compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon"; reg = <0x0 0x80>; + reg-io-width = <4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x80>; + + kcs1: kcs1@0 { + compatible = "aspeed,ast2500-kcs-bmc"; + interrupts = <8>; + kcs_chan = <1>; + status = "disabled"; + }; + kcs2: kcs2@0 { + compatible = "aspeed,ast2500-kcs-bmc"; + interrupts = <8>; + kcs_chan = <2>; + status = "disabled"; + }; + kcs3: kcs3@0 { + compatible = "aspeed,ast2500-kcs-bmc"; + interrupts = <8>; + kcs_chan = <3>; + status = "disabled"; + }; }; lpc_host: lpc-host@80 { @@ -344,6 +368,13 @@ #size-cells = <1>; ranges = <0x0 0x80 0x1e0>; + kcs4: kcs4@0 { + compatible = "aspeed,ast2500-kcs-bmc"; + interrupts = <8>; + kcs_chan = <4>; + status = "disabled"; + }; + lpc_ctrl: lpc-ctrl@0 { compatible = "aspeed,ast2500-lpc-ctrl"; reg = <0x0 0x80>; From e7b66ba2db01997e8f75548389b93eec4db61059 Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Mon, 17 Dec 2018 12:04:04 -0800 Subject: [PATCH 135/506] ARM: dts: aspeed: tiogapass: Enable KCS Tiogapass uses two KCS channels. Signed-off-by: Vijay Khemka Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index f8e7b71af7e6..a4c7e205ca96 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -56,6 +56,18 @@ status = "okay"; }; +&kcs2 { + // BMC KCS channel 2 + status = "okay"; + kcs_addr = <0xca8>; +}; + +&kcs3 { + // BMC KCS channel 3 + status = "okay"; + kcs_addr = <0xca2>; +}; + &mac0 { status = "okay"; From 1a5ebcd4356d5354e001898595ce9c50f3e8d09f Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Mon, 17 Dec 2018 12:04:02 -0800 Subject: [PATCH 136/506] ARM: dts: aspeed: tiogapass: Add sensors Added ADC and other sensor devices present in the Facebook Tiogapass machine. Signed-off-by: Vijay Khemka Signed-off-by: Joel Stanley --- .../dts/aspeed-bmc-facebook-tiogapass.dts | 23 +++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index a4c7e205ca96..73e58a821613 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -21,6 +21,17 @@ memory@80000000 { reg = <0x80000000 0x20000000>; }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 7>; + }; }; &fmc { @@ -76,6 +87,10 @@ use-ncsi; }; +&adc { + status = "okay"; +}; + &i2c0 { status = "okay"; //Airmax Conn B, CPU0 PIROM, CPU1 PIROM @@ -134,6 +149,10 @@ &i2c8 { status = "okay"; + tmp421@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; //Mezz Sensor SMBus }; @@ -152,7 +171,7 @@ }; fan@1 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; }; }; From adbb78e1104a006275e0e8e37526f617bb2a3d91 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Thu, 10 Jan 2019 16:32:32 +0100 Subject: [PATCH 137/506] ARM: dts: r8a7778: Add HSCIF0/1 support Add HSCIF0/1 clocks and device nodes, based on Rev. 1.00 of the R-Car M1A datasheet. Signed-off-by: Ulrich Hecht [geert: Squashed two patches] [geert: Correct HSCIF1 module clock index] [geert: Correct reg properties for non-LPAE] Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 28 +++++++++++++++++++++++ include/dt-bindings/clock/r8a7778-clock.h | 2 ++ 2 files changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 05db0ccad7a6..10d996d2941f 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -367,6 +367,30 @@ status = "disabled"; }; + hscif0: serial@ffe48000 { + compatible = "renesas,hscif-r8a7778", + "renesas,rcar-gen1-hscif", "renesas,hscif"; + reg = <0xffe48000 96>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>, + <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + hscif1: serial@ffe49000 { + compatible = "renesas,hscif-r8a7778", + "renesas,rcar-gen1-hscif", "renesas,hscif"; + reg = <0xffe49000 96>; + interrupts = ; + clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>, + <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + mmcif: mmc@ffe4e000 { compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif"; reg = <0xffe4e000 0x100>; @@ -535,6 +559,8 @@ <&cpg_clocks R8A7778_CLK_P>, <&cpg_clocks R8A7778_CLK_P>, <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_S>, + <&cpg_clocks R8A7778_CLK_S>, <&cpg_clocks R8A7778_CLK_P>, <&cpg_clocks R8A7778_CLK_P>, <&cpg_clocks R8A7778_CLK_P>, @@ -551,6 +577,7 @@ R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5 + R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2 @@ -560,6 +587,7 @@ clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", + "hscif0", "hscif1", "tmu0", "tmu1", "tmu2", "ssi0", "ssi1", "ssi2", "ssi3", "sru", "hspi"; }; diff --git a/include/dt-bindings/clock/r8a7778-clock.h b/include/dt-bindings/clock/r8a7778-clock.h index f6b07c5399de..d0bff9ec5c66 100644 --- a/include/dt-bindings/clock/r8a7778-clock.h +++ b/include/dt-bindings/clock/r8a7778-clock.h @@ -30,6 +30,8 @@ #define R8A7778_CLK_SCIF3 23 #define R8A7778_CLK_SCIF4 22 #define R8A7778_CLK_SCIF5 21 +#define R8A7778_CLK_HSCIF0 19 +#define R8A7778_CLK_HSCIF1 18 #define R8A7778_CLK_TMU0 16 #define R8A7778_CLK_TMU1 15 #define R8A7778_CLK_TMU2 14 From 1a6e741177d0fb70993d605305b09f9cb3b54414 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Mon, 14 Jan 2019 12:05:31 +0000 Subject: [PATCH 138/506] arm64: dts: rockchip: Add DT for NanoPi M4 There are a number of subtle differences between the nanopi4 variants, and where they disagree, the common DTSI currently follows the details of NanoPi M4. In order to improve matters even more, let's add a separate DTS for the M4 to which we can start splitting things out appropriately. The third variant, NanoPi NEO4, is a lot closer to the M4 than either is to the larger T4, so arguably could get away with just sharing the M4 DT for now (plus I have neither of the smaller boards to actually test with). CC: Rob Herring CC: Mark Rutland Signed-off-by: Robin Murphy Reviewed-by: Rob Herring Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/arm/rockchip.yaml | 6 ++++-- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3399-nanopi-m4.dts | 18 ++++++++++++++++++ 3 files changed, 23 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 21d09a78869d..eb4d7f356543 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -87,9 +87,11 @@ properties: - const: firefly,roc-rk3399-pc - const: rockchip,rk3399 - - description: FriendlyElec NanoPC-T4 + - description: FriendlyElec NanoPi4 series boards items: - - const: friendlyarm,nanopc-t4 + - enum: + - friendlyarm,nanopc-t4 + - friendlyarm,nanopi-m4 - const: rockchip,rk3399 - description: GeekBuying GeekBox diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 899f4a75b058..1b28fa72ea0b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts new file mode 100644 index 000000000000..8d3f0ba29c72 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPi M4 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi M4"; + compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; +}; From c62ffaf5026d0b7633e62b2cea8450b5543c349a Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Mon, 14 Jan 2019 12:05:32 +0000 Subject: [PATCH 139/506] arm64: dts: rockchip: Refine nanopi4 differences The nanopi4 boards differ primarily in their power trees, with the main 5V and 3.3V rails having very different topologies on the smaller USB-C powered boards vs. the 12V-powered T4, as well as minor variation in other regulators related to various external connectors. Additionally, the recovery key is only present on the T4 - ADC_IN1 is simply pulled high and not exposed on the other boards - and the lowest common denominator for MMC speed is actually HS200 according to the vendor DTs. Signed-off-by: Robin Murphy Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-nanopc-t4.dts | 58 +++++++++++++++++++ .../boot/dts/rockchip/rk3399-nanopi-m4.dts | 48 +++++++++++++++ .../boot/dts/rockchip/rk3399-nanopi4.dtsi | 55 +----------------- 3 files changed, 107 insertions(+), 54 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts index af0bb2544709..623a03f2548a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts @@ -14,4 +14,62 @@ / { model = "FriendlyElec NanoPC-T4"; compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; + + vcc12v0_sys: vcc12v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "vcc12v0_sys"; + }; + + vcc5v0_host0: vcc5v0-host0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host0"; + vin-supply = <&vcc5v0_sys>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <18000>; + }; + }; +}; + +&sdhci { + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host0>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host0>; +}; + +&vcc5v0_sys { + vin-supply = <&vcc12v0_sys>; +}; + +&vcc3v3_sys { + vin-supply = <&vcc12v0_sys>; +}; + +&vbus_typec { + enable-active-high; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts index 8d3f0ba29c72..60358ab8c7df 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts @@ -15,4 +15,52 @@ / { model = "FriendlyElec NanoPi M4"; compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2: vcc5v0-usb2 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb2"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_core>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_usb2>; +}; + +&vbus_typec { + regulator-always-on; + vin-supply = <&vdd_5v>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index 3e8f1c10ba4f..9c723038d8f8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -28,21 +28,6 @@ #clock-cells = <0>; }; - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd_5v"; - }; - - vcc5v0_core: vcc5v0-core { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc5v0_core"; - vin-supply = <&vdd_5v>; - }; - vcc3v3_sys: vcc3v3-sys { compatible = "regulator-fixed"; regulator-always-on; @@ -50,7 +35,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc3v3_sys"; - vin-supply = <&vcc5v0_core>; }; vcc5v0_sys: vcc5v0-sys { @@ -63,22 +47,6 @@ vin-supply = <&vdd_5v>; }; - vcc5v0_usb1: vcc5v0-usb1 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc5v0_usb1"; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb2: vcc5v0-usb2 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc5v0_usb2"; - vin-supply = <&vcc5v0_sys>; - }; - /* switched by pmic_sleep */ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { compatible = "regulator-fixed"; @@ -105,27 +73,9 @@ vbus_typec: vbus-typec { compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - regulator-always-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-name = "vbus_typec"; - vin-supply = <&vdd_5v>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <18000>; - }; }; gpio-keys { @@ -590,8 +540,7 @@ &sdhci { bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; + mmc-hs200-1_8v; non-removable; status = "okay"; }; @@ -644,7 +593,6 @@ }; &u2phy0_host { - phy-supply = <&vcc5v0_usb1>; status = "okay"; }; @@ -657,7 +605,6 @@ }; &u2phy1_host { - phy-supply = <&vcc5v0_usb2>; status = "okay"; }; From 95658e21b1707ad7844f873db2fdaa295109a5a3 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Mon, 14 Jan 2019 12:05:33 +0000 Subject: [PATCH 140/506] arm64: dts: rockchip: Add NanoPC-T4 IR receiver In common with most Rockchip reference designs, NanoPC-T4 has a passive IR receiver connected to PWM3. In lieu of a specialised driver for PWM-based IR pulse measurement, running the pin as a GPIO with the basic driver works perfectly well. Signed-off-by: Robin Murphy Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts index 623a03f2548a..84433cf02be9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts @@ -45,6 +45,22 @@ press-threshold-microvolt = <18000>; }; }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx>; + }; +}; + +&pinctrl { + ir { + ir_rx: ir-rx { + /* external pullup to VCC3V3_SYS, despite being 1.8V :/ */ + rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; }; &sdhci { From 10f595eedc22a4ffcdeee23093fbb32a5a5b0226 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Mon, 14 Jan 2019 12:05:34 +0000 Subject: [PATCH 141/506] arm64: dts: rockchip: 'Fix' nanopi4 uSD card detect For whatever reason, the sdmmc_dectn function isn't working properly as-is, and microSD insertion and removal goes unnoticed. Using the pin as a GPIO interrupt instead is rather noisy without any debouncing, but is good enough to make it useful until someone feels inclined to figure out how the vendor kernel/firmware gets the dedicated function to work with no obvious difference in the pinmux/GRF configuration. Let's also take the opportunity to tweak the node name so that all related pins end up grouped together in the compiled DTB. Signed-off-by: Robin Murphy Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-nanopi4.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index 9c723038d8f8..2d304d2df62e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -501,17 +501,21 @@ }; }; - sd { - sdmmc0_pwr_h: sdmmc0-pwr-h { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - sdio-pwrseq { wifi_reg_on_h: wifi-reg_on-h { rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + sdmmc { + sdmmc0_det_l: sdmmc0-det-l { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pmu_io_domains { @@ -563,9 +567,10 @@ bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; disable-wp; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_cd &sdmmc_clk &sdmmc_cmd>; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; sd-uhs-sdr104; vmmc-supply = <&vcc3v0_sd>; vqmmc-supply = <&vcc_sdio>; From cf34287986d0b68596a010a0471854e41f4a42b6 Mon Sep 17 00:00:00 2001 From: Maxime Jourdan Date: Mon, 14 Jan 2019 17:22:29 +0100 Subject: [PATCH 142/506] arm64: dts: meson-gx: Add canvas provider node to the vpu Allows the vpu driver to optionally use a canvas provider node. Signed-off-by: Maxime Jourdan Acked-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 44c5c51ff1fa..9b0ac183ee0c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -510,6 +510,7 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + amlogic,canvas = <&canvas>; /* CVBS VDAC output port */ cvbs_vdac_port: port@0 { From a720349d2cb2e3d6d2f793b35ce7ffac38f9fcb8 Mon Sep 17 00:00:00 2001 From: Maxime Jourdan Date: Wed, 16 Jan 2019 13:40:29 +0100 Subject: [PATCH 143/506] dt-bindings: meson: add specific simplefb bindings Similar to simple-framebuffer-sunxi, we support different display pipelines that the firmware is free to choose from. This documents the "amlogic,simple-framebuffer" compatible and the "amlogic,pipeline" extension. Reviewed-by: Rob Herring Signed-off-by: Maxime Jourdan Signed-off-by: Kevin Hilman --- .../display/amlogic,simple-framebuffer.txt | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/amlogic,simple-framebuffer.txt diff --git a/Documentation/devicetree/bindings/display/amlogic,simple-framebuffer.txt b/Documentation/devicetree/bindings/display/amlogic,simple-framebuffer.txt new file mode 100644 index 000000000000..aaa6c24c8e70 --- /dev/null +++ b/Documentation/devicetree/bindings/display/amlogic,simple-framebuffer.txt @@ -0,0 +1,33 @@ +Meson specific Simple Framebuffer bindings + +This binding documents meson specific extensions to the simple-framebuffer +bindings. The meson simplefb u-boot code relies on the devicetree containing +pre-populated simplefb nodes. + +These extensions are intended so that u-boot can select the right node based +on which pipeline is being used. As such they are solely intended for +firmware / bootloader use, and the OS should ignore them. + +Required properties: +- compatible: "amlogic,simple-framebuffer", "simple-framebuffer" +- amlogic,pipeline, one of: + "vpu-cvbs" + "vpu-hdmi" + +Example: + +chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + simplefb_hdmi: framebuffer-hdmi { + compatible = "amlogic,simple-framebuffer", + "simple-framebuffer"; + amlogic,pipeline = "vpu-hdmi"; + clocks = <&clkc CLKID_HDMI_PCLK>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_GCLK_VENCI_INT0>; + power-domains = <&pwrc_vpu>; + }; +}; From 03b370357907c251c4ba19cbd113eebd907ca5c0 Mon Sep 17 00:00:00 2001 From: Maxime Jourdan Date: Wed, 16 Jan 2019 13:40:30 +0100 Subject: [PATCH 144/506] arm64: dts: meson-gx: add support for simplefb SimpleFB allows transferring a framebuffer from the firmware/bootloader to the kernel, while making sure the related clocks and power supplies stay enabled. Add nodes for CVBS and HDMI Simple Framebuffers. Signed-off-by: Maxime Jourdan Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 22 +++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 6 ++++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 6 ++++++ 3 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 9b0ac183ee0c..86a14f37f624 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -50,6 +50,28 @@ }; }; + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + simplefb_cvbs: framebuffer-cvbs { + compatible = "amlogic,simple-framebuffer", + "simple-framebuffer"; + amlogic,pipeline = "vpu-cvbs"; + power-domains = <&pwrc_vpu>; + status = "disabled"; + }; + + simplefb_hdmi: framebuffer-hdmi { + compatible = "amlogic,simple-framebuffer", + "simple-framebuffer"; + amlogic,pipeline = "vpu-hdmi"; + power-domains = <&pwrc_vpu>; + status = "disabled"; + }; + }; + cpus { #address-cells = <0x2>; #size-cells = <0x0>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index a7b883ced0a8..a60d3652beee 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -784,6 +784,12 @@ resets = <&reset RESET_SD_EMMC_C>; }; +&simplefb_hdmi { + clocks = <&clkc CLKID_HDMI_PCLK>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_GCLK_VENCI_INT0>; +}; + &spicc { clocks = <&clkc CLKID_SPICC>; clock-names = "core"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index d5c3d78aafeb..3093ae421b17 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -787,6 +787,12 @@ resets = <&reset RESET_SD_EMMC_C>; }; +&simplefb_hdmi { + clocks = <&clkc CLKID_HDMI_PCLK>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_GCLK_VENCI_INT0>; +}; + &spicc { clocks = <&clkc CLKID_SPICC>; clock-names = "core"; From 5ca872c530e5fd8ae24c999d4bc103bc1c8ac6af Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 16 Jan 2019 18:59:13 +0100 Subject: [PATCH 145/506] arm64: dts: meson: s400: enable sdr104 on sdio The bcm wifi/bt device on SDIO support SDR104 and it seems to work well following the recent mmc driver update, so enable this ultra high speed mode Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 2e1dcf1c26bf..0c98ca78c8b8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -464,7 +464,8 @@ bus-width = <4>; cap-sd-highspeed; - max-frequency = <100000000>; + sd-uhs-sdr104; + max-frequency = <200000000>; non-removable; disable-wp; From ec01fb69ac8034ad6e839b31f9df167a110f868b Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 16 Jan 2019 18:59:47 +0100 Subject: [PATCH 146/506] arm64: dts: meson: s400: fix emmc maximum rate Limiting the HS200 rate on the s400 was just a way to mask that the tuning setting were not correct. This seems to have been fixed with the recent MMC driver update. We can now use HS200 at full speed. Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 0c98ca78c8b8..75fe1a2c49d0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -488,9 +488,8 @@ pinctrl-names = "default", "clk-gate"; bus-width = <8>; - cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <180000000>; + max-frequency = <200000000>; non-removable; disable-wp; mmc-ddr-1_8v; From 9ab2d15ce1c392602a4ae062746b3d9ab5cf47ec Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 17 Jan 2019 11:02:34 +0100 Subject: [PATCH 147/506] arm64: dts: meson-axg: add efuse device Add efuse to the AXG family Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 781632bd60ed..f044473dc7d0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -111,6 +111,14 @@ compatible = "amlogic,meson-gxbb-sm"; }; + efuse: efuse { + compatible = "amlogic,meson-gxbb-efuse"; + clocks = <&clkc CLKID_EFUSE>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; From 055d15a88f66b096ca4df7cde83a80b80cd22dff Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Fri, 18 Jan 2019 11:48:15 +0100 Subject: [PATCH 148/506] ARM: dts: r8a7779: Add HSCIF0/1 device nodes Based on Rev. 1.00 of the R-Car H1 datasheet. Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 3bc133d9489c..3ff259207527 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -287,6 +287,32 @@ status = "disabled"; }; + hscif0: serial@ffe48000 { + compatible = "renesas,hscif-r8a7779", + "renesas,rcar-gen1-hscif", "renesas,hscif"; + reg = <0xffe48000 96>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>, + <&cpg_clocks R8A7779_CLK_S>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + hscif1: serial@ffe49000 { + compatible = "renesas,hscif-r8a7779", + "renesas,rcar-gen1-hscif", "renesas,hscif"; + reg = <0xffe49000 96>; + interrupts = ; + clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>, + <&cpg_clocks R8A7779_CLK_S>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + pfc: pin-controller@fffc0000 { compatible = "renesas,pfc-r8a7779"; reg = <0xfffc0000 0x23c>; From 890c506735864dfcd172ea4d57d4378bbe66a06c Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Fri, 18 Jan 2019 15:57:29 +0100 Subject: [PATCH 149/506] ARM: dts: sun4i: Add support for the C1 SRAM region with the SRAM controller This adds support for the C1 SRAM region (to be used with the SRAM controller driver) for the A10 platform. The region is shared between the Video Engine and the CPU. Signed-off-by: Paul Kocialkowski Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index a2fb473cbb9d..c3a74024ca0f 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -229,6 +229,19 @@ status = "disabled"; }; }; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; }; dma: dma-controller@1c02000 { From 5949bc5602ccd88161982e646432944eb318fa6e Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Fri, 18 Jan 2019 15:57:30 +0100 Subject: [PATCH 150/506] ARM: dts: sun4i-a10: Add Video Engine and reserved memory nodes This adds nodes for the Video Engine and the associated reserved memory for the A10. Up to 96 MiB of memory are dedicated to the CMA pool. The VPU can only map the first 256 MiB of DRAM, so the reserved memory pool has to be located in that area. Following Allwinner's decision in downstream software, the last 96 MiB of the first 256 MiB of RAM are reserved for this purpose. Signed-off-by: Paul Kocialkowski Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index c3a74024ca0f..73c3ac42095f 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -189,6 +189,21 @@ interrupts = <3>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ + default-pool { + compatible = "shared-dma-pool"; + size = <0x6000000>; + alloc-ranges = <0x4a000000 0x6000000>; + reusable; + linux,cma-default; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -412,6 +427,17 @@ }; }; + video-codec@1c0e000 { + compatible = "allwinner,sun4i-a10-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_VE>; + interrupts = <53>; + allwinner,sram = <&ve_sram 1>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c0f000 0x1000>; From 43d78e726a2b5fef0c0e0f07e2bed0faa4918d1b Mon Sep 17 00:00:00 2001 From: John Wang Date: Thu, 17 Jan 2019 17:32:42 +0800 Subject: [PATCH 151/506] ARM: dts: aspeed: Add Inspur on5263m5 BMC The Inspur on5263m5 is an Intel Xeon OCP server that uses the ASPEED AST2500 BMC. Signed-off-by: John Wang Reviewed-by: Andrew Jeffery [joel: Rework commit message] Signed-off-by: Joel Stanley --- .../boot/dts/aspeed-bmc-inspur-on5263m5.dts | 145 ++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts new file mode 100644 index 000000000000..2337ee23f5c4 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Inspur Corporation +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include + +/ { + model = "ON5263M5 BMC"; + compatible = "inspur,on5263m5-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "earlyprintk"; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + bmc_alive { + label = "bmc_alive"; + gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; + +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c6 { + status = "okay"; + + tmp421@4e { + compatible = "ti,tmp421"; + reg = <0x4e>; + }; + + tmp112@48 { + compatible = "ti,tmp112"; + reg = <0x48>; + }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + }; +}; + +&i2c7 { + status = "okay"; + + adm1278@11 { + compatible = "adi,adm1278"; + reg = <0x11>; + }; +}; + +&gfx { + status = "okay"; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; + }; +}; + +&adc { + status = "okay"; +}; From 3dada33d735b27646720d8fcb105097b40646add Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Mon, 21 Jan 2019 09:57:04 +0000 Subject: [PATCH 152/506] dt-bindings: Add vendor prefix for Catalyst Semiconductor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add vendor prefix "catalyst" for Catalyst Semiconductor which is already in use but undocumented. Signed-off-by: Martyn Welch Reviewed-by: Rob Herring Reviewed-by: Andreas Färber Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..a81de3134724 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -65,6 +65,7 @@ bticino Bticino International calxeda Calxeda capella Capella Microsystems, Inc cascoda Cascoda, Ltd. +catalyst Catalyst Semiconductor, Inc. cavium Cavium, Inc. cdns Cadence Design Systems Inc. cdtech CDTech(H.K.) Electronics Limited From 179cbdb8747ca551e57dc10271eb1f540499c8cf Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Wed, 16 Jan 2019 13:21:36 +0000 Subject: [PATCH 153/506] arm64: dts: imx8qxp: Fix MU4_INT number MU4_INT correct number is 180, while 179 is for MU3_INT. Fixes: 3d91ba65fecd ("arm64: dts: imx: add imx8qxp support") Reviewed-by: Fabio Estevam Reviewed-by: Dong Aisheng Signed-off-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index bb877cf25edc..4c3dd95ed488 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -350,7 +350,7 @@ lsio_mu4: mailbox@5d1f0000 { compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; reg = <0x5d1f0000 0x10000>; - interrupts = ; + interrupts = ; #mbox-cells = <0>; status = "disabled"; }; From fc71f69ceccf64cb198c0301d982e0a21c3181ae Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Mon, 21 Jan 2019 10:35:39 +0000 Subject: [PATCH 154/506] ARM: dts: mps2: use list instead of tuple for uart interrupts MPS2 UART requires dedicated interrupts for RX, TX and overflow, which obviously should be expressed as a list. Current form uses tuple and it has worked so far because NVIC has interrupt-cells equal to 1. Signed-off-by: Vladimir Murzin Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/mps2.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi index 23467390558d..96fb5a5cf4d3 100644 --- a/arch/arm/boot/dts/mps2.dtsi +++ b/arch/arm/boot/dts/mps2.dtsi @@ -171,7 +171,7 @@ uart0: serial@4000 { compatible = "arm,mps2-uart"; reg = <0x4000 0x1000>; - interrupts = <0 1 12>; + interrupts = <0>, <1>, <12>; clocks = <&sysclk>; status = "disabled"; }; @@ -179,7 +179,7 @@ uart1: serial@5000 { compatible = "arm,mps2-uart"; reg = <0x5000 0x1000>; - interrupts = <2 3 12>; + interrupts = <2>, <3>, <12>; clocks = <&sysclk>; status = "disabled"; }; @@ -187,7 +187,7 @@ uart2: serial@6000 { compatible = "arm,mps2-uart"; reg = <0x6000 0x1000>; - interrupts = <4 5 12>; + interrupts = <4>, <5>, <12>; clocks = <&sysclk>; status = "disabled"; }; From 01980aa7b0d7fde864899787510ddc01c1657c9a Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Tue, 22 Jan 2019 12:00:59 +0000 Subject: [PATCH 155/506] ARM: dts: vexpress: use list instead of tuple for mmci interrupts Vexpress motherboard MMCI requires dedicated interrupts for CMD and PIO, which obviously should be expressed as a list. Current form uses tuple and it works fine since interrupt-cells equal to 1. Reported-by: Vladimir Murzin Reviewed-by: Vladimir Murzin Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 2 +- arch/arm/boot/dts/vexpress-v2m.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index a9569d15de41..d3963e9eaf48 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -133,7 +133,7 @@ mmci@50000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x050000 0x1000>; - interrupts = <9 10>; + interrupts = <9>, <10>; cd-gpios = <&v2m_mmc_gpios 0 0>; wp-gpios = <&v2m_mmc_gpios 1 0>; max-frequency = <12000000>; diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index fd42e1194179..798c97aff7fa 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -133,7 +133,7 @@ mmci@5000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x05000 0x1000>; - interrupts = <9 10>; + interrupts = <9>, <10>; cd-gpios = <&v2m_mmc_gpios 0 0>; wp-gpios = <&v2m_mmc_gpios 1 0>; max-frequency = <12000000>; From 7eda14afb8843a0d5b6120b889ec8eec407b214d Mon Sep 17 00:00:00 2001 From: Kazuya Mizuguchi Date: Fri, 14 Dec 2018 16:58:44 +0100 Subject: [PATCH 156/506] arm64: dts: renesas: r8a77990: ebisu: Fix EthernetAVB phy mode to rgmii According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of August 24, 2018, the TX clock internal delay mode doesn't support on R-Car E3. This patch fixes EthernetAVB phy mode to rgmii. This is achieved by simply dropping the phy-mode property from r8a77990-ebisu.dts as the default property for this for r8a77990, as set in r8a77990.dtsi, is "rgmii". Signed-off-by: Kazuya Mizuguchi Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman Reviewed-by: Ulrich Hecht --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 24beb0e22cb0..8b66ee86e7bb 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -267,7 +267,6 @@ pinctrl-names = "default"; renesas,no-ether-link; phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; status = "okay"; phy0: ethernet-phy@0 { From c257628dcdcc2b0f40ccbc127554f18c272e7f2d Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:10:05 +0000 Subject: [PATCH 157/506] arm64: dts: renesas: Initial device tree for r8a774c0 Basic support for the RZ/G2E SoC (a.k.a. r8a774c0). Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 186 ++++++++++++++++++++++ 1 file changed, 186 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi new file mode 100644 index 000000000000..f425d0b3a31b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZ/G2E (R8A774C0) SoC + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a774c0"; + #address-cells = <2>; + #size-cells = <2>; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* 1 core only at this point */ + a53_0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA53: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A774C0_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a774c0-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a774c0-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a774c0-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a774c0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clocks - can be overridden by the board */ + usb3s0_clk: usb3s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; +}; From e2088cf8e6d5c5bf0b822b07fa9778d41894dee2 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:10:06 +0000 Subject: [PATCH 158/506] arm64: dts: renesas: r8a774c0: Add SYS-DMAC controller nodes Add sys-dmac[012] device nodes for the RZ/G2E SoC (a.k.a. r8a774c0). Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 102 ++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index f425d0b3a31b..7b3d247ca004 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -126,6 +126,108 @@ #power-domain-cells = <1>; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a774c0", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a774c0", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a774c0", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + }; + scif2: serial@e6e88000 { compatible = "renesas,scif-r8a774c0", "renesas,rcar-gen3-scif", "renesas,scif"; From 2660a6af690ebbb4f342944ec8ab7c1a2766672c Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:10:07 +0000 Subject: [PATCH 159/506] arm64: dts: renesas: r8a774c0: Add SCIF and HSCIF nodes Add the device nodes for all RZ/G2E SCIF and HSCIF serial ports, including clocks, power domains and DMAs. According to the HW user manual, SCIF[015] and HSCIF[012] are connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and HSCIF[34] are connected to SYS-DMAC0. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 171 ++++++++++++++++++++++ 1 file changed, 171 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 7b3d247ca004..872efa755532 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -126,6 +126,94 @@ #power-domain-cells = <1>; }; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a774c0", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a774c0", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a774c0", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a774c0", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a774c0", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a774c0", "renesas,rcar-dmac"; @@ -228,6 +316,40 @@ dma-channels = <16>; }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a774c0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a774c0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + scif2: serial@e6e88000 { compatible = "renesas,scif-r8a774c0", "renesas,rcar-gen3-scif", "renesas,scif"; @@ -242,6 +364,55 @@ status = "disabled"; }; + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a774c0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a774c0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a774c0", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; From 13fd6932045d1a5b3bbdfc1097f9065369e52e96 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:10:08 +0000 Subject: [PATCH 160/506] arm64: dts: renesas: r8a774c0: Add INTC-EX device node Add support for the Interrupt Controller for External Devices (INTC-EX) on RZ/G2E. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 872efa755532..895f407f7043 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -126,6 +126,22 @@ #power-domain-cells = <1>; }; + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a774c0", "renesas,rcar-gen3-hscif", From 788e55b66c13e8e77003e9226677e49eaaa9f751 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:10:09 +0000 Subject: [PATCH 161/506] arm64: dts: renesas: r8a774c0: Add PFC support Add PFC support to the RZ/G2E (a.k.a. r8a774c0) SoC specific device tree. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 895f407f7043..afb4751219fa 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -105,6 +105,11 @@ #size-cells = <2>; ranges; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a774c0"; + reg = <0 0xe6060000 0 0x508>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a774c0-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; From fccd45bd23c2643872dd96e52078ecc39ccfe424 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:10:10 +0000 Subject: [PATCH 162/506] arm64: dts: renesas: r8a774c0: Add GPIO device nodes Add GPIO device nodes to the DT of the r8a774c0 SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 105 ++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index afb4751219fa..f09a240acb15 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -105,6 +105,111 @@ #size-cells = <2>; ranges; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a774c0", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a774c0", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a774c0", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a774c0", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a774c0", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 11>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a774c0", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 20>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a774c0", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 906>; + }; + pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a774c0"; reg = <0 0xe6060000 0 0x508>; From 2f71109eef53e3396510afb724358be91e2eb5c9 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:10:11 +0000 Subject: [PATCH 163/506] arm64: dts: renesas: r8a774c0: Add Ethernet AVB node This patch adds the SoC specific part of the Ethernet AVB device tree node. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 45 +++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index f09a240acb15..ea405289bcf5 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -442,6 +442,51 @@ dma-channels = <16>; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a774c0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a774c0", "renesas,rcar-gen3-scif", "renesas,scif"; From 8d68821ced28391551b5e2014de4b1bf461b667e Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:10:12 +0000 Subject: [PATCH 164/506] arm64: dts: renesas: r8a774c0: Add watchdog support Add watchdog support to the RZ/G2E (a.k.a. R8A774C0) SoC specific device tree. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index ea405289bcf5..a51b6d37f0cb 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -105,6 +105,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a774c0-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a774c0", "renesas,rcar-gen3-gpio"; From 9b55a05ebfbe41bfb4c2aa98a81a46f2031e599f Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:10:13 +0000 Subject: [PATCH 165/506] arm64: dts: renesas: r8a774c0: Add secondary CA53 CPU core Add a device node for the second Cortex-A53 CPU core on the Renesas RZ/G2E (a.k.a r8a774c0) SoC, and adjust the interrupt delivery masks for the ARM Generic Interrupt Controller and Architectured Timer. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 25 +++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index a51b6d37f0cb..83db7c740481 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -48,7 +48,6 @@ #address-cells = <1>; #size-cells = <0>; - /* 1 core only at this point */ a53_0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; reg = <0>; @@ -58,6 +57,15 @@ enable-method = "psci"; }; + a53_1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <1>; + device_type = "cpu"; + power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + L2_CA53: cache-controller-0 { compatible = "cache"; power-domains = <&sysc R8A774C0_PD_CA53_SCU>; @@ -82,8 +90,9 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, <&a53_1>; }; psci { @@ -604,7 +613,7 @@ <0x0 0xf1040000 0 0x20000>, <0x0 0xf1060000 0 0x20000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -619,10 +628,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; /* External USB clocks - can be overridden by the board */ From 77223211f44db5b35541f4cc1fe48cdee21a85b2 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:24 +0000 Subject: [PATCH 166/506] arm64: dts: renesas: r8a774c0: Add SDHI nodes Add SDHI nodes to the DT of the r8a774c0 SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 83db7c740481..96a71e3f9fe4 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -603,6 +603,42 @@ status = "disabled"; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a774c0", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a774c0", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a774c0", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; From abf8cc35bf89d897442643269079431a370e9f48 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:25 +0000 Subject: [PATCH 167/506] arm64: dts: renesas: r8a774c0: Add I2C and IIC-DVFS support Add the I2C[0-7] and IIC Bus Interface for DVFS (IIC for DVFS) devices nodes to the r8a774c0 device tree. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 143 ++++++++++++++++++++++ 1 file changed, 143 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 96a71e3f9fe4..bf08aba0f4d6 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -271,6 +271,149 @@ resets = <&cpg 407>; }; + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774c0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774c0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774c0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774c0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774c0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774c0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774c0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c7: i2c@e6690000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774c0", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6690000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1003>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 1003>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a774c0"; + reg = <0 0xe60b0000 0 0x15>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a774c0", "renesas,rcar-gen3-hscif", From 6c7e02178e8fb75dc6114cb12be1ce65741502fb Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:26 +0000 Subject: [PATCH 168/506] arm64: dts: renesas: r8a774c0: Add IPMMU device nodes Add r8a774c0 IPMMU nodes. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 73 +++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index bf08aba0f4d6..042e26da08b2 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -604,6 +604,79 @@ dma-channels = <16>; }; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a774c0"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a774c0"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a774c0"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a774c0"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a774c0"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a774c0"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a774c0"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A774C0_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a774c0"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a774c0"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a774c0", "renesas,etheravb-rcar-gen3"; From 59c3a00d6d41f72d9993e3a33b6cf8a396efffc5 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:27 +0000 Subject: [PATCH 169/506] arm64: dts: renesas: r8a774c0: Add CAN nodes Add the device nodes for both RZ/G2E CAN channels. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 042e26da08b2..446cab189c10 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -722,6 +722,30 @@ status = "disabled"; }; + can0: can@e6c30000 { + compatible = "renesas,can-r8a774c0", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, <&can_clk>; + clock-names = "clkp1", "can_clk"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a774c0", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, <&can_clk>; + clock-names = "clkp1", "can_clk"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a774c0", "renesas,rcar-gen3-scif", "renesas,scif"; From 6e9dd34eb6b0ffb9e5ff7f18c58193737d24cb37 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:28 +0000 Subject: [PATCH 170/506] arm64: dts: renesas: r8a774c0: Add thermal support This patch adds the thermal device node and the thermal-zones node to the SoC specific dtsi for the RZ/G2E. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 446cab189c10..9532d2960f9c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -255,6 +255,18 @@ #power-domain-cells = <1>; }; + thermal: thermal@e6190000 { + compatible = "renesas,thermal-r8a774c0"; + reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; #interrupt-cells = <2>; @@ -902,6 +914,25 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, From 62c0056f1c3eb15d6f40c2b958e0e023d5845852 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:29 +0000 Subject: [PATCH 171/506] arm64: dts: renesas: r8a774c0: Add MSIOF nodes Add the device nodes for all MSIOF SPI controllers on RZ/G2E SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 62 +++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 9532d2960f9c..9bd66b1474d5 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -855,6 +855,68 @@ status = "disabled"; }; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a774c0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a774c0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a774c0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a774c0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a774c0", "renesas,rcar-gen3-sdhi"; From cf8f74d6587d96abf746041d4df1425715f69c85 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:30 +0000 Subject: [PATCH 172/506] arm64: dts: renesas: r8a774c0: Add audio support Add sound support for the RZ/G2E SoC (a.k.a. R8A774C0). This work is based on similar work done on the R8A77990 SoC by Yoshihiro Kaneko . Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 241 ++++++++++++++++++++++ 1 file changed, 241 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 9bd66b1474d5..35b27b81bcd4 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -917,6 +917,247 @@ status = "disabled"; }; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a774c0", + "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774C0_CLK_ZA2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma0 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma0 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma0 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma0 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma0 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma0 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma0 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma0 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma0 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma0 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma0 0x02>, + <&audma0 0x15>, <&audma0 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma0 0x04>, + <&audma0 0x49>, <&audma0 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma0 0x06>, + <&audma0 0x63>, <&audma0 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma0 0x08>, + <&audma0 0x6f>, <&audma0 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma0 0x0a>, + <&audma0 0x71>, <&audma0 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma0 0x0c>, + <&audma0 0x73>, <&audma0 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma0 0x0e>, + <&audma0 0x75>, <&audma0 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma0 0x10>, + <&audma0 0x79>, <&audma0 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma0 0x12>, + <&audma0 0x7b>, <&audma0 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma0 0x14>, + <&audma0 0x7d>, <&audma0 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a774c0", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a774c0", "renesas,rcar-gen3-sdhi"; From 47f638672385a76adb6c736425b4c69e4d04186c Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:31 +0000 Subject: [PATCH 173/506] arm64: dts: renesas: r8a774c0: Add PWM support Add PWM support to the RZ/G2E (a.k.a. R8A774C0) SoC specific device tree. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 70 +++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 35b27b81bcd4..d87652087dde 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -758,6 +758,76 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a774c0", "renesas,rcar-gen3-scif", "renesas,scif"; From 8ed3a6b223159df3eb52e85f59819ba1a1459940 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:32 +0000 Subject: [PATCH 174/506] arm64: dts: renesas: r8a774c0: Add display output support The RZ/G2E (a.k.a. R8A774C0) has one RGB output and two LVDS outputs connected to DU. This patch add support for DU, LVDS encoders, VSP and FCP. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 167 ++++++++++++++++++++++ 1 file changed, 167 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index d87652087dde..f3c4910e6585 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1281,6 +1281,173 @@ resets = <&cpg 408>; }; + vspb0: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 626>; + renesas,fcp = <&fcpvb0>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 607>; + iommus = <&ipmmu_vp0 5>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 631>; + renesas,fcp = <&fcpvi0>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 611>; + iommus = <&ipmmu_vp0 8>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x7000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 623>; + renesas,fcp = <&fcpvd0>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x7000>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 622>; + renesas,fcp = <&fcpvd1>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 602>; + iommus = <&ipmmu_vi0 9>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a774c0"; + reg = <0 0xfeb00000 0 0x80000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + vsps = <&vspd0 0 &vspd1 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + + port@2 { + reg = <2>; + du_out_lvds1: endpoint { + remote-endpoint = <&lvds1_in>; + }; + }; + }; + }; + + lvds0: lvds-encoder@feb90000 { + compatible = "renesas,r8a774c0-lvds"; + reg = <0 0xfeb90000 0 0x20>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + lvds1: lvds-encoder@feb90100 { + compatible = "renesas,r8a774c0-lvds"; + reg = <0 0xfeb90100 0 0x20>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds1_in: endpoint { + remote-endpoint = <&du_out_lvds1>; + }; + }; + + port@1 { + reg = <1>; + lvds1_out: endpoint { + }; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From 89893580cf561fd67a3f70ee812e02eac9966096 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:33 +0000 Subject: [PATCH 175/506] arm64: dts: renesas: r8a774c0: Add USB2.0 phy and host device nodes Add USB2.0 phy and host (EHCI/OHCI) device tree nodes to the RZ/G2E SoC dtsi. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 37 +++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index f3c4910e6585..0ab3aa66354c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1228,6 +1228,43 @@ dma-channels = <16>; }; + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a774c0", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + #phy-cells = <0>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a774c0", "renesas,rcar-gen3-sdhi"; From 19777736ced78c4ea9b171ff758f62e04915f005 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:34 +0000 Subject: [PATCH 176/506] arm64: dts: renesas: r8a774c0: Add USB-DMAC and HSUSB device nodes Add usb dmac and hsusb device nodes on RZ/G2E SoC dtsi. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 45 +++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 0ab3aa66354c..79cdaacc2c8c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -514,6 +514,51 @@ status = "disabled"; }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a774c0", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x200>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 704>, <&cpg 703>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a774c0-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a774c0-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a774c0", "renesas,rcar-dmac"; From 3a6addcaedecf2a8261c3491693be38b28a75444 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:35 +0000 Subject: [PATCH 177/506] arm64: dts: renesas: r8a774c0: Add USB3.0 device nodes Add usb3.0 host and function device nodes to the RZ/G2E SoC dtsi. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 79cdaacc2c8c..6491fddaa489 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1273,6 +1273,28 @@ dma-channels = <16>; }; + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a774c0", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a774c0-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + ohci0: usb@ee080000 { compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; From 3cdc999db97349bf8fde1c1816c3522b74d8d733 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:36 +0000 Subject: [PATCH 178/506] arm64: dts: renesas: r8a774c0: Connect RZ/G2E SYS-DMAC to IPMMU Hook up SYS-DMAC0, SYS-DMAC1, and SYS-DMAC2 to IPMMU-DS0 and IPMMU-DS1, according to what reported by the RZ/G2 User's manual. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 6491fddaa489..5186a1b4201b 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -591,6 +591,14 @@ resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; }; dmac1: dma-controller@e7300000 { @@ -625,6 +633,14 @@ resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, + <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, + <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, + <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, + <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; }; dmac2: dma-controller@e7310000 { @@ -659,6 +675,14 @@ resets = <&cpg 217>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, + <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, + <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, + <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, + <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; ipmmu_ds0: mmu@e6740000 { From 4035f91a3b421f70e6e7b1e90f89ac4efc7bb7a5 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:37 +0000 Subject: [PATCH 179/506] arm64: dts: renesas: r8a774c0: Connect RZ/G2E AVB to IPMMU Hook up the RZ/G2E AVB device to IPMMU-DS0 as stated by the RZ/G2 User's manual. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 5186a1b4201b..58d4c60c54c3 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -798,6 +798,7 @@ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From 52a20e64cce7f25727e6ca5de19424222bdd220a Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:38 +0000 Subject: [PATCH 180/506] arm64: dts: renesas: r8a774c0: Connect RZ/G2E Audio-DMAC to IPMMU Hook up the RZ/G2E Audio-DMAC device to IPMMU-MP as stated by the RZ/G2 User's manual. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 58d4c60c54c3..6247ebc22b2a 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1296,6 +1296,14 @@ resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, + <&ipmmu_mp 2>, <&ipmmu_mp 3>, + <&ipmmu_mp 4>, <&ipmmu_mp 5>, + <&ipmmu_mp 6>, <&ipmmu_mp 7>, + <&ipmmu_mp 8>, <&ipmmu_mp 9>, + <&ipmmu_mp 10>, <&ipmmu_mp 11>, + <&ipmmu_mp 12>, <&ipmmu_mp 13>, + <&ipmmu_mp 14>, <&ipmmu_mp 15>; }; xhci0: usb@ee000000 { From f0c2aa1664a2ea6d05ca58fd35767aa0c22dd97e Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:39 +0000 Subject: [PATCH 181/506] arm64: dts: renesas: r8a774c0: Add PCIe device node This patch adds PCI express channel 0 device tree node to the RZ/G2E (a.k.a. R8A774C0) SoC dtsi. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 6247ebc22b2a..c13c1827d5d9 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1418,6 +1418,33 @@ resets = <&cpg 408>; }; + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a774c0", + "renesas,pcie-rcar-gen3"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + vspb0: vsp@fe960000 { compatible = "renesas,vsp2"; reg = <0 0xfe960000 0 0x8000>; From e961ab42e034d4690ab4fd6a112b50209dec46ea Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 14 Dec 2018 09:37:40 +0000 Subject: [PATCH 182/506] arm64: dts: renesas: r8a774c0: Add VIN and CSI-2 device nodes Add device nodes for VIN4, VIN5 and CSI40 to RZ/G2E (a.k.a. R8A774C0) SoC specific device tree. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 88 +++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index c13c1827d5d9..3970aafeee12 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1057,6 +1057,62 @@ status = "disabled"; }; + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a774c0"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a774c0"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin5>; + }; + }; + }; + }; + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required @@ -1521,6 +1577,38 @@ iommus = <&ipmmu_vi0 9>; }; + csi40: csi2@feaa0000 { + compatible = "renesas,r8a774c0-csi2", + "renesas,rcar-gen3-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin4: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin4csi40>; + }; + csi40vin5: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin5csi40>; + }; + }; + }; + }; + du: display@feb00000 { compatible = "renesas,du-r8a774c0"; reg = <0 0xfeb00000 0 0x80000>; From 1a69a73c9b006ae72e06a5e637932bfe2fb7bc05 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 16 Jan 2019 18:37:45 +0000 Subject: [PATCH 183/506] dt-bindings: arm: renesas: Add si-linux cat87[45] boards This patch adds board cat874 (powered by the RZ/G2E) and board cat875 (that sits on top of cat874). Both boards are made by Silicon Linux. Signed-off-by: Fabrizio Castro Reviewed-by: Chris Paterson Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 5e9d4864a600..9e1e07b5192e 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -108,6 +108,14 @@ properties: - description: RZ/G2E (R8A774C0) items: + - enum: + - si-linux,cat874 # Silicon Linux RZ/G2E 96board platform (CAT874) + - const: renesas,r8a774c0 + + - items: + - enum: + - si-linux,cat875 # Silicon Linux sub board for CAT874 (CAT875) + - const: si-linux,cat874 - const: renesas,r8a774c0 - description: R-Car M1A (R8A77781) From 76c27054ebb90302eb819e7ae76f3a04ed70ae78 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 29 Nov 2018 11:58:00 +0100 Subject: [PATCH 184/506] ARM: dts: msm8660: Mark two GSBI blocks "disabled" The GSBI module complains: gsbi 16500000.gsbi: missing mode configuration gsbi: probe of 16500000.gsbi failed with error -22 gsbi 16600000.gsbi: missing mode configuration gsbi: probe of 16600000.gsbi failed with error -22 gsbi 19800000.gsbi: GSBI port protocol: 2 crci: 0 So we should mark these GSBIs as "disabled" in the SoC file by default. If boards appear that make use of them, we can simply set status = "ok" in the DTS for them. Signed-off-by: Linus Walleij Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8660.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 70698941f64c..9b1cf00d8ca3 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -133,6 +133,7 @@ #address-cells = <1>; #size-cells = <1>; ranges; + status = "disabled"; syscon-tcsr = <&tcsr>; @@ -167,6 +168,7 @@ #address-cells = <1>; #size-cells = <1>; ranges; + status = "disabled"; syscon-tcsr = <&tcsr>; From 57c23241be8490c9db5c1d8c4496e7f13f2236ae Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 29 Nov 2018 12:08:21 +0100 Subject: [PATCH 185/506] ARM: dts: msm8660: Fix up GIC IRQ flags All the GSBI blocks are marking their GIC IRQ lines as "IRQ_TYPE_NONE" but there is no such thing: all GIC IRQ lines have a trigger type. That yields the following warning from the GIC driver: WARNING: CPU: 0 PID: 1 at ../drivers/irqchip/irq-gic.c:1016 gic_irq_domain_translate+0xdc/0xe4 (...) Mark all of these IRQ_TYPE_LEVEL_HIGH as is common so this warning goes away. Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8660.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 9b1cf00d8ca3..e5da87036dbb 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -141,7 +141,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16540000 0x1000>, <0x16500000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -150,7 +150,7 @@ gsbi6_i2c: i2c@16580000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16580000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -176,7 +176,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16640000 0x1000>, <0x16600000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -185,7 +185,7 @@ gsbi7_i2c: i2c@16680000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16680000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -209,7 +209,7 @@ gsbi8_i2c: i2c@19880000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x19880000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -234,7 +234,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; - interrupts = <0 195 IRQ_TYPE_NONE>; + interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -243,7 +243,7 @@ gsbi12_i2c: i2c@19c80000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x19c80000 0x1000>; - interrupts = <0 196 IRQ_TYPE_NONE>; + interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; From ec4c6c57af576e10c70547b782db04eb3602f5f4 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Sun, 4 Nov 2018 16:50:34 -0500 Subject: [PATCH 186/506] ARM: dts: qcom: msm8974-hammerhead: add WiFi support This patch adds WiFi support to the LG Nexus 5 (hammerhead) phone. Signed-off-by: Jonathan Marek [masneyb@onstation.org: Enabled wlan_regulator_pin and wlan_sleep_clk_pin] Signed-off-by: Brian Masney Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 51444c53fc72..5cf9c7e20f2e 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -220,6 +220,20 @@ }; }; }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_pin>; + }; }; &soc { @@ -242,6 +256,20 @@ }; }; + sdhc2_pin_a: sdhc2-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + i2c3_pins: i2c3 { mux { pins = "gpio10", "gpio11"; @@ -283,6 +311,32 @@ pinctrl-0 = <&sdhc1_pin_a>; }; + sdhci@f98a4900 { + status = "ok"; + + max-frequency = <100000000>; + bus-width = <4>; + non-removable; + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a>; + + #address-cells = <1>; + #size-cells = <0>; + + bcrmf@1 { + compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + brcm,drive-strength = <10>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin>; + }; + }; + gpio-keys { compatible = "gpio-keys"; input-name = "gpio-keys"; @@ -371,6 +425,22 @@ bias-pull-up; power-source = ; }; + + wlan_sleep_clk_pin: wl-sleep-clk { + pins = "gpio16"; + function = "func2"; + + output-high; + power-source = ; + }; + + wlan_regulator_pin: wl-reg-active { + pins = "gpio17"; + function = "normal"; + + bias-disable; + power-source = ; + }; }; }; }; From cdd3d64d843a2a4c658a182b744bfefbd021d542 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Wed, 31 Oct 2018 20:11:48 -0400 Subject: [PATCH 187/506] ARM: dts: qcom: msm8974: add gpio-ranges This adds the gpio-ranges property to pm8941_gpios so that the GPIO pins are initialized by the GPIO framework and not pinctrl. This fixes a circular dependency so GPIO hogging can be used on this board. Signed-off-by: Brian Masney Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-pm8941.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index 2515c5c217ac..9a91b758f7aa 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -63,6 +63,7 @@ compatible = "qcom,pm8941-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8941_gpios 0 0 36>; #gpio-cells = <2>; interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, <0 0xc1 0 IRQ_TYPE_NONE>, From fb143fcbb9ad361004f2818e9dcb52b2556bfec1 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Wed, 31 Oct 2018 20:11:49 -0400 Subject: [PATCH 188/506] ARM: dts: qcom: msm8974-hammerhead: add USB OTG support Add the device tree bindings for USB OTG support. Driver was tested using on a LG Nexus 5 (hammerhead) phone. This patch is based on work from Jonathan Marek and from the other msm8974 devices. Signed-off-by: Brian Masney Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 60 +++++++++++++++++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 11 ++++ 2 files changed, 71 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 5cf9c7e20f2e..b3b04736a159 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -270,6 +270,16 @@ }; }; + i2c1_pins: i2c1 { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + + drive-strength = <2>; + bias-disable; + }; + }; + i2c3_pins: i2c3 { mux { pins = "gpio10", "gpio11"; @@ -396,6 +406,24 @@ }; }; + i2c@f9923000 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; + qcom,src-freq = <50000000>; + + charger: bq24192@6b { + compatible = "ti,bq24192"; + reg = <0x6b>; + interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>; + + omit-battery-class; + + usb_otg_vbus: usb-otg-vbus { }; + }; + }; + i2c@f9925000 { status = "ok"; pinctrl-names = "default"; @@ -413,6 +441,31 @@ amstaos,proximity-diodes = <0>; }; }; + + usb@f9a55000 { + status = "ok"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + + extcon = <&charger>, <&usb_id>; + vbus-supply = <&usb_otg_vbus>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "ok"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; + }; }; &spmi_bus { @@ -441,6 +494,13 @@ bias-disable; power-source = ; }; + + otg { + gpio-hog; + gpios = <35 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "otg-gpio"; + }; }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index ca266a5f021d..05b86f21d41b 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -706,6 +706,17 @@ interrupts = ; }; + i2c@f9923000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9923000 0x1000>; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@f9924000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; From 40122db87778970c96062c9f49b42cdf6809bf94 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 18 Dec 2018 21:42:04 +0100 Subject: [PATCH 189/506] ARM: dts: ipq4019: Remove skeleton.dtsi The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 2d56008d8d6b..19635f91e2c4 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -13,12 +13,14 @@ /dts-v1/; -#include "skeleton.dtsi" #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; + model = "Qualcomm Technologies, Inc. IPQ4019"; compatible = "qcom,ipq4019"; interrupt-parent = <&intc>; From 173c3b3ca2130af4d69b1b25d95c52709fbd4a2f Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Tue, 18 Dec 2018 12:02:14 +0000 Subject: [PATCH 190/506] arm64: dts: renesas: r8a774a1: Fix hsusb reg size HS-USB has registers outside the currently specified memory area, therefore change the definition accordingly. Fixes: ed898d4fc19d ("arm64: dts: renesas: r8a774a1: Add USB-DMAC and HSUSB device nodes") Signed-off-by: Fabrizio Castro Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 20745a8528c5..46a8fd20108f 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -599,7 +599,7 @@ hsusb: usb@e6590000 { compatible = "renesas,usbhs-r8a774a1", "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x100>; + reg = <0 0xe6590000 0 0x200>; interrupts = ; clocks = <&cpg CPG_MOD 704>; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, From 003233351d4411caf993267f407b5c0a0ae76dd3 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 17 Dec 2018 13:40:53 +0100 Subject: [PATCH 191/506] arm64: dts: renesas: r8a77990: sort pciec0 node within soc node Move the pciec0 node so that sub-nodes of the soc node are sorted by bus address. This change has no run-time affect. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 54 +++++++++++------------ 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index b2f606e286ce..bdc7f7d39820 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1526,6 +1526,33 @@ resets = <&cpg 408>; }; + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a77990", + "renesas,pcie-rcar-gen3"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + vspb0: vsp@fe960000 { compatible = "renesas,vsp2"; reg = <0 0xfe960000 0 0x8000>; @@ -1724,33 +1751,6 @@ }; }; - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a77990", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 - 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 - 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 - 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From d5d7134fd49e6f5382432b9fcfbf68fa6556b04c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 Jan 2019 15:53:19 +0100 Subject: [PATCH 192/506] arm64: dts: renesas: r8a77990: Sort i2c nodes within soc node Move the i2c nodes so that sub-nodes of the soc node are sorted by bus address. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 136 +++++++++++----------- 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index bdc7f7d39820..84bbe70cb0ab 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -240,6 +240,74 @@ resets = <&cpg 906>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77990"; + reg = <0 0xe6060000 0 0x508>; + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a77990"; + reg = <0 0xe60b0000 0 0x15>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77990-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77990-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77990-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + thermal: thermal@e6190000 { + compatible = "renesas,thermal-r8a77990"; + reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a77990", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; @@ -369,74 +437,6 @@ status = "disabled"; }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77990"; - reg = <0 0xe6060000 0 0x508>; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a77990"; - reg = <0 0xe60b0000 0 0x15>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77990-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77990-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77990-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - thermal: thermal@e6190000 { - compatible = "renesas,thermal-r8a77990"; - reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77990", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a77990", "renesas,rcar-gen3-hscif", From 2e0e5b1685b708297b8ace867eacb0d692a2b7cf Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 3 Dec 2018 16:12:42 +0100 Subject: [PATCH 193/506] arm64: dts: renesas: r8a7796: salvator-xs: Convert to new LVDS DT bindings As of commit 6d2ca85279becdff ("dt-bindings: display: renesas: Deprecate LVDS support in the DU bindings"), the internal LVDS encoder has DT bindings separate from the DU. The device trees for all R-Car H3 and M3-W development boards were ported over to the new model, but Salvator-XS boards equipped with an R-Car M3-W SoC were forgotten. Fixes: 58e8ed2ee9abe718 ("arm64: dts: renesas: Convert to new LVDS DT bindings") Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts index 8860be65342e..31f12059355e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts @@ -29,11 +29,10 @@ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 727>, <&versaclock6 1>, <&x21_clk>, <&versaclock6 2>; - clock-names = "du.0", "du.1", "du.2", "lvds.0", + clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; From 5d3b226ace6d8d6f1a9fecbfb21e7e743a88f33c Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 7 Jan 2019 12:40:17 +0900 Subject: [PATCH 194/506] arm64: dts: renesas: ulcb: use audio-graph-card ULCB can use daughter board which is called as KingFisher. It has extra sound interface, thus we want to use it. But, basically, ALSA SoC can't use Multiple sound card with single CPU sound interface (= SSI). Thus we need to use Single Sound Card with multiple DAI interface. To be easy to expand ULCB sound card on KingFisher, it is better to use multi-dai-link style sound card on ULCB sound DT. Now, "simple-audio-card" / "audio-graph-card" both can support multi-dai-link style, but HDMI sound support (which is not yet supported on ULCB) needs "audio-graph-card". Using audio-graph-card is better selection. This patch exchange current sound card to use it. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 39 +++++++++++++++------------ 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index de694fdae067..8c6c45863ac8 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -83,20 +83,11 @@ regulator-always-on; }; - rsnd_ak4613: sound { - compatible = "simple-audio-card"; + sound_card: sound { + compatible = "audio-graph-card"; + label = "rcar-sound"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcpu>; - simple-audio-card,frame-master = <&sndcpu>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4613>; - }; + dais = <&rsnd_port0>; }; vcc_sdhi0: regulator-vcc-sdhi0 { @@ -211,6 +202,12 @@ asahi-kasei,out4-single-end; asahi-kasei,out5-single-end; asahi-kasei,out6-single-end; + + port { + ak4613_endpoint: endpoint { + remote-endpoint = <&rsnd_for_ak4613>; + }; + }; }; cs2000: clk-multiplier@4f { @@ -384,10 +381,18 @@ <&audio_clk_c>, <&cpg CPG_CORE CPG_AUDIO_CLK_I>; - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src0 &dvc0>; - capture = <&ssi1 &src1 &dvc1>; + ports { + rsnd_port0: port { + rsnd_for_ak4613: endpoint { + remote-endpoint = <&ak4613_endpoint>; + + dai-format = "left_j"; + bitclock-master = <&rsnd_for_ak4613>; + frame-master = <&rsnd_for_ak4613>; + + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; + }; }; }; }; From c693b2101c9f84af65b128e6f834ef1ccf99ca23 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 7 Jan 2019 12:40:28 +0900 Subject: [PATCH 195/506] arm64: dts: renesas: ulcb: add HDMI sound support This patch adds missing ULCB HDMI sound support. To use sound card, HDMI video is mandatory. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 35 +++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 8c6c45863ac8..a3878fb3c3f1 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -6,6 +6,14 @@ * Copyright (C) 2016 Cogent Embedded, Inc. */ +/* + * SSI-AK4613 + * aplay -D plughw:0,0 xxx.wav + * arecord -D plughw:0,0 xxx.wav + * SSI-HDMI + * aplay -D plughw:0,1 xxx.wav + */ + #include #include @@ -87,7 +95,9 @@ compatible = "audio-graph-card"; label = "rcar-sound"; - dais = <&rsnd_port0>; + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ + >; }; vcc_sdhi0: regulator-vcc-sdhi0 { @@ -173,6 +183,12 @@ remote-endpoint = <&hdmi0_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_for_hdmi>; + }; + }; }; }; @@ -382,7 +398,10 @@ <&cpg CPG_CORE CPG_AUDIO_CLK_I>; ports { - rsnd_port0: port { + #address-cells = <1>; + #size-cells = <0>; + rsnd_port0: port@0 { + reg = <0>; rsnd_for_ak4613: endpoint { remote-endpoint = <&ak4613_endpoint>; @@ -394,6 +413,18 @@ capture = <&ssi1 &src1 &dvc1>; }; }; + rsnd_port1: port@1 { + reg = <1>; + rsnd_for_hdmi: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_for_hdmi>; + frame-master = <&rsnd_for_hdmi>; + + playback = <&ssi2>; + }; + }; }; }; From 80c07701d5918928cb27370e4602e57f2a613515 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 7 Jan 2019 12:40:51 +0900 Subject: [PATCH 196/506] arm64: dts: renesas: ulcb-kf: add pcm3168 sound codec KingFisher has pcm3168 sound codec. This patch enables it. Because pcm3168 can't handle symmetric channel on playback/ capture, we need to handle it as different DAI. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 138 +++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 1b316d79df88..7a09576b3112 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -6,11 +6,38 @@ * Copyright (C) 2017 Cogent Embedded, Inc. */ +/* + * SSI-PCM3168A + * aplay -D plughw:0,2 xxx.wav + * arecord -D plughw:0,3 xxx.wav + */ + / { aliases { serial1 = &hscif0; serial2 = &scif1; }; + + clksndsel: clksndsel { + #clock-cells = <0>; + compatible = "gpio-mux-clock"; + clocks = <&cs2000>, <&audio_clk_a>; /* clk8snd, clksnd */ + select-gpios = <&gpio_exp_75 13 GPIO_ACTIVE_HIGH>; + }; + + snd_3p3v: regulator-snd_3p3v { + compatible = "regulator-fixed"; + regulator-name = "snd-3.3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + snd_vcc5v: regulator-snd_vcc5v { + compatible = "regulator-fixed"; + regulator-name = "snd-vcc5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; }; &can0 { @@ -44,6 +71,7 @@ }; &i2c2 { + /* U11 */ gpio_exp_74: gpio@74 { compatible = "ti,tca9539"; reg = <0x74>; @@ -53,6 +81,13 @@ interrupt-parent = <&gpio6>; interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + audio_out_off { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; /* P00 */ + output-high; + line-name = "Audio_Out_OFF"; + }; + hub_pwen { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; @@ -80,8 +115,16 @@ output-high; line-name = "OTG EXTLPn"; }; + + snd_rst { + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; /* P17 */ + output-high; + line-name = "SND_RST"; + }; }; + /* U5 */ gpio_exp_75: gpio@75 { compatible = "ti,tca9539"; reg = <0x75>; @@ -98,6 +141,48 @@ #size-cells = <0>; reg = <0x71>; reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + + /* Audio_SDA, Audio_SCL */ + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + pcm3168a: audio-codec@44 { + #sound-dai-cells = <0>; + compatible = "ti,pcm3168a"; + reg = <0x44>; + clocks = <&clksndsel>; + clock-names = "scki"; + + VDD1-supply = <&snd_3p3v>; + VDD2-supply = <&snd_3p3v>; + VCCAD1-supply = <&snd_vcc5v>; + VCCAD2-supply = <&snd_vcc5v>; + VCCDA1-supply = <&snd_vcc5v>; + VCCDA2-supply = <&snd_vcc5v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + mclk-fs = <512>; + port@0 { + reg = <0>; + pcm3168a_endpoint_p: endpoint { + remote-endpoint = <&rsnd_for_pcm3168a_play>; + clocks = <&clksndsel>; + }; + }; + port@1 { + reg = <1>; + pcm3168a_endpoint_c: endpoint { + remote-endpoint = <&rsnd_for_pcm3168a_capture>; + clocks = <&clksndsel>; + }; + }; + }; + }; + }; }; }; @@ -173,6 +258,11 @@ groups = "usb0"; function = "usb0"; }; + + sound_pcm_pins: sound-pcm { + groups = "ssi349_ctrl", "ssi3_data", "ssi4_data"; + function = "ssi"; + }; }; &scif1 { @@ -193,3 +283,51 @@ &xhci0 { status = "okay"; }; + +&sound_card { + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ + &rsnd_port2 /* pcm3168a playback */ + &rsnd_port3 /* pcm3168a capture */ + >; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins + &sound_clk_pins + &sound_pcm_pins>; + + ports { + /* rsnd_port0/1 are on salvator-common */ + rsnd_port2: port@2 { + reg = <2>; + rsnd_for_pcm3168a_play: endpoint { + remote-endpoint = <&pcm3168a_endpoint_p>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_for_pcm3168a_play>; + frame-master = <&rsnd_for_pcm3168a_play>; + dai-tdm-slot-num = <8>; + + playback = <&ssi3>; + }; + }; + rsnd_port3: port@3 { + reg = <3>; + rsnd_for_pcm3168a_capture: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_for_pcm3168a_capture>; + frame-master = <&rsnd_for_pcm3168a_capture>; + dai-tdm-slot-num = <6>; + + capture = <&ssi4>; + }; + }; + }; +}; + +&ssi4 { + shared-pin; +}; From 0ec8e0a879b8d7eacbfbed9a7face8f97f9493a8 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 7 Jan 2019 12:41:01 +0900 Subject: [PATCH 197/506] arm64: dts: renesas: r8a7795: remove BUSIF0 settings from rcar_sound,ssi Before, BUSIF which is needed for DMA transfer was automatically handled via SSI, but it cared BUSIF0 only. Now, rsnd driver can handle BUSIF0-7 (= for Gen3) BUSIF0-3 (= for Gen2) via SSIU, and it is keeping compatibility. Thus, BUSIF0 settings via SSI had been kept to avoid git merge timing issue / git bisect issue, but it is no longer needed. This patch removes it. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 40 ++++++++++++------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index af9605d5db27..a81ed2ba63e7 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -2174,53 +2174,53 @@ rcar_sound,ssi { ssi0: ssi-0 { interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x01>, <&audma1 0x02>; + dma-names = "rx", "tx"; }; ssi1: ssi-1 { interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x03>, <&audma1 0x04>; + dma-names = "rx", "tx"; }; ssi2: ssi-2 { interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x05>, <&audma1 0x06>; + dma-names = "rx", "tx"; }; ssi3: ssi-3 { interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x07>, <&audma1 0x08>; + dma-names = "rx", "tx"; }; ssi4: ssi-4 { interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x09>, <&audma1 0x0a>; + dma-names = "rx", "tx"; }; ssi5: ssi-5 { interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x0b>, <&audma1 0x0c>; + dma-names = "rx", "tx"; }; ssi6: ssi-6 { interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x0d>, <&audma1 0x0e>; + dma-names = "rx", "tx"; }; ssi7: ssi-7 { interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x0f>, <&audma1 0x10>; + dma-names = "rx", "tx"; }; ssi8: ssi-8 { interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x11>, <&audma1 0x12>; + dma-names = "rx", "tx"; }; ssi9: ssi-9 { interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x13>, <&audma1 0x14>; + dma-names = "rx", "tx"; }; }; }; From 10bd03fa896ee5e25fa3548a3d1112b9beb76943 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 7 Jan 2019 12:41:10 +0900 Subject: [PATCH 198/506] arm64: dts: renesas: r8a7796: remove BUSIF0 settings from rcar_sound,ssi Before, BUSIF which is needed for DMA transfer was automatically handled via SSI, but it cared BUSIF0 only. Now, rsnd driver can handle BUSIF0-7 (= for Gen3) BUSIF0-3 (= for Gen2) via SSIU, and it is keeping compatibility. Thus, BUSIF0 settings via SSI had been kept to avoid git merge timing issue / git bisect issue, but it is no longer needed. This patch removes it. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 40 ++++++++++++------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index afedbf5728ec..3a9f8c7081ca 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -2110,53 +2110,53 @@ rcar_sound,ssi { ssi0: ssi-0 { interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x01>, <&audma1 0x02>; + dma-names = "rx", "tx"; }; ssi1: ssi-1 { interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x03>, <&audma1 0x04>; + dma-names = "rx", "tx"; }; ssi2: ssi-2 { interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x05>, <&audma1 0x06>; + dma-names = "rx", "tx"; }; ssi3: ssi-3 { interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x07>, <&audma1 0x08>; + dma-names = "rx", "tx"; }; ssi4: ssi-4 { interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x09>, <&audma1 0x0a>; + dma-names = "rx", "tx"; }; ssi5: ssi-5 { interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x0b>, <&audma1 0x0c>; + dma-names = "rx", "tx"; }; ssi6: ssi-6 { interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x0d>, <&audma1 0x0e>; + dma-names = "rx", "tx"; }; ssi7: ssi-7 { interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x0f>, <&audma1 0x10>; + dma-names = "rx", "tx"; }; ssi8: ssi-8 { interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x11>, <&audma1 0x12>; + dma-names = "rx", "tx"; }; ssi9: ssi-9 { interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x13>, <&audma1 0x14>; + dma-names = "rx", "tx"; }; }; From 868a49d6f9d915a16f4fa223083eab6fbcbefcbf Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 7 Jan 2019 12:41:28 +0900 Subject: [PATCH 199/506] arm64: dts: renesas: r8a77990-ebisu: use simple-audio-card Current Ebisu board is using simple-scu-audio-card which is used for Sampling Rate Convert, or MIXer, etc. But, Ebisu is not using such feature. Then, simple-audio-card is very enough. This patch fixup it. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 8b66ee86e7bb..e0590c0af4c4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -169,16 +169,13 @@ }; rsnd_ak4613: sound { - compatible = "simple-scu-audio-card"; + compatible = "simple-audio-card"; simple-audio-card,name = "rsnd-ak4613"; simple-audio-card,format = "left_j"; simple-audio-card,bitclock-master = <&sndcpu>; simple-audio-card,frame-master = <&sndcpu>; - simple-audio-card,prefix = "ak4613"; - simple-audio-card,routing = "ak4613 Playback", "DAI0 Playback", - "DAI0 Capture", "ak4613 Capture"; sndcpu: simple-audio-card,cpu { sound-dai = <&rcar_sound>; }; From d5e5790c6ff0b6825f6d8b4baf67fa13810ce4fc Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 8 Jan 2019 22:56:50 +0300 Subject: [PATCH 200/506] arm64: dts: renesas: v3msk: specify EtherAVB PHY IRQ Specify EtherAVB PHY IRQ in the V3M Starter Kit board's device tree, now that we have the GPIO support (previously phylib had to resort to polling). Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 0dbcb4cccc18..15cc9fed2e16 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -108,6 +108,8 @@ phy0: ethernet-phy@0 { rxc-skew-ps = <1500>; reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; }; }; From 12105cec654cf90648f65f7dc90d1be982d326eb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 9 Jan 2019 15:00:45 +0100 Subject: [PATCH 201/506] arm64: dts: renesas: r8a77990: ebisu: Fix backlight regulator numbering There are two regulator1 nodes in the Ebisu DTS right now, one 3.3V for the eMMC and one 12V for the backlight. This causes one to be overwritten by the other, ultimatelly resulting in inoperable eMMC, which depends on the former. Fix this by renumbering the backlight regulator to regulator2. Signed-off-by: Marek Vasut Reported-by: Simon Horman Fixes: 9d16c4a10e07 ("arm64: dts: renesas: r8a77990: ebisu: Add backlight") Reviewed-by: Geert Uytterhoeven Tested-by: Simon Horman Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index e0590c0af4c4..89383aa35d65 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -191,7 +191,7 @@ clock-frequency = <24576000>; }; - reg_12p0v: regulator1 { + reg_12p0v: regulator2 { compatible = "regulator-fixed"; regulator-name = "D12.0V"; regulator-min-microvolt = <12000000>; From d9fd4e5814079ba4a2111d7d792a24bf8f747500 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 10 Jan 2019 14:39:14 +0100 Subject: [PATCH 202/506] arm64: dts: renesas: r8a774c0: Enable DMA for SCIF2 SCIF2 on RZ/G2E can be used with both DMAC1 and DMAC2. Fixes: 1b24f9e8ea3ff95f ("arm64: dts: renesas: r8a774c0: Add SCIF and HSCIF nodes") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 3970aafeee12..f2e390f7f1d5 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -941,6 +941,9 @@ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 310>; status = "disabled"; From a99de47921565c233092b0d3c4652b3a10e715ec Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 10 Jan 2019 14:39:17 +0100 Subject: [PATCH 203/506] arm64: dts: renesas: r8a77990: Enable DMA for SCIF2 SCIF2 on R-Car E3 can be used with both DMAC1 and DMAC2. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 84bbe70cb0ab..786178cf1ffd 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -993,7 +993,9 @@ <&cpg CPG_CORE R8A77990_CLK_S3D1C>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 310>; status = "disabled"; From 3e279a1d44d73aea9ce428ae68e76bf85117031a Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 18 Jan 2019 13:25:36 +0100 Subject: [PATCH 204/506] arm64: dts: renesas: r8a77990: ebisu: Enable HS400 of SDHI3 Enable HS400 of SDHI3 using the corresponding DT property. No further changes are required. Signed-off-by: Simon Horman Tested-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 89383aa35d65..144c0820cf60 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -695,6 +695,7 @@ vmmc-supply = <®_3p3v>; vqmmc-supply = <®_1p8v>; mmc-hs200-1_8v; + mmc-hs400-1_8v; bus-width = <8>; non-removable; status = "okay"; From d828266bb19a901c14b9d5518043f3582629938f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 16 Jan 2019 18:37:46 +0000 Subject: [PATCH 205/506] arm64: dts: renesas: Add Si-Linux CAT874 board support Basic support for the Si-Linux board based on RZ/G2E: - Memory, - Main crystal, - Serial console Signed-off-by: Biju Das Signed-off-by: Fabrizio Castro Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../boot/dts/renesas/r8a774c0-cat874.dts | 37 +++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index a8ce6594342d..11997d752e57 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts new file mode 100644 index 000000000000..6eababc93275 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874) + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774c0.dtsi" + +/ { + model = "Silicon Linux RZ/G2E 96board platform (CAT874)"; + compatible = "si-linux,cat874", "renesas,r8a774c0"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; +}; + +&extal_clk { + clock-frequency = <48000000>; +}; + +&scif2 { + status = "okay"; +}; From 4e8776657dd92854d063658b42440673edd995ae Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 16 Jan 2019 18:37:47 +0000 Subject: [PATCH 206/506] arm64: dts: renesas: Add Si-Linux EK874 board support The EK874 development kit from Silicon Linux is made of CAT874 (the main board) and CAT875 (the sub board that goes on top of CAT874). Signed-off-by: Biju Das Signed-off-by: Fabrizio Castro Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/Makefile | 2 +- arch/arm64/boot/dts/renesas/cat875.dtsi | 10 ++++++++++ arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts | 14 ++++++++++++++ 3 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/renesas/cat875.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 11997d752e57..6cde526547e4 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb +dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi new file mode 100644 index 000000000000..a41d0d81f649 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/cat875.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875) + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ + +/ { + model = "Silicon Linux sub board for CAT874 (CAT875)"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts new file mode 100644 index 000000000000..e7b6619ab224 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874) + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ + +#include "r8a774c0-cat874.dts" +#include "cat875.dtsi" + +/ { + model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)"; + compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0"; +}; From 4cf1f6cec1e99410b5cdc0b865b93bebf68b3fdb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 16 Jan 2019 18:37:48 +0000 Subject: [PATCH 207/506] arm64: dts: renesas: r8a774c0-cat874: Add pincontrol support to scif2 This patch adds pincontrol support to scif2. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts index 6eababc93275..c545ce5320c7 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts @@ -32,6 +32,16 @@ clock-frequency = <48000000>; }; +&pfc { + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; +}; + &scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + status = "okay"; }; From a102b93eafef0994f1a96e9683d1e3d692a6bb48 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 16 Jan 2019 18:37:49 +0000 Subject: [PATCH 208/506] arm64: dts: renesas: r8a774c0-cat874: Add uSD support This patch adds uSD card support. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Chris Paterson Signed-off-by: Simon Horman --- .../boot/dts/renesas/r8a774c0-cat874.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts index c545ce5320c7..477a56b3273c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "r8a774c0.dtsi" +#include / { model = "Silicon Linux RZ/G2E 96board platform (CAT874)"; @@ -26,6 +27,29 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x78000000>; }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; }; &extal_clk { @@ -37,6 +61,18 @@ groups = "scif2_data_a"; function = "scif2"; }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; }; &scif2 { @@ -45,3 +81,17 @@ status = "okay"; }; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; From 6b170cd3ed02949f33fb8b6898b3b31ae5e87716 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 16 Jan 2019 18:37:50 +0000 Subject: [PATCH 209/506] arm64: dts: renesas: cat875: Add ethernet support This patch adds ethernet support to the sub board. Signed-off-by: Biju Das Signed-off-by: Fabrizio Castro Reviewed-by: Chris Paterson Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/cat875.dtsi | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi index a41d0d81f649..805ffa7fb67b 100644 --- a/arch/arm64/boot/dts/renesas/cat875.dtsi +++ b/arch/arm64/boot/dts/renesas/cat875.dtsi @@ -7,4 +7,34 @@ / { model = "Silicon Linux sub board for CAT874 (CAT875)"; + + aliases { + ethernet0 = &avb; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + phy-mode = "rgmii"; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + }; +}; + +&pfc { + avb_pins: avb { + mux { + groups = "avb_mii"; + function = "avb"; + }; + }; }; From bbbcd02b825529076951a37ee632cdb33df414c7 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Tue, 18 Dec 2018 12:05:54 -0500 Subject: [PATCH 210/506] ARM: dts: r7s9210: Initial SoC device tree Basic support for the RZ/A2 (R7S9210) SoC. Signed-off-by: Chris Brandt Reviewed-by: Ulrich Hecht Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s9210.dtsi | 218 +++++++++++++++++++++++++++++++++ 1 file changed, 218 insertions(+) create mode 100644 arch/arm/boot/dts/r7s9210.dtsi diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi new file mode 100644 index 000000000000..22baa96f5974 --- /dev/null +++ b/arch/arm/boot/dts/r7s9210.dtsi @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the R7S9210 SoC + * + * Copyright (C) 2018 Renesas Electronics Corporation + * + */ + +#include +#include + +/ { + compatible = "renesas,r7s9210"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + /* External clocks */ + extal_clk: extal { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* Value must be set by board */ + clock-frequency = <0>; + }; + + rtc_x1_clk: rtc_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value (32678) must be set by board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clock-frequency = <528000000>; + next-level-cache = <&L2>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + L2: cache-controller@1f003000 { + compatible = "arm,pl310-cache"; + reg = <0x1f003000 0x1000>; + interrupts = ; + arm,early-bresp-disable; + arm,full-line-zero-disable; + cache-unified; + cache-level = <2>; + }; + + scif0: serial@e8007000 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8007000 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 47>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif1: serial@e8007800 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8007800 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 46>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif2: serial@e8008000 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8008000 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 45>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif3: serial@e8008800 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8008800 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 44>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif4: serial@e8009000 { + compatible = "renesas,scif-r7s9210"; + reg = <0xe8009000 0x18>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD 43>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm0: timer@e803b000 { + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; + reg = <0xe803b000 0x30>; + interrupts = ; + clocks = <&cpg CPG_MOD 36>; + clock-names = "ostm0"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm1: timer@e803c000 { + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; + reg = <0xe803c000 0x30>; + interrupts = ; + clocks = <&cpg CPG_MOD 35>; + clock-names = "ostm1"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm2: timer@e803d000 { + compatible = "renesas,r7s9210-ostm", "renesas,ostm"; + reg = <0xe803d000 0x30>; + interrupts = ; + clocks = <&cpg CPG_MOD 34>; + clock-names = "ostm2"; + power-domains = <&cpg>; + status = "disabled"; + }; + + gic: interrupt-controller@e8221000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe8221000 0x1000>, + <0xe8222000 0x1000>; + }; + + cpg: clock-controller@fcfe0010 { + compatible = "renesas,r7s9210-cpg-mssr"; + reg = <0xfcfe0010 0x455>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + + wdt: watchdog@fcfe7000 { + compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt"; + reg = <0xfcfe7000 0x26>; + interrupts = ; + clocks = <&cpg CPG_CORE R7S9210_CLK_P0>; + }; + + bsid: chipid@fcfe8004 { + compatible = "renesas,bsid"; + reg = <0xfcfe8004 4>; + }; + + pinctrl: pin-controller@fcffe000 { + compatible = "renesas,r7s9210-pinctrl"; + reg = <0xfcffe000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 176>; + }; + }; +}; From 3a62c2d2581497de89abbb2d7e0d2ade9b39433e Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Tue, 18 Dec 2018 12:05:55 -0500 Subject: [PATCH 211/506] ARM: dts: r7s9210-rza2mevb: Add support for RZ/A2M EVB Add support for Renesas RZ/A2M evaluation board. Signed-off-by: Chris Brandt Reviewed-by: Ulrich Hecht Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r7s9210-rza2mevb.dts | 82 ++++++++++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 arch/arm/boot/dts/r7s9210-rza2mevb.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..3a3a931b431e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -843,6 +843,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r7s72100-genmai.dtb \ r7s72100-gr-peach.dtb \ r7s72100-rskrza1.dtb \ + r7s9210-rza2mevb.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ r8a7743-iwg20d-q7.dtb \ diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts new file mode 100644 index 000000000000..991e09de1219 --- /dev/null +++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZA2MEVB board + * + * Copyright (C) 2018 Renesas Electronics + * + */ + +/dts-v1/; +#include "r7s9210.dtsi" +#include +#include + +/ { + model = "RZA2MEVB"; + compatible = "renesas,rza2mevb", "renesas,r7s9210"; + + aliases { + serial0 = &scif4; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x00800000>; /* HyperRAM */ + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; + + leds { + compatible = "gpio-leds"; + + red { + gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>; + }; + green { + gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* EXTAL */ +&extal_clk { + clock-frequency = <24000000>; /* 24MHz */ +}; + +/* RTC_X1 */ +&rtc_x1_clk { + clock-frequency = <32768>; +}; + +&pinctrl { + /* Serial Console */ + scif4_pins: serial4 { + pinmux = , /* TxD4 */ + ; /* RxD4 */ + }; +}; + +/* High resolution System tick timers */ +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +/* Serial Console */ +&scif4 { + pinctrl-names = "default"; + pinctrl-0 = <&scif4_pins>; + + status = "okay"; +}; From 4abf8049fbd5a783b699e99c92f336aa6e42e17b Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Tue, 22 Jan 2019 07:46:46 +0000 Subject: [PATCH 212/506] ARM: dts: sun8i-h3: nanopi-m1-plus: enable HDMI This patch enable HDMI output on sun8i-h3-nanopi-m1-plus. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts index 65cba1050802..4ec94d72f021 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts @@ -67,6 +67,21 @@ pinctrl-names = "default"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&de { + status = "okay"; }; &ehci1 { @@ -94,6 +109,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; From 55ec26d6a4241363fa94f15377ebd8f1116fbfd7 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 12 Jan 2019 20:17:19 -0600 Subject: [PATCH 213/506] arm64: dts: allwinner: a64: Enable A64 timer workaround As instability in the architectural timer has been observed on multiple devices using this SoC, inluding the Pine64 and the Orange Pi Win, enable the workaround in the SoC's device tree. Acked-by: Maxime Ripard Signed-off-by: Samuel Holland Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index bf9b719481c4..8171c0a7f265 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -200,6 +200,7 @@ timer { compatible = "arm,armv8-timer"; + allwinner,erratum-unknown1; interrupts = , Date: Fri, 30 Nov 2018 15:58:46 +0800 Subject: [PATCH 214/506] ARM: dts: sunxi: h3/h5: Drop A31 fallback compatible for CSI controller The CSI controller found on the H3 (and H5) is a reduced version of the one found on the A31. It only has 1 channel, instead of 4 channels for time-multiplexed BT.656. Since the H3 is a reduced version, it cannot "fallback" to a compatible that implements more features than it supports. Drop the A31 fallback compatible. Fixes: f89120b6f554 ("ARM: dts: sun8i: Add the H3/H5 CSI controller") Reviewed-by: Jagan Teki Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index a4c757c0b741..d74a6cbbfdf4 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -740,8 +740,7 @@ }; csi: camera@1cb0000 { - compatible = "allwinner,sun8i-h3-csi", - "allwinner,sun6i-a31-csi"; + compatible = "allwinner,sun8i-h3-csi"; reg = <0x01cb0000 0x1000>; interrupts = ; clocks = <&ccu CLK_BUS_CSI>, From 7da10df988ca3bf9a07a21ae1f7bc58ac20a600e Mon Sep 17 00:00:00 2001 From: Felix Brack Date: Tue, 18 Dec 2018 15:39:31 +0100 Subject: [PATCH 215/506] ARM: dts: am33xx: Remove unnecessary properties Remove the unnecessary properties #address-cells and #size-cells of node pinmux as there are no child-nodes with property reg. Signed-off-by: Felix Brack Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 7b818d9d2eab..e957370f8aec 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -288,8 +288,6 @@ am33xx_pinmux: pinmux@800 { compatible = "pinctrl-single"; reg = <0x800 0x238>; - #address-cells = <1>; - #size-cells = <0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7f>; From a4aaf1242c2b3975437068d718142cb5ebf26e07 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 21 Dec 2018 18:12:20 +0000 Subject: [PATCH 216/506] ARM: dts: am437x: replace linux,wakeup with wakeup-source property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Most of the legacy "linux,wakeup" boolean property is already replaced with "wakeup-source". However few occurrences of old property has popped up again, probably from the remnants in downstream trees. Replace the legacy properties with the unified "wakeup-source" property introduced in the commit aeda5003d0b9 ("Input: matrix_keypad - change name of wakeup property to "wakeup-source"") Cc: "Benoît Cousson" Cc: Tony Lindgren Cc: linux-omap@vger.kernel.org Signed-off-by: Sudeep Holla Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index f4a20cade808..4c6ee37ea573 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -71,7 +71,7 @@ pinctrl-0 = <&matrix_keypad_default>; pinctrl-1 = <&matrix_keypad_sleep>; - linux,wakeup; + wakeup-source; row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */ &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ From dc81e8465d4a10deba37f5e62368a7d801e3dc0a Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 22 Jan 2019 06:26:22 +0100 Subject: [PATCH 217/506] ARM: dts: am335x-shc.dts: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Heiko Schocher Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-shc.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index d0fd68873689..5cdaf0cd9401 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -1,11 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * support for the bosch am335x based shc c3 board * * Copyright, C) 2015 Heiko Schocher * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; From b4c30df0eb354d8e081132b7b7449f6d17619614 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 13 Dec 2018 15:58:45 +0200 Subject: [PATCH 218/506] ARM: dts: omap4-sdp: Make ethernet working even if booted with latest u-boot The ethernet works in kernel only if we use some binary u-boot from the past which have support for KS8851. The u-boot sources are not available for this mysterious u-boot image people tends to hold on... Mainline u-bott does not have ethernet support for sdp4430 and if we use that the ethernet is not working. After some debugging I have managed to get the ethernet working with mainline u-boot while not breaking the networking with the case when we boot with the mysterious binary u-boot. Basically we were missing bunch of pinmux settings and the 'magic' gpio_138 handling in kernel. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-sdp.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 9dc7ec7655cb..c88817bdcc56 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -26,6 +26,9 @@ }; vdd_eth: fixedregulator-vdd-eth { + pinctrl-names = "default"; + pinctrl-0 = <&enet_enable_gpio>; + compatible = "regulator-fixed"; regulator-name = "VDD_ETH"; regulator-min-microvolt = <3300000>; @@ -352,6 +355,29 @@ OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ >; }; + + /* gpio_48 for ENET_ENABLE */ + enet_enable_gpio: pinmux_enet_enable_gpio { + pinctrl-single,pins = < + OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a24.gpio_48 */ + >; + }; + + ks8851_pins: pinmux_ks8851_pins { + pinctrl-single,pins = < + /* ENET_INT */ + OMAP4_IOPAD(0x054, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.gpio_34 */ + /* + * Misterious pin which makes the ethernet working + * The legacy board file requested this pin on boot + * (ETH_KS8851_QUART) and set it to high, similarly to + * the ENET_ENABLE pin. + * We could use gpio-hog to keep it high, but let's use + * it as a reset GPIO for ks8851. + */ + OMAP4_IOPAD(0x13a, PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.gpio_138 */ + >; + }; }; &i2c1 { @@ -452,12 +478,16 @@ pinctrl-0 = <&mcspi1_pins>; eth@0 { + pinctrl-names = "default"; + pinctrl-0 = <&ks8851_pins>; + compatible = "ks8851"; spi-max-frequency = <24000000>; reg = <0>; interrupt-parent = <&gpio2>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */ vdd-supply = <&vdd_eth>; + reset-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; }; }; From fee3b67480360c5a3d54c7f11c6ef8f6d30b76fe Mon Sep 17 00:00:00 2001 From: Graeme Smecher Date: Thu, 3 Jan 2019 15:16:26 -0800 Subject: [PATCH 219/506] ARM: ti81xx: Move I2C entries in omap_hwmod_81xx to maintain grouping There is no functional change here; the I2C and ELM entries leaked into each other and this separates them again. Signed-off-by: Graeme Smecher Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index 8e44e2728620..1ca8710ff29e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -432,6 +432,13 @@ static struct omap_hwmod dm81xx_i2c2_hwmod = { .class = &i2c_class, }; +static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_i2c2_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { .rev_offs = 0x0000, .sysc_offs = 0x0010, @@ -443,13 +450,6 @@ static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { .sysc_fields = &omap_hwmod_sysc_type1, }; -static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = { - .master = &dm81xx_l4_ls_hwmod, - .slave = &dm81xx_i2c2_hwmod, - .clk = "sysclk6_ck", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_class dm81xx_elm_hwmod_class = { .name = "elm", .sysc = &dm81xx_elm_sysc, From d27cda291b2341d39692421b4e64940879ff9dd8 Mon Sep 17 00:00:00 2001 From: Graeme Smecher Date: Thu, 3 Jan 2019 15:16:27 -0800 Subject: [PATCH 220/506] ARM: ti81xx: Add hwmod boilerplate for all GPIO and SPI peripherals GPIO3/4 and MCSPI2/3/4 are now present. Lightly tested on am3874 platform. Signed-off-by: Graeme Smecher [tony@atomide.com: split to apply hwmod and dts changes separately] Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 117 +++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index 1ca8710ff29e..debcd88ab971 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -539,6 +539,58 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "sysclk18_ck" }, +}; + +static struct omap_hwmod dm81xx_gpio3_hwmod = { + .name = "gpio3", + .clkdm_name = "alwon_l3s_clkdm", + .class = &dm81xx_gpio_hwmod_class, + .main_clk = "sysclk6_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), +}; + +static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio3 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_gpio3_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { + { .role = "dbclk", .clk = "sysclk18_ck" }, +}; + +static struct omap_hwmod dm81xx_gpio4_hwmod = { + .name = "gpio4", + .clkdm_name = "alwon_l3s_clkdm", + .class = &dm81xx_gpio_hwmod_class, + .main_clk = "sysclk6_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), +}; + +static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio4 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_gpio4_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = { .rev_offs = 0x0, .sysc_offs = 0x10, @@ -1133,6 +1185,45 @@ static struct omap_hwmod dm81xx_mcspi1_hwmod = { .class = &dm816x_mcspi_class, }; +static struct omap_hwmod dm81xx_mcspi2_hwmod = { + .name = "mcspi2", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk10_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &dm816x_mcspi_class, +}; + +static struct omap_hwmod dm81xx_mcspi3_hwmod = { + .name = "mcspi3", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk10_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &dm816x_mcspi_class, +}; + +static struct omap_hwmod dm81xx_mcspi4_hwmod = { + .name = "mcspi4", + .clkdm_name = "alwon_l3s_clkdm", + .main_clk = "sysclk10_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &dm816x_mcspi_class, +}; + static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { .master = &dm81xx_l4_ls_hwmod, .slave = &dm81xx_mcspi1_hwmod, @@ -1140,6 +1231,27 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi2 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_mcspi2_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi3 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_mcspi3_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi4 = { + .master = &dm81xx_l4_ls_hwmod, + .slave = &dm81xx_mcspi4_hwmod, + .clk = "sysclk6_ck", + .user = OCP_USER_MPU, +}; + static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = { .rev_offs = 0x000, .sysc_offs = 0x010, @@ -1378,8 +1490,13 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { &dm81xx_l4_ls__i2c2, &dm81xx_l4_ls__gpio1, &dm81xx_l4_ls__gpio2, + &dm81xx_l4_ls__gpio3, + &dm81xx_l4_ls__gpio4, &dm81xx_l4_ls__elm, &dm81xx_l4_ls__mcspi1, + &dm81xx_l4_ls__mcspi2, + &dm81xx_l4_ls__mcspi3, + &dm81xx_l4_ls__mcspi4, &dm814x_l4_ls__mmc1, &dm814x_l4_ls__mmc2, &ti81xx_l4_ls__rtc, From 417992d5744fe943d79f6681e29e7a54bb97e2e0 Mon Sep 17 00:00:00 2001 From: Graeme Smecher Date: Thu, 3 Jan 2019 15:16:27 -0800 Subject: [PATCH 221/506] ARM: dts: ti81xx: Add dts boilerplate for all GPIO and SPI peripherals GPIO3/4 and MCSPI2/3/4 are now present. Lightly tested on am3874 platform. Signed-off-by: Graeme Smecher [tony@atomide.com: split to apply hwmod and dts changes separately] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 64 ++++++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 601c57afd4fe..f044abd64b7e 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -222,6 +222,30 @@ #interrupt-cells = <2>; }; + gpio3: gpio@1ac000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio3"; + ti,gpio-always-on; + reg = <0x1ac000 0x2000>; + interrupts = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@1ae000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio4"; + ti,gpio-always-on; + reg = <0x1ae000 0x2000>; + interrupts = <62>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + i2c2: i2c@2a000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; @@ -240,10 +264,48 @@ ti,spi-num-cs = <4>; ti,hwmods = "mcspi1"; dmas = <&edma 16 0 &edma 17 0 - &edma 18 0 &edma 19 0>; + &edma 18 0 &edma 19 0 + &edma 20 0 &edma 21 0 + &edma 22 0 &edma 23 0>; + + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + }; + + mcspi2: spi@1a0000 { + compatible = "ti,omap4-mcspi"; + reg = <0x1a0000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <125>; + ti,spi-num-cs = <4>; + ti,hwmods = "mcspi2"; + dmas = <&edma 42 0 &edma 43 0 + &edma 44 0 &edma 45 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; }; + /* Board must configure dmas with edma_xbar for EDMA */ + mcspi3: spi@1a2000 { + compatible = "ti,omap4-mcspi"; + reg = <0x1a2000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <126>; + ti,spi-num-cs = <4>; + ti,hwmods = "mcspi3"; + }; + + mcspi4: spi@1a4000 { + compatible = "ti,omap4-mcspi"; + reg = <0x1a4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <127>; + ti,spi-num-cs = <4>; + ti,hwmods = "mcspi4"; + }; + timer1: timer@2e000 { compatible = "ti,dm814-timer"; reg = <0x2e000 0x2000>; From d031773169df2de868c1b6ff75679ddac5d4a7ec Mon Sep 17 00:00:00 2001 From: Graeme Smecher Date: Thu, 24 Jan 2019 10:15:58 -0800 Subject: [PATCH 222/506] ARM: dts: Adds device tree file for McGill's IceBoard, based on TI AM3874 This is an ARM + FPGA instrumentation board used at telescopes in Antarctica, Chile, and Canada: https://pole.uchicago.edu/ https://arxiv.org/abs/1608.03025 https://chime-experiment.ca/ With these commits and a suitable userspace, we can boot the board, load a FPGA bitstream, and communicate with the RTL design. Most of the board's telemetry sensors (temperatures, voltages) are functional but detailed testing is to follow. We are weaning ourselves off TI's "official" kernel for this SOC, which has been stuck at 2.6.37 and is not really fit for use. To anyone at TI: despite good silicon and some dedicated support enginers, your open-source software strategy for these parts has not worked well. Please get in touch with me if you'd like to have a constructive discussion about ways to improve it. Signed-off-by: Graeme Smecher [tony@atomide.com: dropped fpga@1 as linux,spidev is still undocumented] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/am3874-iceboard.dts | 496 ++++++++++++++++++++++++++ 2 files changed, 497 insertions(+) create mode 100644 arch/arm/boot/dts/am3874-iceboard.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..d87a165abebd 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -700,6 +700,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ omap3-thunder.dtb \ omap3-zoom3.dtb dtb-$(CONFIG_SOC_TI81XX) += \ + am3874-iceboard.dtb \ dm8148-evm.dtb \ dm8148-t410.dtb \ dm8168-evm.dtb \ diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts new file mode 100644 index 000000000000..883fb85135d4 --- /dev/null +++ b/arch/arm/boot/dts/am3874-iceboard.dts @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for Winterland IceBoard + * + * http://mcgillcosmology.com + * http://threespeedlogic.com + * + * This is an ARM + FPGA instrumentation board used at telescopes in + * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO + * observatory in British Columbia (CHIME). + * + * Copyright (c) 2019 Three-Speed Logic, Inc. + */ + +/dts-v1/; + +#include "dm814x.dtsi" +#include + +/ { + model = "Winterland IceBoard"; + compatible = "ti,dm8148", "ti,dm814"; + + chosen { + stdout-path = "serial1:115200n8"; + bootargs = "earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +/* The MAC provides internal delay for the transmit path ONLY, which is enabled + * provided no -id/-txid/-rxid suffix is provided to "phy-mode". + * + * The receive path is delayed at the PHY. The recommended register settings + * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the + * conversion code in the kernel lies: the PHY's registers are 120 ps per tap, + * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to + * obtain the correct register settings. + */ +&mac { dual_emac = <1>; }; +&cpsw_emac0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; +&cpsw_emac1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + ethphy0: ethernet-phy@0 { + reg = <0x2>; + + rxc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + + rxd3-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd0-skew-ps = <0>; + + phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + }; + + ethphy1: ethernet-phy@1 { + reg = <0x1>; + + rxc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + + rxd3-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd0-skew-ps = <0>; + + phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc1 { status = "disabled"; }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; +}; +&mmc3 { status = "disabled"; }; + +&i2c1 { + /* Most I2C activity happens through this port, with the sole exception + * of the backplane. Since there are multiply assigned addresses, the + * "i2c-mux-idle-disconnect" is important. + */ + + pca9548@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + /* FMC A */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + i2c-mux-idle-disconnect; + }; + + i2c@1 { + /* FMC B */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + i2c-mux-idle-disconnect; + }; + + i2c@2 { + /* QSFP A */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + i2c-mux-idle-disconnect; + }; + + i2c@3 { + /* QSFP B */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + i2c-mux-idle-disconnect; + }; + + i2c@4 { + /* SFP */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + i2c-mux-idle-disconnect; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + i2c-mux-idle-disconnect; + + ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; }; + ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; }; + ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; }; + + ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; }; + ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; }; + ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; }; + + ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; }; + ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; }; + ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; }; + ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; }; + ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; }; + ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; }; + ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; }; + ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; }; + ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; }; + }; + + i2c@6 { + /* Backplane */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + i2c-mux-idle-disconnect; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + i2c-mux-idle-disconnect; + + u41: pca9575@20 { + compatible = "nxp,pca9575"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C", + "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS", + "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C", + "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL"; + reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + u42: pca9575@21 { + compatible = "nxp,pca9575"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL", + "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL", + "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1", + "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR"; + reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + u48: pca9575@22 { + compatible = "nxp,pca9575"; + reg=<0x22>; + gpio-controller; + #gpio-cells = <2>; + + sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>, + <&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>; + led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>, + <&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>; + + gpio-line-names = + "GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4", + "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8", + "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5", + "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1"; + reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + u59: pca9575@23 { + compatible = "nxp,pca9575"; + reg=<0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12", + "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault", + "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3", + "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17"; + reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; }; + tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; }; + tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; }; + tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; }; + + /* EEPROM bank and serial number are treated as separate devices */ + at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; }; + at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; }; + }; + }; +}; + +&i2c2 { + pca9548@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@6 { + /* Backplane */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + multi-master; + + /* All backplanes should have this -- it's how we know they're there. */ + at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; }; + at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; }; + + /* 16 slot backplane */ + tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; }; + tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; }; + ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; }; + amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; }; + + /* Single slot backplane */ + }; + }; +}; + +&pincntl { + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ + DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ + DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ + DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ + DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ + DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ + DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40) /* SD1_POW */ + DM814X_IOPAD(0x0928, PIN_INPUT | 0x40) /* SD1_SDWP */ + DM814X_IOPAD(0x093C, PIN_INPUT | 0x2) /* SD1_SDCD */ + >; + }; + + usb0_pins: pinmux_usb0_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ + >; + }; + + usb1_pins: pinmux_usb1_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ + >; + }; + + gpio1_pins: pinmux_gpio1_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */ + DM814X_IOPAD(0x0820, PIN_INPUT | 0x80) /* INIT_B */ + DM814X_IOPAD(0x0824, PIN_INPUT | 0x80) /* DONE */ + + DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */ + DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */ + DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */ + DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */ + DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */ + + DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */ + DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */ + DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */ + DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */ + DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */ + + DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */ + DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */ + DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */ + DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */ + >; + }; + + gpio2_pins: pinmux_gpio2_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */ + DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */ + DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */ + DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */ + + //DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */ + //DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */ + DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */ + >; + }; + + gpio4_pins: pinmux_gpio4_pins { + pinctrl-single,pins = < + /* The PLL doesn't react well to the SPI controller reset, so + * we force the CS lines to pull up as GPIOs until we're ready. + * See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3 + */ + DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */ + DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */ + DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */ + DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */ + DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */ + DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */ + >; + }; + + spi2_pins: pinmux_spi2_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */ + DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */ + >; + }; + + spi4_pins: pinmux_spi4_pins { + pinctrl-single,pins = < + DM814X_IOPAD(0x0a7c, 0x20) + DM814X_IOPAD(0x0b74, 0x20) + DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20) + DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20) + DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20) + >; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; + gpio-line-names = + "", "PROGRAM_B", "INIT_B", "DONE", /* 0-3 */ + "", "", "", "", /* 4-7 */ + "FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI", /* 8-11 */ + "", "", "", "FMCA_TRST", /* 12-15 */ + "FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI", /* 16-19 */ + "FMCB_TRST", "", "", "", /* 20-23 */ + "FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI", /* 24-27 */ + "", "", "", ""; /* 28-31 */ +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_pins>; + gpio-line-names = + "PHYA_IRQ_N", "PHYA_RESET_N", "", "", /* 0-3 */ + "", "", "", "PHYB_IRQ_N", /* 4-7 */ + "PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", ""; /* 8-11 */ +}; + +&gpio3 { + pinctrl-names = "default"; + /*pinctrl-0 = <&gpio3_pins>;*/ + gpio-line-names = + "", "", "ARMClkSel0", "", /* 0-3 */ + "EnFPGARef", "", "", "ARMClkSel1"; /* 4-7 */ +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio4_pins>; + gpio-line-names = + "BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3", + "BP_ARM_GPIO4", "BP_ARM_GPIO5"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; + dr_mode = "host"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; + dr_mode = "host"; +}; + +&mcspi1 { + s25fl256@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + + fsbl@0 { + /* 256 kB */ + label = "U-Boot-min"; + reg = <0 0x40000>; + }; + ssbl@1 { + /* 512 kB */ + label = "U-Boot"; + reg = <0x40000 0x80000>; + }; + bootenv@2 { + /* 256 kB */ + label = "U-Boot Env"; + reg = <0xc0000 0x40000>; + }; + kernel@3 { + /* 4 MB */ + label = "Kernel"; + reg = <0x100000 0x400000>; + }; + ipmi@4 { + label = "IPMI FRU"; + reg = <0x500000 0x40000>; + }; + fs@5 { + label = "File System"; + reg = <0x540000 0x1ac0000>; + }; + }; +}; + +&mcspi3 { + /* DMA event numbers stolen from MCASP */ + dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17 + &edma_xbar 10 0 18 &edma_xbar 11 0 19>; + dma-names = "tx0", "rx0", "tx1", "rx1"; +}; + +&mcspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins>; + + /* DMA event numbers stolen from MCASP, MCBSP */ + dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>; + dma-names = "tx0", "rx0"; +}; From 08c2a076d18f3e481c004f59a9c4c9f07eec01db Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 4 Dec 2018 15:54:12 -0800 Subject: [PATCH 223/506] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file DPU is short for the Display Processing Unit. It is the display controller on Qualcomm SDM845 chips. This change adds MDSS and DSI nodes to enable display on the target device. Changes in v2: - Beefed up commit message - Use SoC specific compatibles for mdss and dpu (Rob H) - Use assigned-clocks to set initial clock frequency(Rob H) Changes in v3: - added IOMMU node - Fix device naming (remove _phys) - Use correct IRQ_TYPE in interrupt specifiers Changes in v4: - move mdss node to preserve the unit address sort order - remove _clk suffix from dsi clocks (both the comments are from Doug Anderson) Changes in v5: - Keep the device status "disabled" by default (Bjorn Andersson) - Use MDSS_GDSC macro (Jordan) - Fix phy-names (Jordan) - List reg ranges in numerical order (Jordan) Changes in v6: - Separating this patch out of the series - fix phy-names Signed-off-by: Jeykumar Sankaran Signed-off-by: Sean Paul Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 203 +++++++++++++++++++++++++++ 1 file changed, 203 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d9be5bba62c4..f19353414eda 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1617,6 +1617,209 @@ }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <300000000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0xae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0xae94400 0x200>, + <0xae94600 0x280>, + <0xae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface"; + + status = "disabled"; + }; + + dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0xae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0xae96400 0x200>, + <0xae96600 0x280>, + <0xae96a00 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface"; + + status = "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; reg = <0xaf00000 0x10000>; From d558f4c2c438c771514fc90ac1edf4b45cbc35fb Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Tue, 18 Dec 2018 11:04:43 -0700 Subject: [PATCH 224/506] arm64: dts: qcom: msm8998-mtp: Increase load on l21 for sdcard l21 is used as sdcard vmmc, and needs the load increased to prevent voltage drop issues with some sdcards. This addresses -84 errors seen during sdcard init with SDR104 cards. Signed-off-by: Jeffrey Hugo Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi index 50e9033aa7f6..288adbfe9086 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi @@ -192,6 +192,8 @@ vreg_l21a_2p95: l21 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; + regulator-allow-set-load; + regulator-system-load = <800000>; }; vreg_l22a_2p85: l22 { regulator-min-microvolt = <2864000>; From 1e71d0c273d0ad20c56371c5b1fd743c6a774207 Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Tue, 15 Jan 2019 11:36:23 -0700 Subject: [PATCH 225/506] arm64: dts: qcom: msm8998: Enumerate i2c controllers msm8998 has a dozen i2c controllers which can be used to connect to board specific peripherals. Enumerate the controllers so that boards can wire up as needed. Signed-off-by: Jeffrey Hugo [bjorn: Renumbered labels on BLSP2 nodes] Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 180 ++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 8d41b69ec2da..7136ab14df42 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -624,6 +624,186 @@ status = "disabled"; }; + blsp1_i2c1: i2c@c175000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c175000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c2: i2c@c176000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c176000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c3: i2c@c177000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c177000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c4: i2c@c178000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c178000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c5: i2c@c179000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c179000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c6: i2c@c17a000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c17a000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_i2c0: i2c@c1b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c1b5000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_i2c1: i2c@c1b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c1b6000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_i2c2: i2c@c1b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c1b7000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_i2c3: i2c@c1b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c1b8000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_i2c4: i2c@c1b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c1b9000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_i2c5: i2c@c1ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c175000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + blsp2_uart1: serial@c1b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xc1b0000 0x1000>; From e1ce853932b771a8a524f214b036941d9832e7c7 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 8 Oct 2018 13:17:11 -0700 Subject: [PATCH 226/506] arm64: dts: qcom: sdm845: Add qspi (quad SPI) node This adds the Quad SPI controller to the main sdm845 device tree file. Boards will be expected to assign the proper pinctrl depending on how many chip selects they have hooked up and how many data lines. This depends on commit 48735597f7bd ("clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header") to add the needed defines. It also shouldn't land until the patch ("dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation") [1] lands. [1] https://lkml.kernel.org/r/20181002214709.162330-1-ryandcase@chromium.org Reviewed-by: Stephen Boyd Signed-off-by: Douglas Anderson Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 47 ++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index f19353414eda..f6af1d02c8e3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1069,6 +1069,41 @@ interrupt-controller; #interrupt-cells = <2>; + qspi_clk: qspi-clk { + pinmux { + pins = "gpio95"; + function = "qspi_clk"; + }; + }; + + qspi_cs0: qspi-cs0 { + pinmux { + pins = "gpio90"; + function = "qspi_cs"; + }; + }; + + qspi_cs1: qspi-cs1 { + pinmux { + pins = "gpio89"; + function = "qspi_cs"; + }; + }; + + qspi_data01: qspi-data01 { + pinmux-data { + pins = "gpio91", "gpio92"; + function = "qspi_data"; + }; + }; + + qspi_data12: qspi-data12 { + pinmux-data { + pins = "gpio93", "gpio94"; + function = "qspi_data"; + }; + }; + qup_i2c0_default: qup-i2c0-default { pinmux { pins = "gpio0", "gpio1"; @@ -1437,6 +1472,18 @@ status = "disabled"; }; + qspi: spi@88df000 { + compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; + reg = <0x88df000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <&gcc GCC_QSPI_CORE_CLK>; + clock-names = "iface", "core"; + status = "disabled"; + }; + usb_1_hsphy: phy@88e2000 { compatible = "qcom,sdm845-qusb2-phy"; reg = <0x88e2000 0x400>; From 9aa4a27ec6b0cd7292dd8452dd386c6d0d5a4a18 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 28 Nov 2018 10:57:43 -0800 Subject: [PATCH 227/506] arm64: dts: sdm845: Add gpu clock controller node Add the GPU clock controller nodes as per the example. Signed-off-by: Douglas Anderson Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index f6af1d02c8e3..7cf3991b9d54 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -1457,6 +1458,16 @@ }; }; + gpucc: clock-controller@5090000 { + compatible = "qcom,sdm845-gpucc"; + reg = <0x05090000 0x9000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + sdhc_2: sdhci@8804000 { compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; reg = <0x8804000 0x1000>; From 05556681948be46422618e662edd69d719f6b109 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 3 Dec 2018 11:36:29 -0800 Subject: [PATCH 228/506] arm64: dts: sdm845: Add videocc node This adds the video clock controller node to sdm845 based on the examples in the bindings. Signed-off-by: Taniya Das Signed-off-by: Douglas Anderson Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 7cf3991b9d54..b86ba0d7feda 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -1675,6 +1676,14 @@ }; }; + videocc: clock-controller@ab00000 { + compatible = "qcom,sdm845-videocc"; + reg = <0x0ab00000 0x10000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; + mdss: mdss@ae00000 { compatible = "qcom,sdm845-mdss"; reg = <0x0ae00000 0x1000>; From 0cef5dd4035fb856a0b4676283d90f093ecd0148 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 5 Dec 2018 13:30:36 +0530 Subject: [PATCH 229/506] arm64: dts: sdm845: Add lpasscc node This adds the low pass audio clock controller node to sdm845 based on the example in the bindings. Reviewed-by: Douglas Anderson Signed-off-by: Taniya Das [bjorn: Disabled lpasscc node, as it's normally protected] Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 4 +++- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 55292f2f1552..ebf059eb7ffc 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -347,7 +347,9 @@ &gcc { protected-clocks = , , - ; + , + , + ; }; &i2c10 { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b86ba0d7feda..b5dc7c0e9d5a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -2008,6 +2009,14 @@ ; }; + lpasscc: clock-controller@17014000 { + compatible = "qcom,sdm845-lpasscc"; + reg = <0x17014000 0x1f004>, <0x17300000 0x200>; + reg-names = "cc", "qdsp6ss"; + #clock-cells = <1>; + status = "disabled"; + }; + apss_shared: mailbox@17990000 { compatible = "qcom,sdm845-apss-shared"; reg = <0x17990000 0x1000>; From 539e7a6849ae6a96f758889df8922b47b649f37c Mon Sep 17 00:00:00 2001 From: Manu Gautam Date: Thu, 25 Oct 2018 22:53:17 +0530 Subject: [PATCH 230/506] arm64: dts: qcom: sdm845: Fix pcs_misc region address for UNI PHY Correct address for pcs_misc register region of USB3 QMP UNI PHY. These registers are used during runtime-suspend/resume routines of phy. Reviewed-by: Douglas Anderson Fixes: ca4db2b538a1 ("arm64: dts: qcom: sdm845: Add USB-related nodes") Signed-off-by: Manu Gautam Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b5dc7c0e9d5a..14eb5ff7be59 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1585,7 +1585,7 @@ reg = <0x88eb200 0x128>, <0x88eb400 0x1fc>, <0x88eb800 0x218>, - <0x88e9600 0x70>; + <0x88eb600 0x70>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "pipe0"; From 77bb7f94555c3863f815e41c62149e0df2deaa62 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 26 Oct 2018 17:55:42 +0530 Subject: [PATCH 231/506] arm64: dts: qcom: sdm845: Add SCM DT node Add SCM DT node to enable SCM functionality on SDM845. Reviewed-by: Bjorn Andersson Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 14eb5ff7be59..492c5c027a8e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -233,6 +233,12 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-sdm845", "qcom,scm"; + }; + }; + tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_regs 0 0x1000>; From 13393da0c698b43b0e8bd710060b99da59727150 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 26 Oct 2018 17:56:53 +0530 Subject: [PATCH 232/506] arm64: dts: qcom: sdm845: Add PDC Global reset driver node This patch adds the node to support PDC Global reset driver on SDM845 SoCs Reviewed-by: Bjorn Andersson Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 492c5c027a8e..c98b1937353b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -1902,6 +1903,12 @@ #power-domain-cells = <1>; }; + pdc_reset: reset-controller@b2e0000 { + compatible = "qcom,sdm845-pdc-global"; + reg = <0x0b2e0000 0x20000>; + #reset-cells = <1>; + }; + tsens0: thermal-sensor@c263000 { compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; reg = <0xc263000 0x1ff>, /* TM */ From 022bccb840b7ff9c64a70e81ac017d4d10bb8a9c Mon Sep 17 00:00:00 2001 From: Govind Singh Date: Mon, 5 Nov 2018 18:38:37 +0530 Subject: [PATCH 233/506] arm64: dts: sdm845: Add WCN3990 WLAN module device node Add device node for the ath10k SNOC platform driver probe and add resources required for WCN3990 on SDM845 soc. Reviewed-by: Brian Norris Tested-by: Brian Norris Signed-off-by: Govind Singh Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 8 ++++++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 +++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index ebf059eb7ffc..af8c6a2445a2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -452,6 +452,14 @@ vdda-pll-supply = <&vdda_usb2_ss_core>; }; +&wifi { + status = "okay"; + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; +}; + /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qup_i2c10_default { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index c98b1937353b..0c92a603133e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -92,6 +92,11 @@ reg = <0 0x86200000 0 0x2d00000>; no-map; }; + + wlan_msa_mem: memory@96700000 { + reg = <0 0x96700000 0 0x100000>; + no-map; + }; }; cpus { @@ -2147,6 +2152,27 @@ #freq-domain-cells = <1>; }; + + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + status = "disabled"; + reg = <0x18800000 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_msa_mem>; + interrupts = + , + , + , + , + , + , + , + , + , + , + , + ; + }; }; thermal-zones { From fae1967f31c3accb6d0be95da3b0cd909850d80a Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 10 Jan 2019 09:32:06 +0530 Subject: [PATCH 234/506] arm64: dts: msm8996: Add rpmpd device node Add rpmpd device node and its OPP table Reviewed-by: Ulf Hansson Reviewed-by: Stephen Boyd Signed-off-by: Rajendra Nayak Signed-off-by: Viresh Kumar Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 34 +++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 838e32cc14c9..6ba96916c66d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -306,6 +306,40 @@ #clock-cells = <1>; }; + rpmpd: power-controller { + compatible = "qcom,msm8996-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp1: opp1 { + opp-level = <1>; + }; + + rpmpd_opp2: opp2 { + opp-level = <2>; + }; + + rpmpd_opp3: opp3 { + opp-level = <3>; + }; + + rpmpd_opp4: opp4 { + opp-level = <4>; + }; + + rpmpd_opp5: opp5 { + opp-level = <5>; + }; + + rpmpd_opp6: opp6 { + opp-level = <6>; + }; + }; + }; + pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; From 5b6f186f0abb7e6c0db4ab3a5eb2831412d03673 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 10 Jan 2019 09:32:08 +0530 Subject: [PATCH 235/506] arm64: dts: sdm845: Add rpmh powercontroller node Add the DT node for the rpmhpd powercontroller. Acked-by: Viresh Kumar Reviewed-by: Stephen Boyd Signed-off-by: Rajendra Nayak Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0c92a603133e..f39e291fb1c6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -2062,6 +2063,56 @@ compatible = "qcom,sdm845-rpmh-clk"; #clock-cells = <1>; }; + + rpmhpd: power-controller { + compatible = "qcom,sdm845-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; }; intc: interrupt-controller@17a00000 { From bede7d2dc8f36cc88212ae8d1e849fc7203cf2fe Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 16 Jan 2019 20:29:39 -0800 Subject: [PATCH 236/506] arm64: dts: qcom: sdm845: Increase address and size cells for soc The busses on SDM845 provides 36 address bits, extend the address and size cells to make it possible to describe this in "ranges" and "dma-ranges". While touching all reg properties, addresses are padded to 8 digits. Tested-by: Douglas Anderson Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 300 +++++++++++++-------------- 1 file changed, 150 insertions(+), 150 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index f39e291fb1c6..e8daa73e1551 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -352,14 +352,14 @@ }; soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0 0xffffffff>; compatible = "simple-bus"; gcc: clock-controller@100000 { compatible = "qcom,gcc-sdm845"; - reg = <0x100000 0x1f0000>; + reg = <0 0x00100000 0 0x1f0000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -367,7 +367,7 @@ qfprom@784000 { compatible = "qcom,qfprom"; - reg = <0x784000 0x8ff>; + reg = <0 0x00784000 0 0x8ff>; #address-cells = <1>; #size-cells = <1>; @@ -384,25 +384,25 @@ rng: rng@793000 { compatible = "qcom,prng-ee"; - reg = <0x00793000 0x1000>; + reg = <0 0x00793000 0 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; - reg = <0x8c0000 0x6000>; + reg = <0 0x008c0000 0 0x6000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; status = "disabled"; i2c0: i2c@880000 { compatible = "qcom,geni-i2c"; - reg = <0x880000 0x4000>; + reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; @@ -415,7 +415,7 @@ spi0: spi@880000 { compatible = "qcom,geni-spi"; - reg = <0x880000 0x4000>; + reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; @@ -428,7 +428,7 @@ uart0: serial@880000 { compatible = "qcom,geni-uart"; - reg = <0x880000 0x4000>; + reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; @@ -439,7 +439,7 @@ i2c1: i2c@884000 { compatible = "qcom,geni-i2c"; - reg = <0x884000 0x4000>; + reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; @@ -452,7 +452,7 @@ spi1: spi@884000 { compatible = "qcom,geni-spi"; - reg = <0x884000 0x4000>; + reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; @@ -465,7 +465,7 @@ uart1: serial@884000 { compatible = "qcom,geni-uart"; - reg = <0x884000 0x4000>; + reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; @@ -476,7 +476,7 @@ i2c2: i2c@888000 { compatible = "qcom,geni-i2c"; - reg = <0x888000 0x4000>; + reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; @@ -489,7 +489,7 @@ spi2: spi@888000 { compatible = "qcom,geni-spi"; - reg = <0x888000 0x4000>; + reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; @@ -502,7 +502,7 @@ uart2: serial@888000 { compatible = "qcom,geni-uart"; - reg = <0x888000 0x4000>; + reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; @@ -513,7 +513,7 @@ i2c3: i2c@88c000 { compatible = "qcom,geni-i2c"; - reg = <0x88c000 0x4000>; + reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; @@ -526,7 +526,7 @@ spi3: spi@88c000 { compatible = "qcom,geni-spi"; - reg = <0x88c000 0x4000>; + reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; @@ -539,7 +539,7 @@ uart3: serial@88c000 { compatible = "qcom,geni-uart"; - reg = <0x88c000 0x4000>; + reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; @@ -550,7 +550,7 @@ i2c4: i2c@890000 { compatible = "qcom,geni-i2c"; - reg = <0x890000 0x4000>; + reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; @@ -563,7 +563,7 @@ spi4: spi@890000 { compatible = "qcom,geni-spi"; - reg = <0x890000 0x4000>; + reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; @@ -576,7 +576,7 @@ uart4: serial@890000 { compatible = "qcom,geni-uart"; - reg = <0x890000 0x4000>; + reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; @@ -587,7 +587,7 @@ i2c5: i2c@894000 { compatible = "qcom,geni-i2c"; - reg = <0x894000 0x4000>; + reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; @@ -600,7 +600,7 @@ spi5: spi@894000 { compatible = "qcom,geni-spi"; - reg = <0x894000 0x4000>; + reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; @@ -613,7 +613,7 @@ uart5: serial@894000 { compatible = "qcom,geni-uart"; - reg = <0x894000 0x4000>; + reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; @@ -624,7 +624,7 @@ i2c6: i2c@898000 { compatible = "qcom,geni-i2c"; - reg = <0x898000 0x4000>; + reg = <0 0x00898000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; pinctrl-names = "default"; @@ -637,7 +637,7 @@ spi6: spi@898000 { compatible = "qcom,geni-spi"; - reg = <0x898000 0x4000>; + reg = <0 0x00898000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; pinctrl-names = "default"; @@ -650,7 +650,7 @@ uart6: serial@898000 { compatible = "qcom,geni-uart"; - reg = <0x898000 0x4000>; + reg = <0 0x00898000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; pinctrl-names = "default"; @@ -661,7 +661,7 @@ i2c7: i2c@89c000 { compatible = "qcom,geni-i2c"; - reg = <0x89c000 0x4000>; + reg = <0 0x0089c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; pinctrl-names = "default"; @@ -674,7 +674,7 @@ spi7: spi@89c000 { compatible = "qcom,geni-spi"; - reg = <0x89c000 0x4000>; + reg = <0 0x0089c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; pinctrl-names = "default"; @@ -687,7 +687,7 @@ uart7: serial@89c000 { compatible = "qcom,geni-uart"; - reg = <0x89c000 0x4000>; + reg = <0 0x0089c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; pinctrl-names = "default"; @@ -699,18 +699,18 @@ qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; - reg = <0xac0000 0x6000>; + reg = <0 0x00ac0000 0 0x6000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; status = "disabled"; i2c8: i2c@a80000 { compatible = "qcom,geni-i2c"; - reg = <0xa80000 0x4000>; + reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; @@ -723,7 +723,7 @@ spi8: spi@a80000 { compatible = "qcom,geni-spi"; - reg = <0xa80000 0x4000>; + reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; @@ -736,7 +736,7 @@ uart8: serial@a80000 { compatible = "qcom,geni-uart"; - reg = <0xa80000 0x4000>; + reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; @@ -747,7 +747,7 @@ i2c9: i2c@a84000 { compatible = "qcom,geni-i2c"; - reg = <0xa84000 0x4000>; + reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; @@ -760,7 +760,7 @@ spi9: spi@a84000 { compatible = "qcom,geni-spi"; - reg = <0xa84000 0x4000>; + reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; @@ -773,7 +773,7 @@ uart9: serial@a84000 { compatible = "qcom,geni-debug-uart"; - reg = <0xa84000 0x4000>; + reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; @@ -784,7 +784,7 @@ i2c10: i2c@a88000 { compatible = "qcom,geni-i2c"; - reg = <0xa88000 0x4000>; + reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; @@ -797,7 +797,7 @@ spi10: spi@a88000 { compatible = "qcom,geni-spi"; - reg = <0xa88000 0x4000>; + reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; @@ -810,7 +810,7 @@ uart10: serial@a88000 { compatible = "qcom,geni-uart"; - reg = <0xa88000 0x4000>; + reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; @@ -821,7 +821,7 @@ i2c11: i2c@a8c000 { compatible = "qcom,geni-i2c"; - reg = <0xa8c000 0x4000>; + reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; @@ -834,7 +834,7 @@ spi11: spi@a8c000 { compatible = "qcom,geni-spi"; - reg = <0xa8c000 0x4000>; + reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; @@ -847,7 +847,7 @@ uart11: serial@a8c000 { compatible = "qcom,geni-uart"; - reg = <0xa8c000 0x4000>; + reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; @@ -858,7 +858,7 @@ i2c12: i2c@a90000 { compatible = "qcom,geni-i2c"; - reg = <0xa90000 0x4000>; + reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; @@ -871,7 +871,7 @@ spi12: spi@a90000 { compatible = "qcom,geni-spi"; - reg = <0xa90000 0x4000>; + reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; @@ -884,7 +884,7 @@ uart12: serial@a90000 { compatible = "qcom,geni-uart"; - reg = <0xa90000 0x4000>; + reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; @@ -895,7 +895,7 @@ i2c13: i2c@a94000 { compatible = "qcom,geni-i2c"; - reg = <0xa94000 0x4000>; + reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; @@ -908,7 +908,7 @@ spi13: spi@a94000 { compatible = "qcom,geni-spi"; - reg = <0xa94000 0x4000>; + reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; @@ -921,7 +921,7 @@ uart13: serial@a94000 { compatible = "qcom,geni-uart"; - reg = <0xa94000 0x4000>; + reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; @@ -932,7 +932,7 @@ i2c14: i2c@a98000 { compatible = "qcom,geni-i2c"; - reg = <0xa98000 0x4000>; + reg = <0 0x00a98000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; pinctrl-names = "default"; @@ -945,7 +945,7 @@ spi14: spi@a98000 { compatible = "qcom,geni-spi"; - reg = <0xa98000 0x4000>; + reg = <0 0x00a98000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; pinctrl-names = "default"; @@ -958,7 +958,7 @@ uart14: serial@a98000 { compatible = "qcom,geni-uart"; - reg = <0xa98000 0x4000>; + reg = <0 0x00a98000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; pinctrl-names = "default"; @@ -969,7 +969,7 @@ i2c15: i2c@a9c000 { compatible = "qcom,geni-i2c"; - reg = <0xa9c000 0x4000>; + reg = <0 0x00a9c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; pinctrl-names = "default"; @@ -982,7 +982,7 @@ spi15: spi@a9c000 { compatible = "qcom,geni-spi"; - reg = <0xa9c000 0x4000>; + reg = <0 0x00a9c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; pinctrl-names = "default"; @@ -995,7 +995,7 @@ uart15: serial@a9c000 { compatible = "qcom,geni-uart"; - reg = <0xa9c000 0x4000>; + reg = <0 0x00a9c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; pinctrl-names = "default"; @@ -1008,7 +1008,7 @@ ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0x1d84000 0x2500>; + reg = <0 0x01d84000 0 0x2500>; interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -1050,9 +1050,9 @@ ufs_mem_phy: phy@1d87000 { compatible = "qcom,sdm845-qmp-ufs-phy"; - reg = <0x1d87000 0x18c>; - #address-cells = <1>; - #size-cells = <1>; + reg = <0 0x01d87000 0 0x18c>; + #address-cells = <2>; + #size-cells = <2>; ranges; clock-names = "ref", "ref_aux"; @@ -1062,23 +1062,23 @@ status = "disabled"; ufs_mem_phy_lanes: lanes@1d87400 { - reg = <0x1d87400 0x108>, - <0x1d87600 0x1e0>, - <0x1d87c00 0x1dc>, - <0x1d87800 0x108>, - <0x1d87a00 0x1e0>; + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; #phy-cells = <0>; }; }; tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; - reg = <0x1f40000 0x40000>; + reg = <0 0x01f40000 0 0x40000>; }; tlmm: pinctrl@3400000 { compatible = "qcom,sdm845-pinctrl"; - reg = <0x03400000 0xc00000>; + reg = <0 0x03400000 0 0xc00000>; interrupts = ; gpio-controller; #gpio-cells = <2>; @@ -1475,7 +1475,7 @@ gpucc: clock-controller@5090000 { compatible = "qcom,sdm845-gpucc"; - reg = <0x05090000 0x9000>; + reg = <0 0x05090000 0 0x9000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -1485,7 +1485,7 @@ sdhc_2: sdhci@8804000 { compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x8804000 0x1000>; + reg = <0 0x08804000 0 0x1000>; interrupts = , ; @@ -1500,7 +1500,7 @@ qspi: spi@88df000 { compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; - reg = <0x88df000 0x600>; + reg = <0 0x088df000 0 0x600>; #address-cells = <1>; #size-cells = <0>; interrupts = ; @@ -1512,7 +1512,7 @@ usb_1_hsphy: phy@88e2000 { compatible = "qcom,sdm845-qusb2-phy"; - reg = <0x88e2000 0x400>; + reg = <0 0x088e2000 0 0x400>; status = "disabled"; #phy-cells = <0>; @@ -1527,7 +1527,7 @@ usb_2_hsphy: phy@88e3000 { compatible = "qcom,sdm845-qusb2-phy"; - reg = <0x88e3000 0x400>; + reg = <0 0x088e3000 0 0x400>; status = "disabled"; #phy-cells = <0>; @@ -1542,13 +1542,13 @@ usb_1_qmpphy: phy@88e9000 { compatible = "qcom,sdm845-qmp-usb3-phy"; - reg = <0x88e9000 0x18c>, - <0x88e8000 0x10>; + reg = <0 0x088e9000 0 0x18c>, + <0 0x088e8000 0 0x10>; reg-names = "reg-base", "dp_com"; status = "disabled"; #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, @@ -1562,12 +1562,12 @@ reset-names = "phy", "common"; usb_1_ssphy: lanes@88e9200 { - reg = <0x88e9200 0x128>, - <0x88e9400 0x200>, - <0x88e9c00 0x218>, - <0x88e9600 0x128>, - <0x88e9800 0x200>, - <0x88e9a00 0x100>; + reg = <0 0x088e9200 0 0x128>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x218>, + <0 0x088e9600 0 0x128>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "pipe0"; @@ -1577,11 +1577,11 @@ usb_2_qmpphy: phy@88eb000 { compatible = "qcom,sdm845-qmp-usb3-uni-phy"; - reg = <0x88eb000 0x18c>; + reg = <0 0x088eb000 0 0x18c>; status = "disabled"; #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, @@ -1595,10 +1595,10 @@ reset-names = "phy", "common"; usb_2_ssphy: lane@88eb200 { - reg = <0x88eb200 0x128>, - <0x88eb400 0x1fc>, - <0x88eb800 0x218>, - <0x88eb600 0x70>; + reg = <0 0x088eb200 0 0x128>, + <0 0x088eb400 0 0x1fc>, + <0 0x088eb800 0 0x218>, + <0 0x088eb600 0 0x70>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "pipe0"; @@ -1608,10 +1608,10 @@ usb_1: usb@a6f8800 { compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; - reg = <0xa6f8800 0x400>; + reg = <0 0x0a6f8800 0 0x400>; status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, @@ -1639,7 +1639,7 @@ usb_1_dwc3: dwc3@a600000 { compatible = "snps,dwc3"; - reg = <0xa600000 0xcd00>; + reg = <0 0x0a600000 0 0xcd00>; interrupts = ; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; @@ -1650,10 +1650,10 @@ usb_2: usb@a8f8800 { compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; - reg = <0xa8f8800 0x400>; + reg = <0 0x0a8f8800 0 0x400>; status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, @@ -1681,7 +1681,7 @@ usb_2_dwc3: dwc3@a800000 { compatible = "snps,dwc3"; - reg = <0xa800000 0xcd00>; + reg = <0 0x0a800000 0 0xcd00>; interrupts = ; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; @@ -1692,7 +1692,7 @@ videocc: clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; - reg = <0x0ab00000 0x10000>; + reg = <0 0x0ab00000 0 0x10000>; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; @@ -1700,7 +1700,7 @@ mdss: mdss@ae00000 { compatible = "qcom,sdm845-mdss"; - reg = <0x0ae00000 0x1000>; + reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; power-domains = <&dispcc MDSS_GDSC>; @@ -1722,14 +1722,14 @@ status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; mdss_mdp: mdp@ae01000 { compatible = "qcom,sdm845-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; reg-names = "mdp", "vbif"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, @@ -1770,7 +1770,7 @@ dsi0: dsi@ae94000 { compatible = "qcom,mdss-dsi-ctrl"; - reg = <0xae94000 0x400>; + reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; @@ -1818,9 +1818,9 @@ dsi0_phy: dsi-phy@ae94400 { compatible = "qcom,dsi-phy-10nm"; - reg = <0xae94400 0x200>, - <0xae94600 0x280>, - <0xae94a00 0x1e0>; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -1836,7 +1836,7 @@ dsi1: dsi@ae96000 { compatible = "qcom,mdss-dsi-ctrl"; - reg = <0xae96000 0x400>; + reg = <0 0x0ae96000 0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; @@ -1884,9 +1884,9 @@ dsi1_phy: dsi-phy@ae96400 { compatible = "qcom,dsi-phy-10nm"; - reg = <0xae96400 0x200>, - <0xae96600 0x280>, - <0xae96a00 0x10e>; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96a00 0 0x10e>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -1903,7 +1903,7 @@ dispcc: clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; - reg = <0xaf00000 0x10000>; + reg = <0 0x0af00000 0 0x10000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -1911,39 +1911,39 @@ pdc_reset: reset-controller@b2e0000 { compatible = "qcom,sdm845-pdc-global"; - reg = <0x0b2e0000 0x20000>; + reg = <0 0x0b2e0000 0 0x20000>; #reset-cells = <1>; }; tsens0: thermal-sensor@c263000 { compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; - reg = <0xc263000 0x1ff>, /* TM */ - <0xc222000 0x1ff>; /* SROT */ + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x1ff>; /* SROT */ #qcom,sensors = <13>; #thermal-sensor-cells = <1>; }; tsens1: thermal-sensor@c265000 { compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; - reg = <0xc265000 0x1ff>, /* TM */ - <0xc223000 0x1ff>; /* SROT */ + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x1ff>; /* SROT */ #qcom,sensors = <8>; #thermal-sensor-cells = <1>; }; aoss_reset: reset-controller@c2a0000 { compatible = "qcom,sdm845-aoss-cc"; - reg = <0xc2a0000 0x31000>; + reg = <0 0x0c2a0000 0 0x31000>; #reset-cells = <1>; }; spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0xc440000 0x1100>, - <0xc600000 0x2000000>, - <0xe600000 0x100000>, - <0xe700000 0xa0000>, - <0xc40a000 0x26000>; + reg = <0 0x0c440000 0 0x1100>, + <0 0x0c600000 0 0x2000000>, + <0 0x0e600000 0 0x100000>, + <0 0x0e700000 0 0xa0000>, + <0 0x0c40a000 0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; @@ -1958,7 +1958,7 @@ apps_smmu: iommu@15000000 { compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; - reg = <0x15000000 0x80000>; + reg = <0 0x15000000 0 0x80000>; #iommu-cells = <2>; #global-interrupts = <1>; interrupts = , @@ -2038,16 +2038,16 @@ apss_shared: mailbox@17990000 { compatible = "qcom,sdm845-apss-shared"; - reg = <0x17990000 0x1000>; + reg = <0 0x17990000 0 0x1000>; #mbox-cells = <1>; }; apps_rsc: rsc@179c0000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; - reg = <0x179c0000 0x10000>, - <0x179d0000 0x10000>, - <0x179e0000 0x10000>; + reg = <0 0x179c0000 0 0x10000>, + <0 0x179d0000 0 0x10000>, + <0 0x179e0000 0 0x10000>; reg-names = "drv-0", "drv-1", "drv-2"; interrupts = , , @@ -2117,85 +2117,85 @@ intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; #interrupt-cells = <3>; interrupt-controller; - reg = <0x17a00000 0x10000>, /* GICD */ - <0x17a60000 0x100000>; /* GICR * 8 */ + reg = <0 0x17a00000 0 0x10000>, /* GICD */ + <0 0x17a60000 0 0x100000>; /* GICR * 8 */ interrupts = ; gic-its@17a40000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; - reg = <0x17a40000 0x20000>; + reg = <0 0x17a40000 0 0x20000>; status = "disabled"; }; }; timer@17c90000 { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; compatible = "arm,armv7-timer-mem"; - reg = <0x17c90000 0x1000>; + reg = <0 0x17c90000 0 0x1000>; frame@17ca0000 { frame-number = <0>; interrupts = , ; - reg = <0x17ca0000 0x1000>, - <0x17cb0000 0x1000>; + reg = <0 0x17ca0000 0 0x1000>, + <0 0x17cb0000 0 0x1000>; }; frame@17cc0000 { frame-number = <1>; interrupts = ; - reg = <0x17cc0000 0x1000>; + reg = <0 0x17cc0000 0 0x1000>; status = "disabled"; }; frame@17cd0000 { frame-number = <2>; interrupts = ; - reg = <0x17cd0000 0x1000>; + reg = <0 0x17cd0000 0 0x1000>; status = "disabled"; }; frame@17ce0000 { frame-number = <3>; interrupts = ; - reg = <0x17ce0000 0x1000>; + reg = <0 0x17ce0000 0 0x1000>; status = "disabled"; }; frame@17cf0000 { frame-number = <4>; interrupts = ; - reg = <0x17cf0000 0x1000>; + reg = <0 0x17cf0000 0 0x1000>; status = "disabled"; }; frame@17d00000 { frame-number = <5>; interrupts = ; - reg = <0x17d00000 0x1000>; + reg = <0 0x17d00000 0 0x1000>; status = "disabled"; }; frame@17d10000 { frame-number = <6>; interrupts = ; - reg = <0x17d10000 0x1000>; + reg = <0 0x17d10000 0 0x1000>; status = "disabled"; }; }; cpufreq_hw: cpufreq@17d43000 { compatible = "qcom,cpufreq-hw"; - reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; + reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; @@ -2207,7 +2207,7 @@ wifi: wifi@18800000 { compatible = "qcom,wcn3990-wifi"; status = "disabled"; - reg = <0x18800000 0x800000>; + reg = <0 0x18800000 0 0x800000>; reg-names = "membase"; memory-region = <&wlan_msa_mem>; interrupts = From 9feb667d8674f7f85f5ab6c8d88788a0fbef8d7d Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 16 Jan 2019 20:29:40 -0800 Subject: [PATCH 237/506] arm64: dts: qcom: sdm845: Extend ranges and describe DMA space For devices attached to an IOMMU, translation between IOVA and physical addresses is no longer 1:1 and dma-ranges should be specified to describe the available IOVA address space. On SDM845 the busses are implemented with 36 address bits, so dma-ranges must be defined to reduce the size of the IOVA address space from the 48 bits supported by the SMMU. Without this DMA allocations may end up with IOVAs outside the valid range, that gets truncated by the bus between the device and its translation unit. Also extend ranges to describe the available address space. Tested-by: Douglas Anderson Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e8daa73e1551..e4156ea320aa 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -354,7 +354,8 @@ soc: soc { #address-cells = <2>; #size-cells = <2>; - ranges = <0 0 0 0 0 0xffffffff>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; compatible = "simple-bus"; gcc: clock-controller@100000 { From bc2c806293c671e3ca403712c737cb4e7dfb15ef Mon Sep 17 00:00:00 2001 From: Evan Green Date: Fri, 9 Nov 2018 15:52:12 -0800 Subject: [PATCH 238/506] arm64: dts: qcom: sdm845: Add gpio-ranges to TLMM node Add the gpio-ranges property to the TLMM node so that GPIO hogs work. Reviewed-by: Stephen Boyd Signed-off-by: Evan Green Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e4156ea320aa..f6b11d55cfae 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1085,6 +1085,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 150>; qspi_clk: qspi-clk { pinmux { From 8ed6d484ec76c8c77ef9deca3875de50d83c7221 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Wed, 31 Oct 2018 11:39:21 +0530 Subject: [PATCH 239/506] arm64: dts: qcom: sdm845: Add reserve-memory nodes Add reserve-memory nodes for mpss and mba required for remoteproc mss pil. Reviewed-by: Bjorn Andersson Reviewed-by: Douglas Anderson Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index f6b11d55cfae..8803ea7d3af1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -98,6 +98,16 @@ reg = <0 0x96700000 0 0x100000>; no-map; }; + + mpss_region: memory@8e000000 { + reg = <0 0x8e000000 0 0x7800000>; + no-map; + }; + + mba_region: memory@96500000 { + reg = <0 0x96500000 0 0x200000>; + no-map; + }; }; cpus { From ea0edd7e63f4c2f7f024b3280045a31076dbdf70 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Wed, 9 Jan 2019 23:16:49 +0530 Subject: [PATCH 240/506] arm64: dts: qcom: sdm845: Remove the duplicate header inclusion Remove the duplicate inclusion of qcom,gcc-sdm845.h mistakenly introduced by commit 6e17f8140521 ("arm64: dts: sdm845: add prng-ee node"). Reviewed-by: Douglas Anderson Signed-off-by: Sai Prakash Ranjan [bjorn: Also fix sort order of lpasscc include, while we're there] Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 8803ea7d3af1..232de8c690ef 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -7,8 +7,8 @@ #include #include -#include #include +#include #include #include #include @@ -17,7 +17,6 @@ #include #include #include -#include / { interrupt-parent = <&intc>; From 1d918e9a8cc7306ae6a0b0c5580f57cfd1122d6f Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 17 Jan 2019 11:29:55 -0800 Subject: [PATCH 241/506] arm64: dts: qcom: sdm845: Fix lpasscc reg Fix up the lpasscc address and size, missed during the conversion to address- and size-cells of 2. Reviewed-by: Douglas Anderson Reported-by: Doug Anderson Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 232de8c690ef..0ec827394e92 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2041,7 +2041,7 @@ lpasscc: clock-controller@17014000 { compatible = "qcom,sdm845-lpasscc"; - reg = <0x17014000 0x1f004>, <0x17300000 0x200>; + reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; reg-names = "cc", "qdsp6ss"; #clock-cells = <1>; status = "disabled"; From 5bb9ab94f43ba56d048e101df645349c72a15da9 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sun, 18 Nov 2018 12:01:33 -0800 Subject: [PATCH 242/506] arm64: dts: qcom: qcs404: Specify pinctrl state for UART BLSP1 UART2 is used as debug uart on the EVB development board, define pinmux state for the UART in the platform dtsi and pinconf state for it in the board dts. Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/qcom/qcs404.dtsi | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index ba4152318854..50b3589c7f15 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -191,3 +191,17 @@ &wifi { status = "okay"; }; + +/* PINCTRL - additions to nodes defined in qcs404.dtsi */ + +&blsp1_uart2_default { + rx { + drive-strength = <2>; + bias-disable; + }; + + tx { + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index f3d77e7ee0d2..dd918d35f270 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -272,6 +272,18 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + blsp1_uart2_default: blsp1-uart2-default { + rx { + pins = "gpio18"; + function = "blsp_uart_rx_a2"; + }; + + tx { + pins = "gpio17"; + function = "blsp_uart_tx_a2"; + }; + }; }; gcc: clock-controller@1800000 { @@ -343,6 +355,8 @@ clock-names = "core", "iface"; dmas = <&blsp1_dma 5>, <&blsp1_dma 4>; dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart2_default>; status = "okay"; }; From bf9aa8a4711552781365d5da359150ef45ecb3d8 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sun, 18 Nov 2018 12:01:34 -0800 Subject: [PATCH 243/506] arm64: dts: qcom: qcs404: Define remaining UARTs Add the BLSP2 BAM and add the remaining four UARTs found on the QCS404 platform. Note that these has not been tested. Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 84 ++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index dd918d35f270..9c0b95781861 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -273,6 +273,16 @@ interrupt-controller; #interrupt-cells = <2>; + blsp1_uart0_default: blsp1-uart0-default { + pins = "gpio30", "gpio31", "gpio32", "gpio33"; + function = "blsp_uart0"; + }; + + blsp1_uart1_default: blsp1-uart1-default { + pins = "gpio22", "gpio23"; + function = "blsp_uart1"; + }; + blsp1_uart2_default: blsp1-uart2-default { rx { pins = "gpio18"; @@ -284,6 +294,16 @@ function = "blsp_uart_tx_a2"; }; }; + + blsp1_uart3_default: blsp1-uart3-default { + pins = "gpio82", "gpio83", "gpio84", "gpio85"; + function = "blsp_uart3"; + }; + + blsp2_uart0_default: blsp2-uart0-default { + pins = "gpio26", "gpio27", "gpio28", "gpio29"; + function = "blsp_uart5"; + }; }; gcc: clock-controller@1800000 { @@ -347,6 +367,32 @@ status = "okay"; }; + blsp1_uart0: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 1>, <&blsp1_dma 0>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart0_default>; + status = "disabled"; + }; + + blsp1_uart1: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 3>, <&blsp1_dma 2>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart1_default>; + status = "disabled"; + }; + blsp1_uart2: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b1000 0x200>; @@ -380,6 +426,44 @@ status = "disabled"; }; + blsp1_uart3: serial@78b2000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b2000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 7>, <&blsp1_dma 6>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart3_default>; + status = "disabled"; + }; + + blsp2_dma: dma@7ac4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07ac4000 0x17000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,controlled-remotely = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + blsp2_uart0: serial@7aef000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x07aef000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 1>, <&blsp2_dma 0>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_uart0_default>; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; From 734e6d0252bfdb79805b6bc4f3d18cd683d12c17 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sun, 18 Nov 2018 12:01:35 -0800 Subject: [PATCH 244/506] arm64: dts: qcom: qcs404: Add QUP I2C and SPI nodes Define all six QUP controllers, both as SPI and I2C, allowing boards to enable these as needed. Associated pinmux states are also defined, to require only pinconf states to be specified by the boards, as they are enabled. Note that SPI has not been tested. Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 235 +++++++++++++++++++++++++++ 1 file changed, 235 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 9c0b95781861..76699435c8bd 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -273,6 +273,38 @@ interrupt-controller; #interrupt-cells = <2>; + blsp1_i2c0_default: blsp1-i2c0-default { + pins = "gpio32", "gpio33"; + function = "blsp_i2c0"; + }; + + blsp1_i2c1_default: blsp1-i2c1-default { + pins = "gpio24", "gpio25"; + function = "blsp_i2c1"; + }; + + blsp1_i2c2_default: blsp1-i2c2-default { + sda { + pins = "gpio19"; + function = "blsp_i2c_sda_a2"; + }; + + scl { + pins = "gpio20"; + function = "blsp_i2c_scl_a2"; + }; + }; + + blsp1_i2c3_default: blsp1-i2c3-default { + pins = "gpio84", "gpio85"; + function = "blsp_i2c3"; + }; + + blsp1_i2c4_default: blsp1-i2c4-default { + pins = "gpio117", "gpio118"; + function = "blsp_i2c4"; + }; + blsp1_uart0_default: blsp1-uart0-default { pins = "gpio30", "gpio31", "gpio32", "gpio33"; function = "blsp_uart0"; @@ -300,6 +332,41 @@ function = "blsp_uart3"; }; + blsp2_i2c0_default: blsp2-i2c0-default { + pins = "gpio28", "gpio29"; + function = "blsp_i2c5"; + }; + + blsp1_spi0_default: blsp1-spi0-default { + pins = "gpio30", "gpio31", "gpio32", "gpio33"; + function = "blsp_spi0"; + }; + + blsp1_spi1_default: blsp1-spi1-default { + pins = "gpio22", "gpio23", "gpio24", "gpio25"; + function = "blsp_spi1"; + }; + + blsp1_spi2_default: blsp1-spi2-default { + pins = "gpio17", "gpio18", "gpio19", "gpio20"; + function = "blsp_spi2"; + }; + + blsp1_spi3_default: blsp1-spi3-default { + pins = "gpio82", "gpio83", "gpio84", "gpio85"; + function = "blsp_spi3"; + }; + + blsp1_spi4_default: blsp1-spi4-default { + pins = "gpio37", "gpio38", "gpio117", "gpio118"; + function = "blsp_spi4"; + }; + + blsp2_spi0_default: blsp2-spi0-default { + pins = "gpio26", "gpio27", "gpio28", "gpio29"; + function = "blsp_spi5"; + }; + blsp2_uart0_default: blsp2-uart0-default { pins = "gpio26", "gpio27", "gpio28", "gpio29"; function = "blsp_uart5"; @@ -439,6 +506,146 @@ status = "disabled"; }; + blsp1_i2c0: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b5000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c0_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_spi0: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi0_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c1: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c1_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_spi1: spi@78b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi1_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c2: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c2_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_spi2: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi2_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c3: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c3_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_spi3: spi@78b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b8000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi3_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c4: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c4_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_spi4: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b9000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi4_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp2_dma: dma@7ac4000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07ac4000 0x17000>; @@ -464,6 +671,34 @@ status = "disabled"; }; + blsp2_i2c0: i2c@7af5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07af5000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_i2c0_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_spi0: spi@7af5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07af5000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi0_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; From d027521497592773cd23d016d36975574d3452db Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 25 Jan 2019 11:23:10 +0800 Subject: [PATCH 245/506] ARM: dts: sun8i-a23-a33: Move NAND controller device node to sort by address The NAND controller device node was inserted into the wrong position, probably due to a rebase or merge, as the file's structure does not provide enough context for git to accurately match the previous device node block. Fixes: d7b843df13ea ("ARM: dts: sun8i: add NAND controller node for A23/A33") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index a9c123de5d2c..97ec8b8cec09 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -155,6 +155,19 @@ #dma-cells = <1>; }; + nfc: nand@1c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_NAND>; + reset-names = "ahb"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; @@ -214,21 +227,6 @@ #size-cells = <0>; }; - nfc: nand@1c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_NAND>; - reset-names = "ahb"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - usb_otg: usb@1c19000 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c19000 0x0400>; From 437262c0db5de0f3d351592fe92b581dcaf91869 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 25 Jan 2019 11:23:11 +0800 Subject: [PATCH 246/506] ARM: dts: sun8i-a33: Move display pipeline nodes to a23/a33 common dtsi The display pipeline has the same structure, resources and connections on both the A23 and A33. The differences include: - compatible strings - extra clock, reset control, and IO region for SAT in the backend only found on the A33 - missing ch1 clock for the TCON However, while the A23 has the TCON ch1 clock defined in the CCU, and the channel 1 registers are available, it does not have any means to use channel 1 due to a lack of downstream encoders, and the enable bit for channel 1 is hard-wired to 0 (off). As the MIPI DSI output device is not officially documented, and there are no A23 reference devices to test it, it is not covered by this patch. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 147 ++++++++++++++++++++ arch/arm/boot/dts/sun8i-a33.dtsi | 194 ++++++--------------------- 2 files changed, 185 insertions(+), 156 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 97ec8b8cec09..43fe215e83ea 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -68,6 +68,12 @@ }; }; + de: display-engine { + /* compatible gets set in SoC specific dtsi file */ + allwinner,pipelines = <&fe0>; + status = "disabled"; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -168,6 +174,42 @@ #size-cells = <0>; }; + tcon0: lcd-controller@1c0c000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_LCD>, + <&ccu CLK_LCD_CH0>; + clock-names = "ahb", + "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_LCD>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; @@ -570,6 +612,111 @@ interrupts = ; }; + fe0: display-frontend@1e00000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01e00000 0x20000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, + <&ccu CLK_DRAM_DE_FE>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_BUS_DE_FE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; + }; + + be0: display-backend@1e60000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01e60000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_BUS_DE_BE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + + drc0: drc@1e70000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01e70000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, + <&ccu CLK_DRAM_DRC>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_DRC>; + + assigned-clocks = <&ccu CLK_DRC>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc0>; + }; + }; + }; + }; + rtc: rtc@1f00000 { compatible = "allwinner,sun8i-a23-rtc"; reg = <0x01f00000 0x400>; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 626152c30f50..1111a6498102 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -159,12 +159,6 @@ }; }; - de: display-engine { - compatible = "allwinner,sun8i-a33-display-engine"; - allwinner,pipelines = <&fe0>; - status = "disabled"; - }; - iio-hwmon { compatible = "iio-hwmon"; io-channels = <&ths>; @@ -209,47 +203,6 @@ }; soc { - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun8i-a33-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_LCD>, - <&ccu CLK_LCD_CH0>; - clock-names = "ahb", - "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; - resets = <&ccu RST_BUS_LCD>; - reset-names = "lcd"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_drc0: endpoint@0 { - reg = <0>; - remote-endpoint = <&drc0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_dsi: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi_in_tcon0>; - }; - }; - }; - }; - video-codec@1c0e000 { compatible = "allwinner,sun8i-a33-video-engine"; reg = <0x01c0e000 0x1000>; @@ -339,115 +292,6 @@ status = "disabled"; #phy-cells = <0>; }; - - fe0: display-frontend@1e00000 { - compatible = "allwinner,sun8i-a33-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, - <&ccu CLK_DRAM_DE_FE>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_BUS_DE_FE>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - compatible = "allwinner,sun8i-a33-display-backend"; - reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; - reg-names = "be", "sat"; - interrupts = ; - clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; - clock-names = "ahb", "mod", - "ram", "sat"; - resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; - reset-names = "be", "sat"; - assigned-clocks = <&ccu CLK_DE_BE>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_drc0: endpoint@0 { - reg = <0>; - remote-endpoint = <&drc0_in_be0>; - }; - }; - }; - }; - - drc0: drc@1e70000 { - compatible = "allwinner,sun8i-a33-drc"; - reg = <0x01e70000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, - <&ccu CLK_DRAM_DRC>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_DRC>; - - assigned-clocks = <&ccu CLK_DRC>; - assigned-clock-rates = <300000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - drc0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_drc0>; - }; - }; - - drc0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - drc0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_drc0>; - }; - }; - }; - }; }; thermal-zones { @@ -524,10 +368,37 @@ }; }; +&be0 { + compatible = "allwinner,sun8i-a33-display-backend"; + /* A33 has an extra "SAT" module packed inside the display backend */ + reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; + reg-names = "be", "sat"; + clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; + clock-names = "ahb", "mod", + "ram", "sat"; + resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; + reset-names = "be", "sat"; + assigned-clocks = <&ccu CLK_DE_BE>; + assigned-clock-rates = <300000000>; +}; + &ccu { compatible = "allwinner,sun8i-a33-ccu"; }; +&de { + compatible = "allwinner,sun8i-a33-display-engine"; +}; + +&drc0 { + compatible = "allwinner,sun8i-a33-drc"; +}; + +&fe0 { + compatible = "allwinner,sun8i-a33-display-frontend"; +}; + &mali { operating-points-v2 = <&mali_opp_table>; }; @@ -544,6 +415,17 @@ }; +&tcon0 { + compatible = "allwinner,sun8i-a33-tcon"; +}; + +&tcon0_out { + tcon0_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_tcon0>; + }; +}; + &usb_otg { compatible = "allwinner,sun8i-a33-musb"; }; From 4672f69561898d7e1e179608f6db164f9f8e82fa Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 25 Jan 2019 11:23:12 +0800 Subject: [PATCH 247/506] ARM: dts: sun8i-a23: Add compatible strings to display pipeline device nodes Now that the compatible strings for the display pipeline on the A23 have been added to the bindings, add the corresponding compatibles to the device nodes already in the A23/A33 shared dtsi. While the A23 has the TCON ch1 clock defined in the CCU, and the channel 1 registers are available, it does not have any means to use channel 1 due to a lack of downstream encoders, and the enable bit for channel 1 is hard-wired to 0 (off). Hence the ch1 clock is left out. As the MIPI DSI output device is not officially documented, and there are no reference devices to test it, it is not covered by this patch. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index d00055e9eef5..a5e884a8b2ae 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -62,10 +62,26 @@ }; }; +&be0 { + compatible = "allwinner,sun8i-a23-display-backend"; +}; + &ccu { compatible = "allwinner,sun8i-a23-ccu"; }; +&de { + compatible = "allwinner,sun8i-a23-display-engine"; +}; + +&drc0 { + compatible = "allwinner,sun8i-a23-drc"; +}; + +&fe0 { + compatible = "allwinner,sun8i-a23-display-frontend"; +}; + &pio { compatible = "allwinner,sun8i-a23-pinctrl"; interrupts = , @@ -73,6 +89,10 @@ ; }; +&tcon0 { + compatible = "allwinner,sun8i-a23-tcon"; +}; + &usb_otg { compatible = "allwinner,sun6i-a31-musb"; }; From fe244e4c6a0b5acb2b2049fe792c538e70a0d10b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 25 Jan 2019 11:23:13 +0800 Subject: [PATCH 248/506] ARM: dts: sun8i-q8-common: Enable display pipeline with RGB LCD panel The Q8 design for A23/A33 tablets have an 18-bit RGB LCD panel connected to the LCD interface on the SoC, the DC1SW output on the PMIC providing power for the LCD, and PH7 toggling the reset pin for the panel. This patch adds a device node for the panel, describing the above, and enables the display pipeline. The actual model or compatible string for the panel should be added in the tablet device tree file. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-q8-common.dtsi | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi index 719ad769b837..53104f4ccacc 100644 --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi @@ -49,6 +49,26 @@ ethernet0 = &sdio_wifi; }; + panel: panel { + /* Tablet dts should provide panel compatible */ + backlight = <&backlight>; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + power-supply = <®_dc1sw>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_lcd>; + }; + }; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; /* @@ -64,6 +84,10 @@ }; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -90,6 +114,19 @@ }; }; +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + status = "okay"; +}; + +&tcon0_out { + tcon0_out_lcd: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; +}; + &usbphy { usb1_vbus-supply = <®_dldo1>; }; From 55533921301e83162584f87fe571545056d03e09 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 25 Jan 2019 11:23:14 +0800 Subject: [PATCH 249/506] ARM: dts: sun8i-a23-q8: Set compatible string for LCD panel The Q8 tablets follow the A23/A33 tablet reference design, and normally use a "generic" 800x480 LCD panel. The actual panel may vary between production runs, and there are no visible markings denoting its model. This patch uses a panel that has the same dimensions and timings that are close to what was provided in the vendor fex files. Since there are also A33 Q8 tablets with 1024x600 panels, this patch only sets the compatible string for A23 Q8 tablets. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-q8-tablet.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts index b6958e8f2f01..d4dab7c28398 100644 --- a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts +++ b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts @@ -61,3 +61,7 @@ "Headset Mic", "HBIAS"; status = "okay"; }; + +&panel { + compatible = "bananapi,s070wv20-ct16", "simple-panel"; +}; From 58097b0e05c0dc70345c02cd83117f134574024e Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Wed, 23 Jan 2019 09:30:12 -0500 Subject: [PATCH 250/506] dt-bindings: arm: renesas: Document RZ/A2M EVB Add the RZ/A2M Evaluation board. Signed-off-by: Chris Brandt Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/renesas.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 9e1e07b5192e..cb9b4417e8a1 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -30,6 +30,8 @@ properties: - description: RZ/A2 (R7S9210) items: + - enum: + - renesas,rza2mevb # RZ/A2M Eval Board (RTK7921053S00000BE) - const: renesas,r7s9210 - description: SH-Mobile AG5 (R8A73A00/SH73A0) From 8b229a2a9696fdeaf878f4af5d90034247881e70 Mon Sep 17 00:00:00 2001 From: Mark Zhang Date: Thu, 13 Dec 2018 08:46:54 +0800 Subject: [PATCH 251/506] arm64: tegra: Remove property gpio-keys,name gpio-keys,name is not a valid property supported by gpio-keys driver so remove it from DTS. Signed-off-by: Mark Zhang Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 43cae4798870..6ff64e0f65c5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1724,7 +1724,6 @@ gpio-keys { compatible = "gpio-keys"; - gpio-keys,name = "gpio-keys"; power { label = "Power"; From 46e4b2272e9f572c999bc854b9023f65650be4c0 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 15:16:44 +0800 Subject: [PATCH 252/506] arm64: tegra: Fix register range of apbmisc on Tegra210 Fix the register range of apbmisc, that originally inherited from Tegra124. Reported-by: Mark Zhang Signed-off-by: Joseph Lo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 2205d66b0443..61d2dbe4ce53 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -469,7 +469,7 @@ apbmisc@70000800 { compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ - <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ + <0x0 0x70000008 0x0 0x04>; /* Strapping options */ }; pinmux: pinmux@700008d4 { From dcdeec57c3e02b147e04a02dfbb2b62a9e605257 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 15:16:45 +0800 Subject: [PATCH 253/506] arm64: tegra: Fix IRQ type of PMIC on Smaug Fix IRQ type of PMIC which should be configured as high-level trigger. Signed-off-by: Joseph Lo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 6ff64e0f65c5..83956e6c8817 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1343,7 +1343,7 @@ max77620: max77620@3c { compatible = "maxim,max77620"; reg = <0x3c>; - interrupts = <0 86 IRQ_TYPE_NONE>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; interrupt-controller; From 3e65b2b43132cc188e4830b71e9f232c0acc47fb Mon Sep 17 00:00:00 2001 From: Mark Zhang Date: Fri, 11 Jan 2019 10:38:46 +0800 Subject: [PATCH 254/506] dt-bindings: tegra: Add Shield TV device tree binding documentation Add the device tree binding documentation for NVIDIA Shield TV. Signed-off-by: Mark Zhang Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index fbcde8a7e067..60b38eb5c61a 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -87,9 +87,11 @@ properties: - const: nvidia,tegra124 - items: - enum: + - nvidia,darcy - nvidia,p2371-0000 - nvidia,p2371-2180 - nvidia,p2571 + - nvidia,p2894-0050-a08 - const: nvidia,tegra210 - items: - enum: From 968ebd84271b3d8b364ac52ddca6d23ee86639d4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Jan 2019 13:04:28 +0100 Subject: [PATCH 255/506] arm64: tegra: Use GIC_SPI for PMIC interrupt on Smaug Instead of hardcoding the value (0), reuse the symbolic name from dt-bindings/interrupt-controller/arm-gic.h. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 83956e6c8817..ed04526f6252 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1343,7 +1343,7 @@ max77620: max77620@3c { compatible = "maxim,max77620"; reg = <0x3c>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #interrupt-cells = <2>; interrupt-controller; From dd03aeef17ba00bb1b0a5fb7dec3d42125707d12 Mon Sep 17 00:00:00 2001 From: Mark Zhang Date: Fri, 11 Jan 2019 10:38:45 +0800 Subject: [PATCH 256/506] arm64: tegra: Add support for NVIDIA Shield TV Add initial device-tree support for NVIDIA Shield TV (a.k.a. Darcy) based upon Tegra210 SoC with 3 GiB of LPDDR4 RAM. Signed-off-by: Mark Zhang Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/Makefile | 1 + .../dts/nvidia/tegra210-p2894-0050-a08.dts | 9 +++ .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 77 +++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210-p2894-0050-a08.dts create mode 100644 arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index 7c13d7df484e..6b8ab5568481 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -4,5 +4,6 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb +dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894-0050-a08.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2894-0050-a08.dts new file mode 100644 index 000000000000..7ffb351b5882 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894-0050-a08.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra210-p2894.dtsi" + +/ { + model = "NVIDIA Shield TV"; + compatible = "nvidia,p2894-0050-a08", "nvidia,darcy", "nvidia,tegra210"; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi new file mode 100644 index 000000000000..ac52286ab9ab --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra210.dtsi" + +/ { + aliases { + serial0 = &uarta; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + serial@70006000 { + status = "okay"; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + status = "okay"; + }; + + sdhci@700b0600 { + bus-width = <8>; + non-removable; + status = "okay"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + cpus { + cpu@0 { + enable-method = "psci"; + }; + + cpu@1 { + enable-method = "psci"; + }; + + cpu@2 { + enable-method = "psci"; + }; + + cpu@3 { + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; +}; From 7152879d385d0a1ab5859e62c7619ac5668dfa22 Mon Sep 17 00:00:00 2001 From: Mark Zhang Date: Fri, 11 Jan 2019 10:38:47 +0800 Subject: [PATCH 257/506] arm64: tegra: Add gpio-keys nodes for Darcy Add gpio-keys nodes for the power button. Signed-off-by: Mark Zhang Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index ac52286ab9ab..65372263d3a8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 +#include +#include #include "tegra210.dtsi" / { @@ -52,6 +54,20 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + status = "okay"; + + power { + debounce-interval = <30>; + gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; + label = "Power"; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + }; + cpus { cpu@0 { enable-method = "psci"; From 6ec2c7161f36a0d3e8881d818febf9034012e1fe Mon Sep 17 00:00:00 2001 From: Mark Zhang Date: Fri, 11 Jan 2019 10:38:48 +0800 Subject: [PATCH 258/506] arm64: tegra: Add pinmux for Darcy board Add pinmux node for Tegra210 Darcy board. Signed-off-by: Mark Zhang Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 1300 +++++++++++++++++ 1 file changed, 1300 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 65372263d3a8..7e1801e5ca6d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -2,6 +2,7 @@ #include #include +#include #include "tegra210.dtsi" / { @@ -19,6 +20,1305 @@ reg = <0x0 0x80000000 0x0 0xc0000000>; }; + pinmux: pinmux@700008d4 { + status = "okay"; + pinctrl-names = "boot"; + pinctrl-0 = <&state_boot>; + + state_boot: pinmux { + pex_l0_rst_n_pa0 { + nvidia,pins = "pex_l0_rst_n_pa0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + pex_l0_clkreq_n_pa1 { + nvidia,pins = "pex_l0_clkreq_n_pa1"; + nvidia,function = "pe0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + pex_wake_n_pa2 { + nvidia,pins = "pex_wake_n_pa2"; + nvidia,function = "pe"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + pex_l1_rst_n_pa3 { + nvidia,pins = "pex_l1_rst_n_pa3"; + nvidia,function = "pe1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + pex_l1_clkreq_n_pa4 { + nvidia,pins = "pex_l1_clkreq_n_pa4"; + nvidia,function = "pe1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + sata_led_active_pa5 { + nvidia,pins = "sata_led_active_pa5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pa6 { + nvidia,pins = "pa6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dap1_fs_pb0 { + nvidia,pins = "dap1_fs_pb0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dap1_din_pb1 { + nvidia,pins = "dap1_din_pb1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dap1_dout_pb2 { + nvidia,pins = "dap1_dout_pb2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dap1_sclk_pb3 { + nvidia,pins = "dap1_sclk_pb3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spi2_mosi_pb4 { + nvidia,pins = "spi2_mosi_pb4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spi2_miso_pb5 { + nvidia,pins = "spi2_miso_pb5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spi2_sck_pb6 { + nvidia,pins = "spi2_sck_pb6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spi2_cs0_pb7 { + nvidia,pins = "spi2_cs0_pb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spi1_mosi_pc0 { + nvidia,pins = "spi1_mosi_pc0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spi1_miso_pc1 { + nvidia,pins = "spi1_miso_pc1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spi1_sck_pc2 { + nvidia,pins = "spi1_sck_pc2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spi1_cs0_pc3 { + nvidia,pins = "spi1_cs0_pc3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spi1_cs1_pc4 { + nvidia,pins = "spi1_cs1_pc4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spi4_sck_pc5 { + nvidia,pins = "spi4_sck_pc5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spi4_cs0_pc6 { + nvidia,pins = "spi4_cs0_pc6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spi4_mosi_pc7 { + nvidia,pins = "spi4_mosi_pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spi4_miso_pd0 { + nvidia,pins = "spi4_miso_pd0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart3_tx_pd1 { + nvidia,pins = "uart3_tx_pd1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart3_rx_pd2 { + nvidia,pins = "uart3_rx_pd2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart3_rts_pd3 { + nvidia,pins = "uart3_rts_pd3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart3_cts_pd4 { + nvidia,pins = "uart3_cts_pd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dmic1_clk_pe0 { + nvidia,pins = "dmic1_clk_pe0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dmic1_dat_pe1 { + nvidia,pins = "dmic1_dat_pe1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dmic2_clk_pe2 { + nvidia,pins = "dmic2_clk_pe2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dmic2_dat_pe3 { + nvidia,pins = "dmic2_dat_pe3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dmic3_clk_pe4 { + nvidia,pins = "dmic3_clk_pe4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dmic3_dat_pe5 { + nvidia,pins = "dmic3_dat_pe5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pe6 { + nvidia,pins = "pe6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pe7 { + nvidia,pins = "pe7"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen3_i2c_scl_pf0 { + nvidia,pins = "gen3_i2c_scl_pf0"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + gen3_i2c_sda_pf1 { + nvidia,pins = "gen3_i2c_sda_pf1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + uart2_tx_pg0 { + nvidia,pins = "uart2_tx_pg0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart2_rx_pg1 { + nvidia,pins = "uart2_rx_pg1"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart2_rts_pg2 { + nvidia,pins = "uart2_rts_pg2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart2_cts_pg3 { + nvidia,pins = "uart2_cts_pg3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + wifi_en_ph0 { + nvidia,pins = "wifi_en_ph0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + wifi_rst_ph1 { + nvidia,pins = "wifi_rst_ph1"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + wifi_wake_ap_ph2 { + nvidia,pins = "wifi_wake_ap_ph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + ap_wake_bt_ph3 { + nvidia,pins = "ap_wake_bt_ph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + bt_rst_ph4 { + nvidia,pins = "bt_rst_ph4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + bt_wake_ap_ph5 { + nvidia,pins = "bt_wake_ap_ph5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + ph6 { + nvidia,pins = "ph6"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + ap_wake_nfc_ph7 { + nvidia,pins = "ap_wake_nfc_ph7"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + nfc_en_pi0 { + nvidia,pins = "nfc_en_pi0"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + nfc_int_pi1 { + nvidia,pins = "nfc_int_pi1"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gps_en_pi2 { + nvidia,pins = "gps_en_pi2"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gps_rst_pi3 { + nvidia,pins = "gps_rst_pi3"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart4_tx_pi4 { + nvidia,pins = "uart4_tx_pi4"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart4_rx_pi5 { + nvidia,pins = "uart4_rx_pi5"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart4_rts_pi6 { + nvidia,pins = "uart4_rts_pi6"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart4_cts_pi7 { + nvidia,pins = "uart4_cts_pi7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pj0 { + nvidia,pins = "gen1_i2c_sda_pj0"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + gen1_i2c_scl_pj1 { + nvidia,pins = "gen1_i2c_scl_pj1"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + gen2_i2c_scl_pj2 { + nvidia,pins = "gen2_i2c_scl_pj2"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + gen2_i2c_sda_pj3 { + nvidia,pins = "gen2_i2c_sda_pj3"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + dap4_fs_pj4 { + nvidia,pins = "dap4_fs_pj4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dap4_din_pj5 { + nvidia,pins = "dap4_din_pj5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dap4_dout_pj6 { + nvidia,pins = "dap4_dout_pj6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dap4_sclk_pj7 { + nvidia,pins = "dap4_sclk_pj7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pk0 { + nvidia,pins = "pk0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pk1 { + nvidia,pins = "pk1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pk2 { + nvidia,pins = "pk2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pk3 { + nvidia,pins = "pk3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pk4 { + nvidia,pins = "pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pk5 { + nvidia,pins = "pk5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pk6 { + nvidia,pins = "pk6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pk7 { + nvidia,pins = "pk7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pl0 { + nvidia,pins = "pl0"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pl1 { + nvidia,pins = "pl1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc1_clk_pm0 { + nvidia,pins = "sdmmc1_clk_pm0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc1_cmd_pm1 { + nvidia,pins = "sdmmc1_cmd_pm1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc1_dat3_pm2 { + nvidia,pins = "sdmmc1_dat3_pm2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc1_dat2_pm3 { + nvidia,pins = "sdmmc1_dat2_pm3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc1_dat1_pm4 { + nvidia,pins = "sdmmc1_dat1_pm4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc1_dat0_pm5 { + nvidia,pins = "sdmmc1_dat0_pm5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_clk_pp0 { + nvidia,pins = "sdmmc3_clk_pp0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_cmd_pp1 { + nvidia,pins = "sdmmc3_cmd_pp1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_dat3_pp2 { + nvidia,pins = "sdmmc3_dat3_pp2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_dat2_pp3 { + nvidia,pins = "sdmmc3_dat2_pp3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_dat1_pp4 { + nvidia,pins = "sdmmc3_dat1_pp4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_dat0_pp5 { + nvidia,pins = "sdmmc3_dat0_pp5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam1_mclk_ps0 { + nvidia,pins = "cam1_mclk_ps0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam2_mclk_ps1 { + nvidia,pins = "cam2_mclk_ps1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_scl_ps2 { + nvidia,pins = "cam_i2c_scl_ps2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + cam_i2c_sda_ps3 { + nvidia,pins = "cam_i2c_sda_ps3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + cam_rst_ps4 { + nvidia,pins = "cam_rst_ps4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_af_en_ps5 { + nvidia,pins = "cam_af_en_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_flash_en_ps6 { + nvidia,pins = "cam_flash_en_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam1_pwdn_ps7 { + nvidia,pins = "cam1_pwdn_ps7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam2_pwdn_pt0 { + nvidia,pins = "cam2_pwdn_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam1_strobe_pt1 { + nvidia,pins = "cam1_strobe_pt1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart1_tx_pu0 { + nvidia,pins = "uart1_tx_pu0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart1_rx_pu1 { + nvidia,pins = "uart1_rx_pu1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart1_rts_pu2 { + nvidia,pins = "uart1_rts_pu2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + uart1_cts_pu3 { + nvidia,pins = "uart1_cts_pu3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + lcd_bl_pwm_pv0 { + nvidia,pins = "lcd_bl_pwm_pv0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + lcd_bl_en_pv1 { + nvidia,pins = "lcd_bl_en_pv1"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + lcd_rst_pv2 { + nvidia,pins = "lcd_rst_pv2"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + lcd_gpio1_pv3 { + nvidia,pins = "lcd_gpio1_pv3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + lcd_gpio2_pv4 { + nvidia,pins = "lcd_gpio2_pv4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + ap_ready_pv5 { + nvidia,pins = "ap_ready_pv5"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + touch_rst_pv6 { + nvidia,pins = "touch_rst_pv6"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + touch_clk_pv7 { + nvidia,pins = "touch_clk_pv7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + modem_wake_ap_px0 { + nvidia,pins = "modem_wake_ap_px0"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + touch_int_px1 { + nvidia,pins = "touch_int_px1"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + motion_int_px2 { + nvidia,pins = "motion_int_px2"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + als_prox_int_px3 { + nvidia,pins = "als_prox_int_px3"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + temp_alert_px4 { + nvidia,pins = "temp_alert_px4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + button_power_on_px5 { + nvidia,pins = "button_power_on_px5"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + button_vol_up_px6 { + nvidia,pins = "button_vol_up_px6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + button_vol_down_px7 { + nvidia,pins = "button_vol_down_px7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + button_slide_sw_py0 { + nvidia,pins = "button_slide_sw_py0"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + button_home_py1 { + nvidia,pins = "button_home_py1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + lcd_te_py2 { + nvidia,pins = "lcd_te_py2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_scl_py3 { + nvidia,pins = "pwr_i2c_scl_py3"; + nvidia,function = "i2cpmu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + pwr_i2c_sda_py4 { + nvidia,pins = "pwr_i2c_sda_py4"; + nvidia,function = "i2cpmu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + clk_32k_out_py5 { + nvidia,pins = "clk_32k_out_py5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pz0 { + nvidia,pins = "pz0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pz1 { + nvidia,pins = "pz1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pz2 { + nvidia,pins = "pz2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pz3 { + nvidia,pins = "pz3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pz4 { + nvidia,pins = "pz4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pz5 { + nvidia,pins = "pz5"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dap2_fs_paa0 { + nvidia,pins = "dap2_fs_paa0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dap2_sclk_paa1 { + nvidia,pins = "dap2_sclk_paa1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dap2_din_paa2 { + nvidia,pins = "dap2_din_paa2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dap2_dout_paa3 { + nvidia,pins = "dap2_dout_paa3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + aud_mclk_pbb0 { + nvidia,pins = "aud_mclk_pbb0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + dvfs_clk_pbb2 { + nvidia,pins = "dvfs_clk_pbb2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gpio_x1_aud_pbb3 { + nvidia,pins = "gpio_x1_aud_pbb3"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gpio_x3_aud_pbb4 { + nvidia,pins = "gpio_x3_aud_pbb4"; + nvidia,function = "rsvd0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + hdmi_cec_pcc0 { + nvidia,pins = "hdmi_cec_pcc0"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + hdmi_int_dp_hpd_pcc1 { + nvidia,pins = "hdmi_int_dp_hpd_pcc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + spdif_out_pcc2 { + nvidia,pins = "spdif_out_pcc2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + spdif_in_pcc3 { + nvidia,pins = "spdif_in_pcc3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + usb_vbus_en0_pcc4 { + nvidia,pins = "usb_vbus_en0_pcc4"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + usb_vbus_en1_pcc5 { + nvidia,pins = "usb_vbus_en1_pcc5"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + dp_hpd0_pcc6 { + nvidia,pins = "dp_hpd0_pcc6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pcc7 { + nvidia,pins = "pcc7"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,io-hv = ; + }; + spi2_cs1_pdd0 { + nvidia,pins = "spi2_cs1_pdd0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + qspi_sck_pee0 { + nvidia,pins = "qspi_sck_pee0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + qspi_cs_n_pee1 { + nvidia,pins = "qspi_cs_n_pee1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + qspi_io0_pee2 { + nvidia,pins = "qspi_io0_pee2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + qspi_io1_pee3 { + nvidia,pins = "qspi_io1_pee3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + qspi_io2_pee4 { + nvidia,pins = "qspi_io2_pee4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + qspi_io3_pee5 { + nvidia,pins = "qspi_io3_pee5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "core"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "jtag"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + clk_req { + nvidia,pins = "clk_req"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + shutdown { + nvidia,pins = "shutdown"; + nvidia,function = "shutdown"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + }; + }; + serial@70006000 { status = "okay"; }; From 51e5e0182c59f8e4ed4922a77c5b87e2a5c0d84f Mon Sep 17 00:00:00 2001 From: Mark Zhang Date: Fri, 11 Jan 2019 10:38:49 +0800 Subject: [PATCH 259/506] arm64: tegra: Add regulators for Tegra210 Darcy Add regulators to the Tegra210 Darcy DTS file including support for the MAX77620 PMIC. Signed-off-by: Mark Zhang Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 465 ++++++++++++++++++ 1 file changed, 465 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 7e1801e5ca6d..3ddf173ccc18 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -2,6 +2,7 @@ #include #include +#include #include #include "tegra210.dtsi" @@ -1323,6 +1324,250 @@ status = "okay"; }; + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + max77620: max77620@3c { + compatible = "maxim,max77620"; + reg = <0x3c>; + interrupts = ; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&max77620_default>; + + max77620_default: pinmux@0 { + pin_gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "fps-out"; + drive-push-pull = <1>; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <7>; + maxim,active-fps-power-down-slot = <0>; + }; + + pin_gpio2_3 { + pins = "gpio2", "gpio3"; + function = "fps-out"; + drive-open-drain = <1>; + maxim,active-fps-source = ; + }; + + pin_gpio4 { + pins = "gpio4"; + function = "32k-out1"; + }; + + pin_gpio5_6_7 { + pins = "gpio5", "gpio6", "gpio7"; + function = "gpio"; + drive-push-pull = <1>; + }; + + pin_gpio2 { + maxim,active-fps-source = ; + }; + + pin_gpio3 { + maxim,active-fps-source = ; + }; + }; + + spmic-default-output-high { + gpio-hog; + output-high; + gpios = <2 GPIO_ACTIVE_HIGH 7 GPIO_ACTIVE_HIGH>; + }; + + fps { + #address-cells = <1>; + #size-cells = <0>; + + fps0 { + reg = <0>; + maxim,fps-event-source = ; + }; + + fps1 { + reg = <1>; + maxim,fps-event-source = ; + maxim,device-state-on-disabled-event = ; + }; + + fps2 { + reg = <2>; + maxim,fps-event-source = ; + }; + }; + + regulators { + in-ldo0-1-supply = <&max77620_sd2>; + in-ldo7-8-supply = <&max77620_sd2>; + + max77620_sd0: sd0 { + regulator-name = "vdd-core"; + regulator-enable-ramp-delay = <146>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <27500>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-source = ; + }; + + max77620_sd1: sd1 { + regulator-name = "vddio-ddr"; + regulator-enable-ramp-delay = <130>; + regulator-ramp-delay = <27500>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + + max77620_sd2: sd2 { + regulator-name = "vdd-pre-reg"; + regulator-enable-ramp-delay = <176>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-ramp-delay = <27500>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + maxim,suspend-fps-source = ; + }; + + max77620_sd3: sd3 { + regulator-name = "vdd-1v8"; + regulator-enable-ramp-delay = <242>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <27500>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + + max77620_ldo0: ldo0 { + regulator-name = "avdd-sys"; + regulator-enable-ramp-delay = <26>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <100000>; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + + max77620_ldo1: ldo1 { + regulator-name = "vdd-pex"; + regulator-enable-ramp-delay = <22>; + regulator-min-microvolt = <1075000>; + regulator-max-microvolt = <1075000>; + regulator-ramp-delay = <100000>; + regulator-always-on; + + maxim,active-fps-source = ; + }; + + max77620_ldo2: ldo2 { + regulator-name = "vddio-sdmmc3"; + regulator-enable-ramp-delay = <62>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <100000>; + + maxim,active-fps-source = ; + }; + + max77620_ldo3: ldo3 { + regulator-name = "vdd-3v3-eth"; + regulator-enable-ramp-delay = <50>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <100000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + + max77620_ldo4: ldo4 { + regulator-name = "vdd-rtc"; + regulator-enable-ramp-delay = <22>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <100000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + + max77620_ldo5: ldo5 { + regulator-name = "avdd-ts-hv"; + regulator-enable-ramp-delay = <62>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <100000>; + + maxim,active-fps-source = ; + }; + + max77620_ldo6: ldo6 { + regulator-name = "vdd-ts"; + regulator-enable-ramp-delay = <36>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <100000>; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + + max77620_ldo7: ldo7 { + regulator-name = "vdd-gen-pll-edp"; + regulator-enable-ramp-delay = <24>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <100000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + maxim,suspend-fps-source = ; + }; + + max77620_ldo8: ldo8 { + regulator-name = "vdd-hdmi-dp"; + regulator-enable-ramp-delay = <22>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <100000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = ; + }; + }; + }; + }; + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <0>; @@ -1390,4 +1635,224 @@ compatible = "arm,psci-1.0"; method = "smc"; }; + + regulators { + compatible = "simple-bus"; + device_type = "fixed-regulators"; + #address-cells = <1>; + #size-cells = <0>; + + battery_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd-ac-bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd-3v3"; + regulator-enable-ramp-delay = <160>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + gpio = <&max77620 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + max77620_gpio7: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "max77620-gpio7"; + regulator-enable-ramp-delay = <240>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&max77620_ldo0>; + regulator-always-on; + regulator-boot-on; + + gpio = <&max77620 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + lcd_bl_en: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "lcd-bl-en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + + gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + en_vdd_sd: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "en-vdd-sd"; + regulator-enable-ramp-delay = <472>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3>; + + gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + en_vdd_cam: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "en-vdd-cam"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_sys_boost: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "vdd-sys-boost"; + regulator-enable-ramp-delay = <3090>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + + gpio = <&max77620 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_hdmi: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "vdd-hdmi"; + regulator-enable-ramp-delay = <468>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_sys_boost>; + regulator-boot-on; + + gpio = <&gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + en_vdd_cpu_fixed: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "vdd-cpu-fixed"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vdd_aux_3v3: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "aux-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_snsr_pm: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "snsr_pm"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + enable-active-high; + }; + + vdd_usb_5v0: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + status = "disabled"; + regulator-name = "vdd-usb-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_3v3>; + + enable-active-high; + }; + + vdd_cdc_1v2_aud: regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + status = "disabled"; + regulator-name = "vdd_cdc_1v2_aud"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + startup-delay-us = <250000>; + + enable-active-high; + }; + + vdd_disp_3v0: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "vdd-disp-3v0"; + regulator-enable-ramp-delay = <232>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + + gpio = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_fan: regulator@13 { + compatible = "regulator-fixed"; + reg = <13>; + regulator-name = "vdd-fan"; + regulator-enable-ramp-delay = <284>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_vbus1: regulator@14 { + compatible = "regulator-fixed"; + reg = <14>; + regulator-name = "usb-vbus1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + }; + + usb_vbus2: regulator@15 { + compatible = "regulator-fixed"; + reg = <15>; + regulator-name = "usb-vbus2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + }; + + vdd_3v3_eth: regulator@16 { + compatible = "regulator-fixed"; + reg = <16>; + regulator-name = "vdd-3v3-eth-a02"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + }; + }; }; From 35a4f89cd4731ac6ec985cd29ddc1630903006b7 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Thu, 24 Jan 2019 09:28:59 +0100 Subject: [PATCH 260/506] arm64: dts: zcu100-revC: Give wifi some time after power-on Somewhere along recent changes to power control of the wl1831, power-on became very unreliable on the Ultra96, failing like this: wl1271_sdio: probe of mmc2:0001:1 failed with error -16 wl1271_sdio: probe of mmc2:0001:2 failed with error -16 After playing with some dt parameters and comparing to other users of this chip, it turned out we need some power-on delay to make things stable again. In contrast to those other users which define 200 ms, Ultra96 is already happy with 10 ms. Fixes: 5869ba0653b9 ("arm64: zynqmp: Add support for Xilinx zcu100-revC") Signed-off-by: Jan Kiszka Acked-by: Ulf Hansson Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 13a0a028df98..e5699d0d91e4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -101,6 +101,7 @@ sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + post-power-on-delay-ms = <10>; }; }; From 5eef17ee764d20b1c8cec96825e5ef15020fd006 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 16 Jan 2019 13:26:02 +0100 Subject: [PATCH 261/506] arm64: tegra: p2972: Sort nodes properly At some point during rebases these were shuffled around. Put them in the right order again (sorted by unit-address). Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index adf351010ff5..34a7044927fd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -11,12 +11,16 @@ compatible = "nvidia,p2972-0000", "nvidia,tegra194"; cbb { + ddc: i2c@31c0000 { + status = "okay"; + }; + /* SDMMC1 (SD/MMC) */ sdhci@3400000 { status = "okay"; }; - ddc: i2c@31c0000 { + hda@3510000 { status = "okay"; }; @@ -24,10 +28,6 @@ status = "okay"; }; - hda@3510000 { - status = "okay"; - }; - host1x@13e00000 { display-hub@15200000 { status = "okay"; From be4f0dd347ad4036099d7da423ccdd65d3c9775b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Jan 2019 11:14:49 +0100 Subject: [PATCH 262/506] arm64: tegra: p2597: Sort nodes by unit-address Some of these nodes got inserted in the wrong place. Restore ordering by unit-address. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index a96e6ee70c21..f4bb48d87df7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1303,6 +1303,15 @@ clock-frequency = <100000>; }; + sata@70020000 { + status = "okay"; + phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; + }; + + hda@70030000 { + status = "okay"; + }; + usb@70090000 { phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, @@ -1325,15 +1334,6 @@ status = "okay"; }; - sata@70020000 { - status = "okay"; - phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; - }; - - hda@70030000 { - status = "okay"; - }; - padctl@7009f000 { status = "okay"; From caca0482e7ea2e90f8bebe5477ca625621e031a6 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 23 Jan 2019 12:39:42 +0100 Subject: [PATCH 263/506] arm64: tegra: p3310: Use TEGRA186_ prefix for GPIO names The new prefix allows the GPIOs to be uniquely identified on a per-chip basis, which makes it easier to distinguish Tegra186 specific GPIOs from those of later chips such as Tegra194 which supports a very different set of GPIOs. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index b539561e7877..89a2da46efae 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -34,7 +34,8 @@ ethernet@2490000 { status = "okay"; - phy-reset-gpios = <&gpio TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>; + phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4) + GPIO_ACTIVE_LOW>; phy-handle = <&phy>; phy-mode = "rgmii"; @@ -46,7 +47,8 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; }; }; }; @@ -91,8 +93,8 @@ /* SDMMC1 (SD/MMC) */ sdhci@3400000 { - cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>; vqmmc-supply = <&vddio_sdmmc1>; }; From d428f35d959c951244970c5f142616802f39de33 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 23 Jan 2019 12:39:41 +0100 Subject: [PATCH 264/506] arm64: tegra: p2771-0000: Use TEGRA186_ prefix for GPIO names The new prefix allows the GPIOs to be uniquely identified on a per-chip basis, which makes it easier to distinguish Tegra186 specific GPIOs from those of later chips such as Tegra194 which supports a very different set of GPIOs. Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra186-p2771-0000.dts | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 65487eee2ce6..0f3c6cebb049 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -26,7 +26,8 @@ reg = <0x74>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; #gpio-cells = <2>; gpio-controller; @@ -37,7 +38,8 @@ reg = <0x77>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; #gpio-cells = <2>; gpio-controller; @@ -108,7 +110,8 @@ hdmi-supply = <&vdd_hdmi>; nvidia,ddc-i2c-bus = <&ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_MAIN_GPIO(P, 1) GPIO_ACTIVE_LOW>; + nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1) + GPIO_ACTIVE_LOW>; }; dpaux@155c0000 { @@ -121,7 +124,7 @@ power { label = "Power"; - gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 0) + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; @@ -132,7 +135,7 @@ volume-up { label = "Volume Up"; - gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 1) + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; @@ -141,7 +144,7 @@ volume-down { label = "Volume Down"; - gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 2) + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; @@ -158,7 +161,8 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>; + gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) + GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vdd_3v3_sys>; From 0e79cb7010f237a1d63b74cbfa51783eb162a3b2 Mon Sep 17 00:00:00 2001 From: Timo Alho Date: Thu, 24 Jan 2019 19:03:55 +0200 Subject: [PATCH 265/506] dt-bindings: firmware: Add bindings for Tegra210 BPMP The BPMP is a specific processor in Tegra210 chip, which is designed for boot process handling, assisting in entering deep low power states (suspend to ram), and offloading DRAM memory clock scaling on some platforms. Signed-off-by: Timo Alho Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../firmware/nvidia,tegra210-bpmp.txt | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra210-bpmp.txt diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra210-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra210-bpmp.txt new file mode 100644 index 000000000000..68d814e8c09d --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra210-bpmp.txt @@ -0,0 +1,35 @@ +NVIDIA Tegra210 Boot and Power Management Processor (BPMP) + +The Boot and Power Management Processor (BPMP) is a co-processor found +in Tegra210 SoC. It is designed to handle the early stages of the boot +process as well as to assisting in entering deep low power state +(suspend to ram), and also offloading DRAM memory clock scaling on +some platforms. The binding document defines the resources that would +be used by the BPMP T210 firmware driver, which can create the +interprocessor communication (IPC) between the CPU and BPMP. + +Required properties: +- compatible + Array of strings + One of: + - "nvidia,tegra210-bpmp" +- reg: physical base address and length for HW synchornization primitives + 1) base address and length to Tegra 'atomics' hardware + 2) base address and length to Tegra 'semaphore' hardware +- interrupts: specifies the interrupt number for receiving messages ("rx") + and for triggering messages ("tx") + +Optional properties: +- #clock-cells : Should be 1 for platforms where DRAM clock control is + offloaded to bpmp. + +Example: + +bpmp@70016000 { + compatible = "nvidia,tegra210-bpmp"; + reg = <0x0 0x70016000 0x0 0x2000 + 0x0 0x60001000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "tx", "rx"; +}; From 22daf9104902456654da984a31989301b4151967 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Jan 2019 15:47:40 +0100 Subject: [PATCH 266/506] dt-bindings: firmware: tegra186-bpmp: Remove name property This property is not used by device trees and was likely supposed to be a hint as to what the BPMP node should be named, rather than describing a property of the BPMP node. Suggested-by: Jon Hunter Signed-off-by: Thierry Reding --- .../devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt index 0c10802c8327..ff380dadb5f9 100644 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt @@ -8,7 +8,6 @@ which can create the interprocessor communication (IPC) between the CPU and BPMP. Required properties: -- name : Should be bpmp - compatible Array of strings One of: From ec33745bccc8f336957c751f4153421cc9ef5a54 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 24 Jan 2019 13:22:57 +0100 Subject: [PATCH 267/506] ARM: dts: exynos: Fix pinctrl definition for eMMC RTSN line on Odroid X2/U3 Commit 225da7e65a03 ("ARM: dts: add eMMC reset line for exynos4412-odroid-common") added MMC power sequence for eMMC card of Odroid X2/U3. It reused generic sd1_cd pin control configuration node and only disabled pull-up. However that time the pinctrl configuration was not applied during MMC power sequence driver initialization. This has been changed later by commit d97a1e5d7cd2 ("mmc: pwrseq: convert to proper platform device"). It turned out then, that the provided pinctrl configuration is not correct, because the eMMC_RTSN line is being re-configured as 'special function/card detect function for mmc1 controller' not the simple 'output', thus the power sequence driver doesn't really set the pin value. This in effect broke the reboot of Odroid X2/U3 boards. Fix this by providing separate node with eMMC_RTSN pin configuration. Cc: Reported-by: Markus Reichl Suggested-by: Ulf Hansson Fixes: 225da7e65a03 ("ARM: dts: add eMMC reset line for exynos4412-odroid-common") Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 24bcad3dfba9..08d3a0a7b4eb 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -49,7 +49,7 @@ }; emmc_pwrseq: pwrseq { - pinctrl-0 = <&sd1_cd>; + pinctrl-0 = <&emmc_rstn>; pinctrl-names = "default"; compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>; @@ -165,12 +165,6 @@ cpu0-supply = <&buck2_reg>; }; -/* RSTN signal for eMMC */ -&sd1_cd { - samsung,pin-pud = ; - samsung,pin-drv = ; -}; - &pinctrl_1 { gpio_power_key: power_key { samsung,pins = "gpx1-3"; @@ -188,6 +182,11 @@ samsung,pins = "gpx3-7"; samsung,pin-pud = ; }; + + emmc_rstn: emmc-rstn { + samsung,pins = "gpk1-2"; + samsung,pin-pud = ; + }; }; &ehci { From ee65af7f9f425078147107a92e3dc268cad1d591 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 17 Nov 2016 04:06:15 +0200 Subject: [PATCH 268/506] ARM: dts: lpc435x: remove address and size cells from gpio-keys-polled nodes The change removes redundant #address-cells and #size-cells properties from gpio-keys-polled compatible device nodes found in lpc4357-ea4357-devkit and lpc4350-hitex-eval board DTS files. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc4350-hitex-eval.dts | 2 -- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/lpc4350-hitex-eval.dts index 8b973f537d3a..93d0c2e99e7c 100644 --- a/arch/arm/boot/dts/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/lpc4350-hitex-eval.dts @@ -40,8 +40,6 @@ pca_buttons { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; autorepeat; diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts index 02b23fa29d75..224f80a4a31d 100644 --- a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts @@ -57,8 +57,6 @@ compatible = "gpio-keys-polled"; pinctrl-names = "default"; pinctrl-0 = <&gpio_joystick_pins>; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; autorepeat; From 79164c99db284d07aa4e84e57b469d225609799c Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 22 Jan 2019 16:35:46 +0800 Subject: [PATCH 269/506] arm64: dts: rockchip: clean up the abuse of disable-wp The mmc.txt didn't explicitly say disable-wp is for SD card slot only, but that is what it was designed for in the first place. Remove all disable-wp from emmc or sdio controller. Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 1 - arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts | 1 - arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi | 1 - arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts | 1 - arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts | 1 - arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 1 - arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 1 - arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts | 1 - 8 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi index 4de089149c50..e96eb62f362b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi @@ -116,7 +116,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; mmc-pwrseq = <&emmc_pwrseq>; non-removable; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts index 6b9b1ac1994c..8fa550cbd1a4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts @@ -78,7 +78,6 @@ bus-width = <8>; cap-mmc-highspeed; clock-frequency = <150000000>; - disable-wp; non-removable; vmmc-supply = <&vcc_io>; vqmmc-supply = <&vcc18_flash>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi index 1315972412df..1b35d612b660 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi @@ -139,7 +139,6 @@ &emmc { bus-width = <8>; clock-frequency = <150000000>; - disable-wp; mmc-hs200-1_8v; non-removable; vmmc-supply = <&vcc33_io>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts index 96147d93dd1d..f5aa3cad67c5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts @@ -161,7 +161,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; mmc-pwrseq = <&emmc_pwrseq>; mmc-hs200-1_2v; mmc-hs200-1_8v; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts index fc1bf078a41f..41edcfd53184 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts @@ -48,7 +48,6 @@ bus-width = <8>; cap-mmc-highspeed; clock-frequency = <150000000>; - disable-wp; mmc-hs200-1_8v; no-sdio; no-sd; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts index 7452bedf1a7e..d34064c65f10 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts @@ -149,7 +149,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; mmc-pwrseq = <&emmc_pwrseq>; non-removable; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index 2d304d2df62e..cf6cc4e7d315 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -553,7 +553,6 @@ bus-width = <4>; cap-sd-highspeed; cap-sdio-irq; - disable-wp; keep-power-in-suspend; mmc-pwrseq = <&sdio_pwrseq>; non-removable; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts index 0b8f1edbd746..d5abf7d90f91 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts @@ -219,7 +219,6 @@ cap-sd-highspeed; cap-sdio-irq; clock-frequency = <50000000>; - disable-wp; keep-power-in-suspend; max-frequency = <50000000>; mmc-pwrseq = <&sdio_pwrseq>; From e6b97a47b5b9512828859778acafd3fe107b395e Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 22 Jan 2019 16:35:47 +0800 Subject: [PATCH 270/506] ARM: dts: rockchip: clean up the abuse of disable-wp The mmc.txt didn't explicitly say disable-wp is for SD card slot only, but that is what it was designed for in the first place. Remove all disable-wp from emmc or sdio controller. Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 1 - arch/arm/boot/dts/rk3066a-mk808.dts | 1 - arch/arm/boot/dts/rk3066a-rayeager.dts | 2 -- arch/arm/boot/dts/rk3188-bqedison2qc.dts | 1 - arch/arm/boot/dts/rk3188-px3-evb.dts | 1 - arch/arm/boot/dts/rk3229-evb.dts | 1 - arch/arm/boot/dts/rk3288-fennec.dts | 1 - arch/arm/boot/dts/rk3288-firefly-reload.dts | 1 - arch/arm/boot/dts/rk3288-miqi.dts | 1 - arch/arm/boot/dts/rk3288-popmetal.dts | 1 - arch/arm/boot/dts/rk3288-rock2-square.dts | 1 - arch/arm/boot/dts/rk3288-tinker-s.dts | 1 - arch/arm/boot/dts/rk3288-vyasa.dts | 1 - 13 files changed, 14 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 1c925f20dba0..0a56a2f1bc4d 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -171,7 +171,6 @@ pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; bus-width = <4>; - disable-wp; }; &pwm3 { diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts index b6a8a82d219e..9d2216d71f70 100644 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -101,7 +101,6 @@ &mmc1 { bus-width = <4>; - disable-wp; non-removable; pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index cd126b927ba8..949fa800582d 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -147,7 +147,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; @@ -309,7 +308,6 @@ &mmc1 { bus-width = <4>; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index 887d1aa8d0e1..cc66abb22170 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -227,7 +227,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd>; diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts index 9ae65c767c90..c0eaa9c5490b 100644 --- a/arch/arm/boot/dts/rk3188-px3-evb.dts +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts @@ -62,7 +62,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>; diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts index 4df7accc3ad7..350497a3ca86 100644 --- a/arch/arm/boot/dts/rk3229-evb.dts +++ b/arch/arm/boot/dts/rk3229-evb.dts @@ -137,7 +137,6 @@ &emmc { cap-mmc-highspeed; - disable-wp; non-removable; status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts index b1b56dfdfdba..29af26e6d442 100644 --- a/arch/arm/boot/dts/rk3288-fennec.dts +++ b/arch/arm/boot/dts/rk3288-fennec.dts @@ -37,7 +37,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index 58ea8bed040a..3a646c5f4fcf 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -254,7 +254,6 @@ bus-width = <4>; cap-sd-highspeed; cap-sdio-irq; - disable-wp; mmc-pwrseq = <&sdio_pwrseq>; non-removable; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index 504ab1177aa7..fb7365b604bb 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -87,7 +87,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 596435e03132..6a51940398b5 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -109,7 +109,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; mmc-ddr-1_8v; mmc-hs200-1_8v; non-removable; diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index 6a30cadad88a..5b7e1c9e92e1 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -133,7 +133,6 @@ bus-width = <4>; cap-sd-highspeed; cap-sdio-irq; - disable-wp; mmc-pwrseq = <&sdio_pwrseq>; non-removable; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rk3288-tinker-s.dts b/arch/arm/boot/dts/rk3288-tinker-s.dts index 37093922b482..d97da89bcd51 100644 --- a/arch/arm/boot/dts/rk3288-tinker-s.dts +++ b/arch/arm/boot/dts/rk3288-tinker-s.dts @@ -15,7 +15,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts index 4856a9fc0aea..40b232eb5011 100644 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -121,7 +121,6 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; - disable-wp; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; From 52d9bcb3d0de3fa1e07aff3800f857836d30410d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 28 Jan 2019 00:39:30 +0800 Subject: [PATCH 271/506] arm64: dts: allwinner: h6: Move GIC device node fix base address ordering The GIC device node was placed out of order in the initial device tree submission. Move it so the nodes are correctly sorted by base address again. Fixes: e54be32d0273 ("arm64: allwinner: h6: add the basical Allwinner H6 DTSI file") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 22 ++++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index d93a7add67e7..60bf6d915809 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -178,17 +178,6 @@ #reset-cells = <1>; }; - gic: interrupt-controller@3021000 { - compatible = "arm,gic-400"; - reg = <0x03021000 0x1000>, - <0x03022000 0x2000>, - <0x03024000 0x2000>, - <0x03026000 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; @@ -239,6 +228,17 @@ }; }; + gic: interrupt-controller@3021000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + mmc0: mmc@4020000 { compatible = "allwinner,sun50i-h6-mmc", "allwinner,sun50i-a64-mmc"; From 4199ca2a49c6dd47a436a11243676d879c152677 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 27 Jan 2019 22:48:34 +0800 Subject: [PATCH 272/506] ARM: dts: sun5i: Add backlight GPIO for reference design tablet Now that we support the GPIOs on the AXP209, we can control the LCD backlight with them. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index 6202aabedbfe..5b1f0e198eb6 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -54,7 +54,7 @@ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; - /* TODO: backlight uses axp gpio1 as enable pin */ + enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; /* AXP GPIO1 */ }; chosen { From 0a03cd9924dcf09b4c0945776df90546a64c82df Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 27 Jan 2019 22:48:35 +0800 Subject: [PATCH 273/506] ARM: dts: sun5i: q8-tablet: Move panel properties to correct node level The panel backlight and enable GPIO comments were incorrectly placed in the input port, while it should have been in the panel node itself. Move them to the correct position. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts index a89f29fa3e40..3a844dae26f7 100644 --- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts @@ -50,13 +50,13 @@ panel: panel { compatible = "urt,umsh-8596md-t", "simple-panel"; + /* TODO: lcd panel uses axp gpio0 as enable pin */ + backlight = <&backlight>; #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; - /* TODO: lcd panel uses axp gpio0 as enable pin */ - backlight = <&backlight>; #address-cells = <1>; #size-cells = <0>; From 4d58c8cc93bce6ed8180c6ec8da216bfdca397dd Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 27 Jan 2019 22:48:36 +0800 Subject: [PATCH 274/506] ARM: dts: sun5i: q8-tablet: Add LCD Panel enable GPIO Now that we support the AXP209 GPIOs, we can toggle the LCD panel enable line. Add the GPIO phandle to the panel. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts index 3a844dae26f7..ead159f89e74 100644 --- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts @@ -50,7 +50,7 @@ panel: panel { compatible = "urt,umsh-8596md-t", "simple-panel"; - /* TODO: lcd panel uses axp gpio0 as enable pin */ + enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */ backlight = <&backlight>; #address-cells = <1>; #size-cells = <0>; From 64af290124fc067f248d1f667cd04e77578b4877 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 27 Jan 2019 22:48:37 +0800 Subject: [PATCH 275/506] ARM: dts: sun5i: q8-tablet: Add LCD Panel power supply The A13 Q8 tablet, following the A13 reference tablet design, has the system's fixed 3.3V rail feed the VCC supply of the LCD panel. Additional voltage rails used by the panel are generated using a regulator fed from the unregulated IPSOUT output of the PMIC. The latter is unrepresentable in the device tree. Both are controlled with MOSFETs by the enable GPIO added in the previous patch. The actual enable or reset pin for the panel is tied directly to LCD-VCC after the MOSFET. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts index ead159f89e74..c77c0758145a 100644 --- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts @@ -50,6 +50,7 @@ panel: panel { compatible = "urt,umsh-8596md-t", "simple-panel"; + power-supply = <®_vcc3v3>; enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */ backlight = <&backlight>; #address-cells = <1>; From 8f855dbfaf5d0c63f1a6fd7aaeea61ba21e886d2 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 27 Jan 2019 22:48:38 +0800 Subject: [PATCH 276/506] ARM: dts: sun5i: q8-tablet: Use bananapi,s070wv20-ct16 panel compatible The compatible string for the LCD panel used for the Q8 tablets are just a placeholder that was shown to be compatible with the actual panels found on these devices. The real panels do not have any identifiable markings and vary between production runs. The compatibe string previously used had a pixel clock that could not be accurately reproduced on Allwinner hardware, and discussions on whether a margin should be added to the display drivers and how large a margin was acceptable had stalled. Now that we have a panel model that is actually used with Allwinner hardware, has the same dimensions, and the timings have been shown to work with the nameless panels, we can use that one instead. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts index c77c0758145a..7257f39b31ce 100644 --- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts +++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts @@ -49,7 +49,7 @@ compatible = "allwinner,q8-a13", "allwinner,sun5i-a13"; panel: panel { - compatible = "urt,umsh-8596md-t", "simple-panel"; + compatible = "bananapi,s070wv20-ct16", "simple-panel"; power-supply = <®_vcc3v3>; enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */ backlight = <&backlight>; From ff29f13e93a68eb31571db45539371557107683a Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 28 Jan 2019 14:28:45 +0530 Subject: [PATCH 277/506] arm64: dts: allwinner: a64: Add A64 CSI controller Add dts node details for Allwinner A64 CSI controller. A64 CSI has similar features as like in H3, but the CSI_SCLK need to update it to 300MHz than default clock rate. Signed-off-by: Jagan Teki Acked-by: Maxime Ripard Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 8171c0a7f265..b5380dcb596f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -559,6 +559,12 @@ interrupt-controller; #interrupt-cells = <3>; + csi_pins: csi-pins { + pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", + "PE7", "PE8", "PE9", "PE10", "PE11"; + function = "csi"; + }; + i2c0_pins: i2c0_pins { pins = "PH0", "PH1"; function = "i2c0"; @@ -926,6 +932,20 @@ status = "disabled"; }; + csi: csi@1cb0000 { + compatible = "allwinner,sun50i-a64-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + pinctrl-names = "default"; + pinctrl-0 = <&csi_pins>; + status = "disabled"; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"; From 4571a7d814add6bddc91594c0d5862df1504c183 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 28 Jan 2019 21:55:02 +0100 Subject: [PATCH 278/506] dt-bindings: sram: sunxi: Add compatible for the H6 SRAM C1 This introduces a new compatible for the H6 SRAM C1 section, that is compatible with the SRAM C1 section as found on the A10. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/sram/sunxi-sram.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt b/Documentation/devicetree/bindings/sram/sunxi-sram.txt index ab5a70bb9a64..380246a805f2 100644 --- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt +++ b/Documentation/devicetree/bindings/sram/sunxi-sram.txt @@ -63,6 +63,7 @@ The valid sections compatible for H5 are: The valid sections compatible for H6 are: - allwinner,sun50i-h6-sram-c, allwinner,sun50i-a64-sram-c + - allwinner,sun50i-h6-sram-c1, allwinner,sun4i-a10-sram-c1 The valid sections compatible for F1C100s are: - allwinner,suniv-f1c100s-sram-d, allwinner,sun4i-a10-sram-d From 24dd8aed32e041636671ae71fcb242c39e764151 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 28 Jan 2019 21:55:03 +0100 Subject: [PATCH 279/506] arm64: dts: allwinner: h6: Add support for the SRAM C1 section Add a node for H6 SRAM C1 section. Manual calls it VE SRAM, but for consistency with older SoCs, SRAM C1 name is used. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 60bf6d915809..9b6c096e280a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -167,6 +167,20 @@ reg = <0x0000 0x1e000>; }; }; + + sram_c1: sram@1a00000 { + compatible = "mmio-sram"; + reg = <0x01a00000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01a00000 0x200000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun50i-h6-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x200000>; + }; + }; }; ccu: clock@3001000 { From ef972714b1b25683f250e54039623bf3031fe9e6 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 25 Jan 2019 17:49:53 +0000 Subject: [PATCH 280/506] arm64: dts: juno/fast models: using GIC macros instead of hardcoded values There are macros that exist to indicate the GIC specific flags and custom cell values as per the GIC DT bindings. It's used in most of the places in these DTS files but not all. To maintain consistency, lets use the macros at all the places. Since DTC doesn't even warn is any cells are missing, it's very hard to debug if that's the case. Changing to use macros avoids missing cells/ columns. Acked-by: Liviu Dudau Signed-off-by: Sudeep Holla --- .../boot/dts/arm/foundation-v8-gicv2.dtsi | 2 +- .../boot/dts/arm/foundation-v8-gicv3.dtsi | 2 +- arch/arm64/boot/dts/arm/foundation-v8.dtsi | 106 +++++++++--------- arch/arm64/boot/dts/arm/juno-base.dtsi | 38 +++---- arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 106 +++++++++--------- 5 files changed, 129 insertions(+), 125 deletions(-) diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi index 851abf34fc80..15fe81738e94 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi @@ -14,6 +14,6 @@ <0x0 0x2c002000 0 0x2000>, <0x0 0x2c004000 0 0x2000>, <0x0 0x2c006000 0 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = ; }; }; diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi index 91fc5c60d88b..f2c75c756039 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi @@ -17,7 +17,7 @@ <0x0 0x2c000000 0x0 0x2000>, <0x0 0x2c010000 0x0 0x2000>, <0x0 0x2c02f000 0x0 0x2000>; - interrupts = <1 9 4>; + interrupts = ; its: its@2f020000 { compatible = "arm,gic-v3-its"; diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index e080277d27ae..3f78373f708a 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -7,6 +7,8 @@ /dts-v1/; +#include + /memreserve/ 0x80000000 0x00010000; / { @@ -67,26 +69,26 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = , + , + , + ; clock-frequency = <100000000>; }; pmu { compatible = "arm,armv8-pmuv3"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; + interrupts = , + , + , + ; }; watchdog@2a440000 { compatible = "arm,sbsa-gwdt"; reg = <0x0 0x2a440000 0 0x1000>, <0x0 0x2a450000 0 0x1000>; - interrupts = <0 27 4>; + interrupts = ; timeout-sec = <30>; }; @@ -105,49 +107,49 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 0 0 4>, - <0 0 1 &gic 0 0 0 1 4>, - <0 0 2 &gic 0 0 0 2 4>, - <0 0 3 &gic 0 0 0 3 4>, - <0 0 4 &gic 0 0 0 4 4>, - <0 0 5 &gic 0 0 0 5 4>, - <0 0 6 &gic 0 0 0 6 4>, - <0 0 7 &gic 0 0 0 7 4>, - <0 0 8 &gic 0 0 0 8 4>, - <0 0 9 &gic 0 0 0 9 4>, - <0 0 10 &gic 0 0 0 10 4>, - <0 0 11 &gic 0 0 0 11 4>, - <0 0 12 &gic 0 0 0 12 4>, - <0 0 13 &gic 0 0 0 13 4>, - <0 0 14 &gic 0 0 0 14 4>, - <0 0 15 &gic 0 0 0 15 4>, - <0 0 16 &gic 0 0 0 16 4>, - <0 0 17 &gic 0 0 0 17 4>, - <0 0 18 &gic 0 0 0 18 4>, - <0 0 19 &gic 0 0 0 19 4>, - <0 0 20 &gic 0 0 0 20 4>, - <0 0 21 &gic 0 0 0 21 4>, - <0 0 22 &gic 0 0 0 22 4>, - <0 0 23 &gic 0 0 0 23 4>, - <0 0 24 &gic 0 0 0 24 4>, - <0 0 25 &gic 0 0 0 25 4>, - <0 0 26 &gic 0 0 0 26 4>, - <0 0 27 &gic 0 0 0 27 4>, - <0 0 28 &gic 0 0 0 28 4>, - <0 0 29 &gic 0 0 0 29 4>, - <0 0 30 &gic 0 0 0 30 4>, - <0 0 31 &gic 0 0 0 31 4>, - <0 0 32 &gic 0 0 0 32 4>, - <0 0 33 &gic 0 0 0 33 4>, - <0 0 34 &gic 0 0 0 34 4>, - <0 0 35 &gic 0 0 0 35 4>, - <0 0 36 &gic 0 0 0 36 4>, - <0 0 37 &gic 0 0 0 37 4>, - <0 0 38 &gic 0 0 0 38 4>, - <0 0 39 &gic 0 0 0 39 4>, - <0 0 40 &gic 0 0 0 40 4>, - <0 0 41 &gic 0 0 0 41 4>, - <0 0 42 &gic 0 0 0 42 4>; + interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; ethernet@2,02000000 { compatible = "smsc,lan91c111"; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index ed774ee8f659..3a72c04247cb 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -18,7 +18,7 @@ status = "disabled"; frame@2a830000 { frame-number = <1>; - interrupts = <0 60 4>; + interrupts = ; reg = <0x0 0x2a830000 0x0 0x10000>; }; }; @@ -520,10 +520,10 @@ <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>, - <0 0 0 2 &gic 0 0 0 137 4>, - <0 0 0 3 &gic 0 0 0 138 4>, - <0 0 0 4 &gic 0 0 0 139 4>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; msi-parent = <&v2m_0>; status = "disabled"; iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ @@ -787,19 +787,19 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 15>; - interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic 0 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; }; site2: tlx@60000000 { @@ -809,6 +809,6 @@ ranges = <0 0 0x60000000 0x10000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0>; - interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts index fe4fda473c0a..6e685d883303 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts +++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts @@ -10,6 +10,8 @@ /dts-v1/; +#include + /memreserve/ 0x80000000 0x00010000; #include "rtsm_ve-motherboard.dtsi" @@ -101,24 +103,24 @@ <0x0 0x2c002000 0 0x2000>, <0x0 0x2c004000 0 0x2000>, <0x0 0x2c006000 0 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = ; }; timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = , + , + , + ; clock-frequency = <100000000>; }; pmu { compatible = "arm,armv8-pmuv3"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; + interrupts = , + , + , + ; }; panel { @@ -144,48 +146,48 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; + interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; }; }; From 88c2ccc0539136fd5d012462d2893ab12fa6873d Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 25 Jan 2019 17:50:03 +0000 Subject: [PATCH 281/506] arm64: dts: models: use list instead of tuple for mmci interrupts RTSM/FVP vexpress motherboard model MMCI requires dedicated interrupts for CMD and PIO, which obviously should be expressed as a list. Current form uses tuple and it works fine since interrupt-cells equal to 1. Acked-by: Liviu Dudau Reported-by: Vladimir Murzin Reviewed-by: Vladimir Murzin Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index b25f3cbd3da8..102e93744edc 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -86,7 +86,7 @@ mmci@50000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x050000 0x1000>; - interrupts = <9 10>; + interrupts = <9>, <10>; cd-gpios = <&v2m_sysreg 0 0>; wp-gpios = <&v2m_sysreg 1 0>; max-frequency = <12000000>; From 20d00c409475e3ff3a3718f4ce2563adca54fab8 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 25 Jan 2019 17:50:10 +0000 Subject: [PATCH 282/506] arm64: dts: juno/fast models: sort couple of device nodes Sort the couple device nodes with unit addresses which are out of order. Acked-by: Liviu Dudau Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-base.dtsi | 70 +++++++++---------- .../boot/dts/arm/rtsm_ve-motherboard.dtsi | 12 ++-- 2 files changed, 41 insertions(+), 41 deletions(-) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 3a72c04247cb..7446e0dc154d 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -220,6 +220,41 @@ }; }; + replicator@20120000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x20120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + in-ports { + port { + replicator_in_port0: endpoint { + }; + }; + }; + }; + cpu_debug0: cpu-debug@22010000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x22010000 0x0 0x1000>; @@ -452,41 +487,6 @@ }; }; - replicator@20120000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x20120000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; - }; - }; - }; - in-ports { - port { - replicator_in_port0: endpoint { - }; - }; - }; - }; - sram: sram@2e000000 { compatible = "arm,juno-sram-ns", "mmio-sram"; reg = <0x0 0x2e000000 0x0 0x8000>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index 102e93744edc..454cf6c44c49 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -167,6 +167,12 @@ clock-names = "timclken1", "timclken2", "apb_pclk"; }; + virtio-block@130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x200>; + interrupts = <42>; + }; + rtc@170000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x170000 0x1000>; @@ -193,12 +199,6 @@ }; }; }; - - virtio-block@130000 { - compatible = "virtio,mmio"; - reg = <0x130000 0x200>; - interrupts = <42>; - }; }; v2m_fixed_3v3: v2m-3v3 { From fa083b99eb284186ae65193ae856ef2801a1646d Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Fri, 14 Dec 2018 11:35:07 +0000 Subject: [PATCH 283/506] arm64: dts: fast models: Add DTS fo Base RevC FVP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixed Virtual Platforms(FVP) Base RevC model is an emulated Arm platform with GICv3, PCIe, SMMUv3 and various other features. These are available free of charge on the Arm Community website at Arm Development Platforms[1]. It resembles the Foundation Platform, which is a simple FVP that includes an Armv8‑A AEM processor model but this has two cluster of four cores, a CCI-550 interconnect, an SMMU and two PCI devices. In order to enable development of software, let's add a description of the Revison C version of Base platform. The documentation for this FVP model is available @[2] for reference. [1] https://community.arm.com/dev-platforms/ [2] https://static.docs.arm.com/100966/1104/fast_models_fvp_rg_100966_1104_00_en.pdf Cc: Vincent Stehlé Acked-by: Liviu Dudau Signed-off-by: Jean-Philippe Brucker [sudeep.holla: aligned interrupt-map with other DTS, added SPE, changed PMU to use GIC PPI, moved to PSCI v0.2, commit log rewording] Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/fvp-base-revc.dts | 277 ++++++++++++++++++ .../boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 27 ++ 3 files changed, 305 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/fvp-base-revc.dts create mode 100644 arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 5b45144b371a..800da2e84f3f 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += \ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts new file mode 100644 index 000000000000..687707020ec1 --- /dev/null +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Ltd. Fast Models + * + * Architecture Envelope Model (AEM) ARMv8-A + * ARMAEMv8AMPCT + * + * FVP Base RevC + */ + +/dts-v1/; + +#include + +/memreserve/ 0x80000000 0x00010000; + +#include "rtsm_ve-motherboard.dtsi" +#include "rtsm_ve-motherboard-rs2.dtsi" + +/ { + model = "FVP Base RevC"; + compatible = "arm,fvp-base-revc", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "psci"; + }; + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + }; + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + }; + cpu4: cpu@10000 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10000>; + enable-method = "psci"; + }; + cpu5: cpu@10100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10100>; + enable-method = "psci"; + }; + cpu6: cpu@10200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10200>; + enable-method = "psci"; + }; + cpu7: cpu@10300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10300>; + enable-method = "psci"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Chipselect 2,00000000 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0x00000000 0x18000000 0 0x00800000>; + no-map; + }; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, // GICD + <0x0 0x2f100000 0 0x200000>, // GICR + <0x0 0x2c000000 0 0x2000>, // GICC + <0x0 0x2c010000 0 0x2000>, // GICH + <0x0 0x2c02f000 0 0x2000>; // GICV + interrupts = ; + + its: its@2f020000 { + #msi-cells = <1>; + compatible = "arm,gic-v3-its"; + reg = <0x0 0x2f020000 0x0 0x20000>; // GITS + msi-controller; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + spe-pmu { + compatible = "arm,statistical-profiling-extension-v1"; + interrupts = ; + }; + + pci: pci@40000000 { + #address-cells = <0x3>; + #size-cells = <0x2>; + #interrupt-cells = <0x1>; + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0x0 0x1>; + reg = <0x0 0x40000000 0x0 0x10000000>; + ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + msi-map = <0x0 &its 0x0 0x10000>; + iommu-map = <0x0 &smmu 0x0 0x10000>; + + dma-coherent; + }; + + smmu: smmu@2b400000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x2b400000 0x0 0x100000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + dma-coherent; + #iommu-cells = <1>; + msi-parent = <&its 0x10000>; + }; + + panel { + compatible = "arm,rtsm-display", "panel-dpi"; + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <63500127>; + hactive = <1024>; + hback-porch = <152>; + hfront-porch = <48>; + hsync-len = <104>; + vactive = <768>; + vback-porch = <23>; + vfront-porch = <3>; + vsync-len = <4>; + }; + }; + + smb@8000000 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + + motherboard { + iofpga@3,00000000 { + clcd@1f0000 { + max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi new file mode 100644 index 000000000000..57b0b9d7f3fa --- /dev/null +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM Ltd. Fast Models + * + * "rs2" extension for the v2m motherboard + */ +/ { + smb@8000000 { + motherboard { + arm,v2m-memory-map = "rs2"; + + iofpga@3,00000000 { + virtio-p9@140000 { + compatible = "virtio,mmio"; + reg = <0x140000 0x200>; + interrupts = <43>; + }; + + virtio-net@150000 { + compatible = "virtio,mmio"; + reg = <0x150000 0x200>; + interrupts = <44>; + }; + }; + }; + }; +}; From cc0dbf43668db407692deaf2023d4adbeeef9633 Mon Sep 17 00:00:00 2001 From: Dietmar Eggemann Date: Mon, 28 Jan 2019 16:55:22 +0000 Subject: [PATCH 284/506] arm: dts: vexpress-v2p-ca15_a7: Add cpu dynamic-power-coefficient information MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A CPUfreq driver, like the ARM big.LITTLE driver used on the TC2 board, which provide the Energy Model with power cost information via the PM_OPP of_dev_pm_opp_get_cpu_power() function, do need the dynamic-power-coefficient (C) in the device tree. Method used to obtain the C value: C is computed by measuring energy (E) consumption of a frequency domain (FD) over a 10s runtime (t) sysbench workload running at each Operating Performance Point (OPP) affine to 1 or 2 CPUs of that FD while the other CPUs of the system are hotplugged out. By definition all CPUs of a FD have the the same micro-architecture. An OPP is characterized by a certain frequency (f) and voltage (V) value. The corresponding power values (P) are calculated by dividing the delta of the E values between the runs with 2 and 1 CPUs by t. With n data tuples (P, f, V), n equal to number of OPPs for this frequency domain, we can solve C by: P = Pstat + Pdyn P = Pstat + CV²f Cx = (Px - P1)/(Vx²fx - V1²f1) with x = {2, ..., n} The C value is the arithmetic mean out of {C2, ..., Cn}. Signed-off-by: Dietmar Eggemann Signed-off-by: Quentin Perret Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index a2ccacd07f4f..00cd9f5bef2e 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -42,6 +42,7 @@ cci-control-port = <&cci_control1>; cpu-idle-states = <&CLUSTER_SLEEP_BIG>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <990>; }; cpu1: cpu@1 { @@ -51,6 +52,7 @@ cci-control-port = <&cci_control1>; cpu-idle-states = <&CLUSTER_SLEEP_BIG>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <990>; }; cpu2: cpu@2 { @@ -60,6 +62,7 @@ cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; capacity-dmips-mhz = <516>; + dynamic-power-coefficient = <133>; }; cpu3: cpu@3 { @@ -69,6 +72,7 @@ cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; capacity-dmips-mhz = <516>; + dynamic-power-coefficient = <133>; }; cpu4: cpu@4 { @@ -78,6 +82,7 @@ cci-control-port = <&cci_control2>; cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; capacity-dmips-mhz = <516>; + dynamic-power-coefficient = <133>; }; idle-states { From 4daa001a17739947bf966e388e8a287db80d478b Mon Sep 17 00:00:00 2001 From: Dietmar Eggemann Date: Mon, 28 Jan 2019 16:55:21 +0000 Subject: [PATCH 285/506] arm64: dts: juno: Add cpu dynamic-power-coefficient information MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A CPUfreq driver, like the scpi driver used on Juno boards, which provide the Energy Model with power cost information via the PM_OPP of_dev_pm_opp_get_cpu_power() function, do need the dynamic-power-coefficient (C) in the device tree. Method used to obtain the C value: C is computed by measuring energy (E) consumption of a frequency domain (FD) over a 10s runtime (t) sysbench workload running at each Operating Performance Point (OPP) affine to 1 or 2 CPUs of that FD while the other CPUs of the system are hotplugged out. By definition all CPUs of a FD have the the same micro-architecture. An OPP is characterized by a certain frequency (f) and voltage (V) value. The corresponding power values (P) are calculated by dividing the delta of the E values between the runs with 2 and 1 CPUs by t. With n data tuples (P, f, V), n equal to number of OPPs for this frequency domain, we can solve C by: P = Pstat + Pdyn P = Pstat + CV²f Cx = (Px - P1)/(Vx²fx - V1²f1) with x = {2, ..., n} The C value is the arithmetic mean out of {C2, ..., Cn}. Since DVFS is broken on Juno r1, no dynamic-power-coefficient information has been added to its dts file. Signed-off-by: Dietmar Eggemann Signed-off-by: Quentin Perret Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-r2.dts | 6 ++++++ arch/arm64/boot/dts/arm/juno.dts | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index ab77adb4f3c2..66f0ec79c864 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -99,6 +99,7 @@ clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <450>; }; A72_1: cpu@1 { @@ -116,6 +117,7 @@ clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <450>; }; A53_0: cpu@100 { @@ -133,6 +135,7 @@ clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <485>; + dynamic-power-coefficient = <140>; }; A53_1: cpu@101 { @@ -150,6 +153,7 @@ clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <485>; + dynamic-power-coefficient = <140>; }; A53_2: cpu@102 { @@ -167,6 +171,7 @@ clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <485>; + dynamic-power-coefficient = <140>; }; A53_3: cpu@103 { @@ -184,6 +189,7 @@ clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <485>; + dynamic-power-coefficient = <140>; }; A72_L2: l2-cache0 { diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index 08d4ba1716c3..9890afdda77b 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -98,6 +98,7 @@ clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <530>; }; A57_1: cpu@1 { @@ -115,6 +116,7 @@ clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <530>; }; A53_0: cpu@100 { @@ -132,6 +134,7 @@ clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <578>; + dynamic-power-coefficient = <140>; }; A53_1: cpu@101 { @@ -149,6 +152,7 @@ clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <578>; + dynamic-power-coefficient = <140>; }; A53_2: cpu@102 { @@ -166,6 +170,7 @@ clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <578>; + dynamic-power-coefficient = <140>; }; A53_3: cpu@103 { @@ -183,6 +188,7 @@ clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <578>; + dynamic-power-coefficient = <140>; }; A57_L2: l2-cache0 { From 1c909b2dfe6a21de2c24dc1c1405593e40e3a88c Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Tue, 29 Jan 2019 20:46:25 +0100 Subject: [PATCH 286/506] ARM: dts: socfpga: update more missing reset properties Add reset property for dma, can and sdram on socfpga gen5. Signed-off-by: Simon Goldschmidt Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index f365003f0102..ec1966480f2f 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -84,6 +84,7 @@ #dma-requests = <32>; clocks = <&l4_main_clk>; clock-names = "apb_pclk"; + resets = <&rst DMA_RESET>; }; }; @@ -100,6 +101,7 @@ reg = <0xffc00000 0x1000>; interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; clocks = <&can0_clk>; + resets = <&rst CAN0_RESET>; status = "disabled"; }; @@ -108,6 +110,7 @@ reg = <0xffc01000 0x1000>; interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; clocks = <&can1_clk>; + resets = <&rst CAN1_RESET>; status = "disabled"; }; @@ -791,6 +794,7 @@ sdr: sdr@ffc25000 { compatible = "altr,sdr-ctl", "syscon"; reg = <0xffc25000 0x1000>; + resets = <&rst SDR_RESET>; }; sdramedac { From c91d27bba78fa667b020ad08d66d8f16e5dba0ae Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Wed, 23 Jan 2019 15:07:32 -0800 Subject: [PATCH 287/506] ARM: dts: aspeed: tiogapass: Add LPC devices Added lpc control for enabling lpc clock and lpc snoop devices to Facebook Tiogapass device tree. Signed-off-by: Vijay Khemka Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 73e58a821613..8040fa7c007f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -54,6 +54,16 @@ }; }; +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&lpc_ctrl { + // Enable lpc clock + status = "okay"; +}; + &uart1 { // Host Console status = "okay"; From e786eff92838f59a06932c56f0a64c7c050a3418 Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Wed, 23 Jan 2019 15:07:33 -0800 Subject: [PATCH 288/506] ARM: dts: aspeed: tiogapass: Add uarts for SoL Added uart2 and uart3 in Facebook Tiogapass for routing serial input from Host to BMC for SoL via LPC. Signed-off-by: Vijay Khemka Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 8040fa7c007f..4c2dcac738e8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -72,6 +72,16 @@ &pinctrl_rxd1_default>; }; +&uart2 { + // SoL Host Console + status = "okay"; +}; + +&uart3 { + // SoL BMC Console + status = "okay"; +}; + &uart5 { // BMC Console status = "okay"; From 95779307d7e8a730b8327eeca429736f6a8efb05 Mon Sep 17 00:00:00 2001 From: Patrick Venture Date: Tue, 29 Jan 2019 13:46:24 -0800 Subject: [PATCH 289/506] ARM: dts: aspeed: quanta-q71l: enable lpc_ctrl node Enable the lpc_ctrl node in the quanta-q71l dts such that the LPC_CLK is enabled. Signed-off-by: Patrick Venture Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts index 385c0f4b69ee..999679b5ef55 100644 --- a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts @@ -116,6 +116,10 @@ status = "okay"; }; +&lpc_ctrl { + status = "okay"; +}; + &lpc_snoop { status = "okay"; snoop-ports = <0x80>; From e1542521499070f88b18846f676b4cd2a166aee5 Mon Sep 17 00:00:00 2001 From: Patrick Venture Date: Tue, 29 Jan 2019 13:47:02 -0800 Subject: [PATCH 290/506] ARM: dts: aspeed: quanta-q71l: enable uart1 Enable the uart1 node such that the clock will be enabled. Signed-off-by: Patrick Venture Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts index 999679b5ef55..0d7c6339da46 100644 --- a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts @@ -138,6 +138,10 @@ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; }; +&uart1 { + status = "okay"; +}; + &uart5 { status = "okay"; }; From c051dc5e3cea482ceb019028ddde67b7cb921e85 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 28 Jan 2019 09:55:29 +0100 Subject: [PATCH 291/506] dt-bindings: arm: renesas: Fix SoC mismatch for Stout make dtbs_check: arch/arm/boot/dts/r8a7790-stout.dt.yaml: compatible: ['renesas,stout', 'renesas,r8a7790'] is not valid under any of the given schemas The Stout development board has an R-Car H2 (r8a7790) SoC, not an R-Car H1 (r8a7779). Fixes: 12749350567c819d ("dt-bindings: arm: Convert Renesas board/soc bindings to json-schema") Signed-off-by: Geert Uytterhoeven Reviewed-by: Rob Herring Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/renesas.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index cb9b4417e8a1..19f379863d50 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -130,13 +130,13 @@ properties: items: - enum: - renesas,marzen # Marzen (R0P7779A00010S) - - renesas,stout # Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) - const: renesas,r8a7779 - description: R-Car H2 (R8A77900) items: - enum: - renesas,lager # Lager (RTP0RC7790SEB00010S) + - renesas,stout # Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) - const: renesas,r8a7790 - description: R-Car M2-W (R8A77910) From abe60a3a7afb4058278864aa18c5faf62094c11a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 9 Jan 2019 10:26:14 -0600 Subject: [PATCH 292/506] ARM: dts: Kill off skeleton{64}.dtsi Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij Reviewed-by: Florian Fainelli Reviewed-by: Matthias Brugger Acked-by: Viresh Kumar Acked-by: Alexandre Belloni Acked-by: Neil Armstrong Acked-by: Antoine Tenart Acked-by: Alexandre TORGUE Acked-by: Robert Jarzmik Acked-by: Vladimir Zapolskiy Tested-by: Kevin Hilman Reviewed-by: Kevin Hilman Tested-by: Martin Blumenstingl Reviewed-by: Martin Blumenstingl Signed-off-by: Rob Herring Reviewed-by: Gregory CLEMENT Tested-by: Gregory CLEMENT Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/alphascale-asm9260.dtsi | 3 ++- arch/arm/boot/dts/alpine.dtsi | 8 +++++++- arch/arm/boot/dts/arm-realview-eb.dtsi | 4 +++- arch/arm/boot/dts/arm-realview-pb1176.dts | 4 +++- arch/arm/boot/dts/arm-realview-pb11mp.dts | 4 +++- arch/arm/boot/dts/arm-realview-pbx.dtsi | 4 +++- arch/arm/boot/dts/armada-38x.dtsi | 4 +++- arch/arm/boot/dts/armada-39x.dtsi | 3 ++- arch/arm/boot/dts/artpec6.dtsi | 3 ++- arch/arm/boot/dts/at91rm9200.dtsi | 4 +++- arch/arm/boot/dts/at91sam9260.dtsi | 4 +++- arch/arm/boot/dts/at91sam9261.dtsi | 4 +++- arch/arm/boot/dts/at91sam9263.dtsi | 4 +++- arch/arm/boot/dts/at91sam9g45.dtsi | 4 +++- arch/arm/boot/dts/at91sam9n12.dtsi | 4 +++- arch/arm/boot/dts/at91sam9rl.dtsi | 4 +++- arch/arm/boot/dts/at91sam9x5.dtsi | 4 +++- arch/arm/boot/dts/atlas6-evb.dts | 1 + arch/arm/boot/dts/atlas6.dtsi | 1 - arch/arm/boot/dts/atlas7.dtsi | 1 - arch/arm/boot/dts/axm55xx.dtsi | 4 ++-- arch/arm/boot/dts/bcm-cygnus.dtsi | 9 +++++++-- arch/arm/boot/dts/bcm-nsp.dtsi | 4 ++-- arch/arm/boot/dts/bcm11351.dtsi | 4 ++-- arch/arm/boot/dts/bcm21664-garnet.dts | 1 + arch/arm/boot/dts/bcm21664.dtsi | 4 ++-- arch/arm/boot/dts/bcm23550-sparrow.dts | 1 + arch/arm/boot/dts/bcm23550.dtsi | 4 ++-- arch/arm/boot/dts/bcm28155-ap.dts | 1 + arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 1 + .../boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 1 + .../boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 1 + arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 1 + arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 1 + .../boot/dts/bcm47081-tplink-archer-c5-v2.dts | 1 + arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 1 + .../arm/boot/dts/bcm47094-linksys-panamera.dts | 1 + arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 1 + arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 1 + arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 1 + arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 1 + .../boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 1 + arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 1 + arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts | 1 + arch/arm/boot/dts/bcm47189-luxul-xap-810.dts | 1 + arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 1 + arch/arm/boot/dts/bcm5301x.dtsi | 3 ++- .../boot/dts/bcm53340-ubnt-unifi-switch8.dts | 1 + arch/arm/boot/dts/bcm53573.dtsi | 3 ++- arch/arm/boot/dts/bcm63138.dtsi | 4 ++-- arch/arm/boot/dts/bcm7445.dtsi | 2 -- arch/arm/boot/dts/bcm947189acdbmr.dts | 1 + arch/arm/boot/dts/bcm953012er.dts | 1 + arch/arm/boot/dts/bcm953012hr.dts | 1 + arch/arm/boot/dts/bcm953012k.dts | 1 + arch/arm/boot/dts/cx92755.dtsi | 4 ++-- arch/arm/boot/dts/dove.dtsi | 4 ++-- arch/arm/boot/dts/ep7209.dtsi | 4 ++-- arch/arm/boot/dts/ep7211-edb7211.dts | 1 + arch/arm/boot/dts/integrator.dtsi | 10 ++++++++-- arch/arm/boot/dts/kirkwood.dtsi | 3 ++- arch/arm/boot/dts/lpc32xx.dtsi | 4 ++-- arch/arm/boot/dts/ls1021a.dtsi | 8 +++++++- arch/arm/boot/dts/meson.dtsi | 3 ++- arch/arm/boot/dts/meson6-atv1200.dts | 1 + arch/arm/boot/dts/meson8-minix-neo-x8.dts | 1 + arch/arm/boot/dts/meson8b-ec100.dts | 1 + arch/arm/boot/dts/meson8b-mxq.dts | 1 + arch/arm/boot/dts/meson8b-odroidc1.dts | 1 + arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 1 + arch/arm/boot/dts/mmp2-brownstone.dts | 1 + arch/arm/boot/dts/mmp2.dtsi | 4 +++- arch/arm/boot/dts/moxart.dtsi | 3 ++- arch/arm/boot/dts/mt2701-evb.dts | 1 + arch/arm/boot/dts/mt2701.dtsi | 3 ++- arch/arm/boot/dts/mt6580-evbp1.dts | 1 + arch/arm/boot/dts/mt6580.dtsi | 1 - arch/arm/boot/dts/mt6589-aquaris5.dts | 1 + arch/arm/boot/dts/mt6589.dtsi | 3 ++- arch/arm/boot/dts/mt6592-evb.dts | 2 +- arch/arm/boot/dts/mt6592.dtsi | 3 ++- arch/arm/boot/dts/mt8127-moose.dts | 1 + arch/arm/boot/dts/mt8127.dtsi | 3 ++- arch/arm/boot/dts/mt8135-evbp1.dts | 1 + arch/arm/boot/dts/mt8135.dtsi | 3 ++- arch/arm/boot/dts/nspire.dtsi | 4 ++-- arch/arm/boot/dts/orion5x-lacie-d2-network.dts | 1 + .../orion5x-lacie-ethernet-disk-mini-v2.dts | 1 + arch/arm/boot/dts/orion5x-lswsgl.dts | 1 + .../dts/orion5x-maxtor-shared-storage-2.dts | 1 + arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 1 + arch/arm/boot/dts/orion5x-rd88f5182-nas.dts | 1 + arch/arm/boot/dts/orion5x.dtsi | 4 ++-- arch/arm/boot/dts/ox810se.dtsi | 4 +++- arch/arm/boot/dts/ox820.dtsi | 4 +++- arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 1 - arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 1 - arch/arm/boot/dts/prima2-evb.dts | 1 + arch/arm/boot/dts/prima2.dtsi | 1 - arch/arm/boot/dts/pxa168.dtsi | 4 +++- arch/arm/boot/dts/pxa2xx.dtsi | 3 ++- arch/arm/boot/dts/pxa910.dtsi | 4 +++- arch/arm/boot/dts/qcom-apq8064.dtsi | 8 +++++++- arch/arm/boot/dts/qcom-apq8084.dtsi | 9 +++++++-- arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 +++++++- arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++++- arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi | 1 + arch/arm/boot/dts/qcom-mdm9615.dtsi | 4 ++-- arch/arm/boot/dts/qcom-msm8660.dtsi | 9 +++++++-- arch/arm/boot/dts/qcom-msm8960.dtsi | 9 +++++++-- arch/arm/boot/dts/qcom-msm8974.dtsi | 8 +++++++- arch/arm/boot/dts/sama5d2.dtsi | 4 +++- arch/arm/boot/dts/sama5d3.dtsi | 4 +++- arch/arm/boot/dts/sama5d4.dtsi | 4 +++- arch/arm/boot/dts/skeleton.dtsi | 18 ------------------ arch/arm/boot/dts/skeleton64.dtsi | 14 -------------- arch/arm/boot/dts/spear13xx.dtsi | 4 ++-- arch/arm/boot/dts/spear3xx.dtsi | 4 ++-- arch/arm/boot/dts/spear600.dtsi | 4 ++-- arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 2 +- arch/arm/boot/dts/ste-u300.dts | 2 +- arch/arm/boot/dts/stm32429i-eval.dts | 1 + arch/arm/boot/dts/stm32746g-eval.dts | 1 + arch/arm/boot/dts/stm32f429-disco.dts | 1 + arch/arm/boot/dts/stm32f429.dtsi | 4 +++- arch/arm/boot/dts/stm32f469-disco.dts | 1 + arch/arm/boot/dts/stm32f746-disco.dts | 1 + arch/arm/boot/dts/stm32f746.dtsi | 4 +++- arch/arm/boot/dts/stm32f769-disco.dts | 1 + arch/arm/boot/dts/stm32h743.dtsi | 4 +++- arch/arm/boot/dts/stm32h743i-disco.dts | 1 + arch/arm/boot/dts/stm32h743i-eval.dts | 1 + arch/arm/boot/dts/stm32mp157c-ed1.dts | 1 + arch/arm/boot/dts/versatile-ab.dts | 2 +- arch/arm/boot/dts/vt8500.dtsi | 9 +++++++-- arch/arm/boot/dts/wm8505.dtsi | 9 +++++++-- arch/arm/boot/dts/wm8650.dtsi | 9 +++++++-- arch/arm/boot/dts/wm8750.dtsi | 9 +++++++-- arch/arm/boot/dts/wm8850.dtsi | 9 +++++++-- arch/arm/boot/dts/zx296702-ad1.dts | 1 + arch/arm/boot/dts/zx296702.dtsi | 4 +++- 141 files changed, 309 insertions(+), 141 deletions(-) delete mode 100644 arch/arm/boot/dts/skeleton.dtsi delete mode 100644 arch/arm/boot/dts/skeleton64.dtsi diff --git a/arch/arm/boot/dts/alphascale-asm9260.dtsi b/arch/arm/boot/dts/alphascale-asm9260.dtsi index 907fc7bfc418..2ce6038536fd 100644 --- a/arch/arm/boot/dts/alphascale-asm9260.dtsi +++ b/arch/arm/boot/dts/alphascale-asm9260.dtsi @@ -4,10 +4,11 @@ * Licensed under the X11 license or the GPL v2 (or later) */ -#include "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&icoll>; memory { diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi index 731df7a8c4e6..d3036ea823d1 100644 --- a/arch/arm/boot/dts/alpine.dtsi +++ b/arch/arm/boot/dts/alpine.dtsi @@ -25,12 +25,18 @@ */ #include -#include "skeleton64.dtsi" / { + #address-cells = <2>; + #size-cells = <2>; /* SOC compatibility */ compatible = "al,alpine"; + memory { + device_type = "memory"; + reg = <0 0 0 0>; + }; + /* CPU Configuration */ cpus { #address-cells = <1>; diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi index 0e4c7c4c8c09..610506723ea5 100644 --- a/arch/arm/boot/dts/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm-realview-eb.dtsi @@ -22,9 +22,10 @@ #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; compatible = "arm,realview-eb"; chosen { }; @@ -38,6 +39,7 @@ }; memory { + device_type = "memory"; /* 128 MiB memory @ 0x0 */ reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts index 83e0fbc4a1a1..cbbb8878daa3 100644 --- a/arch/arm/boot/dts/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -23,9 +23,10 @@ /dts-v1/; #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; model = "ARM RealView PB1176"; compatible = "arm,realview-pb1176"; @@ -40,6 +41,7 @@ }; memory { + device_type = "memory"; /* 128 MiB memory @ 0x0 */ reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 2f6aa24a0b67..2015619ca22c 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -23,9 +23,10 @@ /dts-v1/; #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; model = "ARM RealView PB11MPcore"; compatible = "arm,realview-pb11mp"; @@ -39,6 +40,7 @@ }; memory { + device_type = "memory"; /* * The PB11MPCore has 512 MiB memory @ 0x70000000 * and the first 256 are also remapped @ 0x00000000 diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi index 916a97734f84..a81e9c282432 100644 --- a/arch/arm/boot/dts/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi @@ -22,9 +22,10 @@ #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; compatible = "arm,realview-pbx"; chosen { }; @@ -39,6 +40,7 @@ }; memory { + device_type = "memory"; /* 128 MiB memory @ 0x0 */ reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 929459c42760..746887f7be5a 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -9,13 +9,15 @@ * Thomas Petazzoni */ -#include "skeleton.dtsi" #include #include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { + #address-cells = <1>; + #size-cells = <1>; + model = "Marvell Armada 38x family SoC"; compatible = "marvell,armada380"; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index f0c949831efb..b1b86934c688 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -7,13 +7,14 @@ * Thomas Petazzoni */ -#include "skeleton.dtsi" #include #include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { + #address-cells = <1>; + #size-cells = <1>; model = "Marvell Armada 39x family SoC"; compatible = "marvell,armada390"; diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi index 3e4115c2cd75..037157e6c5ee 100644 --- a/arch/arm/boot/dts/artpec6.dtsi +++ b/arch/arm/boot/dts/artpec6.dtsi @@ -43,9 +43,10 @@ #include #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; compatible = "axis,artpec6"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 2ad69a7fbc00..5a882a053816 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -10,13 +10,14 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91RM9200 family SoC"; compatible = "atmel,at91rm9200"; interrupt-parent = <&aic>; @@ -49,6 +50,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 7cd9c3bc4dfb..3b58b94b53c9 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -8,13 +8,14 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9260 family SoC"; compatible = "atmel,at91sam9260"; interrupt-parent = <&aic>; @@ -46,6 +47,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 01d700b63b45..a907a1fdd24c 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -6,13 +6,14 @@ * Licensed under GPLv2 only. */ -#include "skeleton.dtsi" #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9261 family SoC"; compatible = "atmel,at91sam9261"; interrupt-parent = <&aic>; @@ -43,6 +44,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index c5766da4e54e..3fb63d81f18e 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -6,13 +6,14 @@ * Licensed under GPLv2 only. */ -#include "skeleton.dtsi" #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9263 family SoC"; compatible = "atmel,at91sam9263"; interrupt-parent = <&aic>; @@ -45,6 +46,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index d16db1fa7e15..f36819607131 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -9,7 +9,6 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include @@ -17,6 +16,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9G45 family SoC"; compatible = "atmel,at91sam9g45"; interrupt-parent = <&aic>; @@ -51,6 +52,7 @@ }; memory { + device_type = "memory"; reg = <0x70000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 37cb81f457b5..f71d65e6e510 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -7,7 +7,6 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include @@ -15,6 +14,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9N12 SoC"; compatible = "atmel,at91sam9n12"; interrupt-parent = <&aic>; @@ -47,6 +48,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 3862ff2f26e0..6b5777f3c20b 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -7,7 +7,6 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include @@ -15,6 +14,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9RL family SoC"; compatible = "atmel,at91sam9rl", "atmel,at91sam9"; interrupt-parent = <&aic>; @@ -48,6 +49,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 07443a387a8f..79c4956d3902 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -9,7 +9,6 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include @@ -17,6 +16,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel AT91SAM9x5 family SoC"; compatible = "atmel,at91sam9x5"; interrupt-parent = <&aic>; @@ -49,6 +50,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/atlas6-evb.dts b/arch/arm/boot/dts/atlas6-evb.dts index ab042ca8dea1..40882419309d 100644 --- a/arch/arm/boot/dts/atlas6-evb.dts +++ b/arch/arm/boot/dts/atlas6-evb.dts @@ -15,6 +15,7 @@ compatible = "sirf,atlas6-cb", "sirf,atlas6"; memory { + device_type = "memory"; reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 29598667420b..5587b98032a3 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -6,7 +6,6 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" / { compatible = "sirf,atlas6"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/atlas7.dtsi b/arch/arm/boot/dts/atlas7.dtsi index 83449b33de6b..f3de9af35b4d 100644 --- a/arch/arm/boot/dts/atlas7.dtsi +++ b/arch/arm/boot/dts/atlas7.dtsi @@ -6,7 +6,6 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" / { compatible = "sirf,atlas7"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi index 47799f59faa5..2a93d3ee3b66 100644 --- a/arch/arm/boot/dts/axm55xx.dtsi +++ b/arch/arm/boot/dts/axm55xx.dtsi @@ -12,9 +12,9 @@ #include #include -#include "skeleton64.dtsi" - / { + #address-cells = <2>; + #size-cells = <2>; interrupt-parent = <&gic>; aliases { diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 253df7170a4e..5f7b46503a51 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -34,9 +34,9 @@ #include #include -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "brcm,cygnus"; model = "Broadcom Cygnus SoC"; interrupt-parent = <&gic>; @@ -45,6 +45,11 @@ ethernet0 = ð0; }; + memory { + device_type = "memory"; + reg = <0 0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 0d2538b46139..6925b30c2253 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -34,9 +34,9 @@ #include #include -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "brcm,nsp"; model = "Broadcom Northstar Plus SoC"; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index db7cded1b7ad..b99c2e579622 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -16,9 +16,9 @@ #include "dt-bindings/clock/bcm281xx.h" -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; model = "BCM11351 SoC"; compatible = "brcm,bcm11351"; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/bcm21664-garnet.dts b/arch/arm/boot/dts/bcm21664-garnet.dts index e87cb26ddf84..8b045cfab64b 100644 --- a/arch/arm/boot/dts/bcm21664-garnet.dts +++ b/arch/arm/boot/dts/bcm21664-garnet.dts @@ -22,6 +22,7 @@ compatible = "brcm,bcm21664-garnet", "brcm,bcm21664"; memory { + device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 266f2611dc22..758daa334148 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -16,9 +16,9 @@ #include "dt-bindings/clock/bcm21664.h" -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; model = "BCM21664 SoC"; compatible = "brcm,bcm21664"; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/bcm23550-sparrow.dts b/arch/arm/boot/dts/bcm23550-sparrow.dts index 4d525ccb48c8..1c66b15f3013 100644 --- a/arch/arm/boot/dts/bcm23550-sparrow.dts +++ b/arch/arm/boot/dts/bcm23550-sparrow.dts @@ -46,6 +46,7 @@ }; memory { + device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; }; diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/bcm23550.dtsi index a7a643f38385..701198f5f498 100644 --- a/arch/arm/boot/dts/bcm23550.dtsi +++ b/arch/arm/boot/dts/bcm23550.dtsi @@ -36,9 +36,9 @@ /* BCM23550 and BCM21664 have almost identical clocks */ #include "dt-bindings/clock/bcm21664.h" -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; model = "BCM23550 SoC"; compatible = "brcm,bcm23550"; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index 9ce91dd60cb6..fbfca83bd28f 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts @@ -22,6 +22,7 @@ compatible = "brcm,bcm28155-ap", "brcm,bcm11351"; memory { + device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts index 76a2bab3bc6f..fe842f2f1ca7 100644 --- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts @@ -20,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index 69e3570e03dd..6fcbb0509ba0 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -20,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts index 0f6f0fe13bfb..b3e8cc90b13f 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts @@ -20,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index f77089744996..fdeaa895512f 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -16,6 +16,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index 4d427863756f..0d510cb15ec3 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts index 189cc3dcd6ef..962e89edba11 100644 --- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts @@ -16,6 +16,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index 03c1ab188576..658a56ff8a5c 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -20,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 36efe410dcd7..5fd47eec4407 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts index 3e5e9972cd97..6604be6ff0a0 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts index 7fd85475893d..567ebbd5a0e9 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts @@ -16,6 +16,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts index 7acbecd42950..ac2d136ed334 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index f4558d9d2769..74371e821b1a 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index bdad7267255a..b44af63ee310 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; }; diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts index 30719380b6c0..eebc0d43e220 100644 --- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts +++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; }; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts index 74c83b0ca54e..1a5ec22a172c 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts index 214df18f3a75..42c1e1f3a4d5 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts index e15e2a1e9d8c..5ad53ea52d0a 100644 --- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts @@ -16,6 +16,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index fd7af943fb0b..ac5266ee8d4c 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -13,9 +13,10 @@ #include #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&gic>; chipcommonA { diff --git a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts index 431cda514230..2e7fda9b998c 100644 --- a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts +++ b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts @@ -20,6 +20,7 @@ }; memory@0 { + device_type = "memory"; reg = <0x00000000 0x08000000>, <0x68000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index 5054fa9eb0d0..b29695bd4855 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -7,9 +7,10 @@ #include #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&gic>; aliases { diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi index f59764008b9c..e6a41e1b27fd 100644 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -6,9 +6,9 @@ #include #include -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "brcm,bcm63138"; model = "Broadcom BCM63138 DSL SoC"; interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi index c859aa6f358c..504a63236a5e 100644 --- a/arch/arm/boot/dts/bcm7445.dtsi +++ b/arch/arm/boot/dts/bcm7445.dtsi @@ -1,8 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include -#include "skeleton.dtsi" - / { #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts index ef263412fea5..4991700ae6b0 100644 --- a/arch/arm/boot/dts/bcm947189acdbmr.dts +++ b/arch/arm/boot/dts/bcm947189acdbmr.dts @@ -18,6 +18,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts index 17f63c7a0437..250a1d6f2d05 100644 --- a/arch/arm/boot/dts/bcm953012er.dts +++ b/arch/arm/boot/dts/bcm953012er.dts @@ -40,6 +40,7 @@ compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708"; memory { + device_type = "memory"; reg = <0x00000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/bcm953012hr.dts index 11b0f5ed99e6..9140be7ec053 100644 --- a/arch/arm/boot/dts/bcm953012hr.dts +++ b/arch/arm/boot/dts/bcm953012hr.dts @@ -46,6 +46,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x10000000>; }; }; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts index e798055d6989..52c4c6c9d3f1 100644 --- a/arch/arm/boot/dts/bcm953012k.dts +++ b/arch/arm/boot/dts/bcm953012k.dts @@ -44,6 +44,7 @@ }; memory { + device_type = "memory"; reg = <0x80000000 0x10000000>; }; }; diff --git a/arch/arm/boot/dts/cx92755.dtsi b/arch/arm/boot/dts/cx92755.dtsi index a5a23c376418..d2e8f36f8c60 100644 --- a/arch/arm/boot/dts/cx92755.dtsi +++ b/arch/arm/boot/dts/cx92755.dtsi @@ -44,9 +44,9 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "cnxt,cx92755"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 250ad0535e8c..2e8a3977219f 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -1,12 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 -/include/ "skeleton.dtsi" - #include #include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { + #address-cells = <1>; + #size-cells = <1>; compatible = "marvell,dove"; model = "Marvell Armada 88AP510 SoC"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/ep7209.dtsi b/arch/arm/boot/dts/ep7209.dtsi index aaf1261d2ee4..0e74222a5eae 100644 --- a/arch/arm/boot/dts/ep7209.dtsi +++ b/arch/arm/boot/dts/ep7209.dtsi @@ -6,11 +6,11 @@ /dts-v1/; -#include "skeleton.dtsi" - #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Cirrus Logic EP7209"; compatible = "cirrus,ep7209"; diff --git a/arch/arm/boot/dts/ep7211-edb7211.dts b/arch/arm/boot/dts/ep7211-edb7211.dts index bc9d5b697452..3475c7777cbc 100644 --- a/arch/arm/boot/dts/ep7211-edb7211.dts +++ b/arch/arm/boot/dts/ep7211-edb7211.dts @@ -12,6 +12,7 @@ compatible = "cirrus,edb7211", "cirrus,ep7211", "cirrus,ep7209"; memory { + device_type = "memory"; reg = <0xc0000000 0x02000000>; }; diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index 4d58638d104b..1612a869a4f7 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi @@ -3,9 +3,15 @@ * SoC core Device Tree for the ARM Integrator platforms */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + core-module@10000000 { compatible = "arm,core-module-integrator", "syscon", "simple-mfd"; reg = <0x10000000 0x200>; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 81c7eda2c442..2161e23bd98e 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 -/include/ "skeleton.dtsi" #include #include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { + #address-cells = <1>; + #size-cells = <1>; compatible = "marvell,kirkwood"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index b7303a4e4236..44b468e4c37a 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -11,12 +11,12 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" - #include #include / { + #address-cells = <1>; + #size-cells = <1>; compatible = "nxp,lpc3220"; interrupt-parent = <&mic>; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index ed0941292172..97c1e37e9997 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -45,11 +45,12 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton64.dtsi" #include #include / { + #address-cells = <2>; + #size-cells = <2>; compatible = "fsl,ls1021a"; interrupt-parent = <&gic>; @@ -88,6 +89,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x0>; + }; + sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index e4645f612712..5c303092520a 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -47,9 +47,10 @@ #include #include -/include/ "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&gic>; L2: l2-cache-controller@c4200000 { diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts index fc48cff71ddf..997e69c5963e 100644 --- a/arch/arm/boot/dts/meson6-atv1200.dts +++ b/arch/arm/boot/dts/meson6-atv1200.dts @@ -61,6 +61,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; }; diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts index 55fb090a40ef..8686abd5de7f 100644 --- a/arch/arm/boot/dts/meson8-minix-neo-x8.dts +++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts @@ -57,6 +57,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 0872f6e3abf5..7b6bfb9e805d 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -23,6 +23,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts index 5c9b76af8d42..08ddd7fb0bf8 100644 --- a/arch/arm/boot/dts/meson8b-mxq.dts +++ b/arch/arm/boot/dts/meson8b-mxq.dts @@ -60,6 +60,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index 58669abda259..4de2b973513d 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -62,6 +62,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts index f5853610b20b..32c7a460f21b 100644 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts @@ -28,6 +28,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts index 350208c5e1ed..3da038ba5733 100644 --- a/arch/arm/boot/dts/mmp2-brownstone.dts +++ b/arch/arm/boot/dts/mmp2-brownstone.dts @@ -19,6 +19,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index ee03e0846740..f02fb97f515c 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -7,10 +7,12 @@ * publishhed by the Free Software Foundation. */ -#include "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { serial0 = &uart1; serial1 = &uart2; diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi index da7b3237bfe9..cbf17656bcc7 100644 --- a/arch/arm/boot/dts/moxart.dtsi +++ b/arch/arm/boot/dts/moxart.dtsi @@ -5,10 +5,11 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; compatible = "moxa,moxart"; model = "MOXART"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts index be0edb3dae6c..88f8fd22302a 100644 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ b/arch/arm/boot/dts/mt2701-evb.dts @@ -13,6 +13,7 @@ compatible = "mediatek,mt2701-evb", "mediatek,mt2701"; memory { + device_type = "memory"; reg = <0 0x80000000 0 0x40000000>; }; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 180377e56ef4..51e1305c6471 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -12,10 +12,11 @@ #include #include #include -#include "skeleton64.dtsi" #include "mt2701-pinfunc.h" / { + #address-cells = <2>; + #size-cells = <2>; compatible = "mediatek,mt2701"; interrupt-parent = <&cirq>; diff --git a/arch/arm/boot/dts/mt6580-evbp1.dts b/arch/arm/boot/dts/mt6580-evbp1.dts index ca137897ed60..755a0774a8ee 100644 --- a/arch/arm/boot/dts/mt6580-evbp1.dts +++ b/arch/arm/boot/dts/mt6580-evbp1.dts @@ -22,6 +22,7 @@ }; memory { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; }; diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi index 2bdc5ed12fca..9e17698c0609 100644 --- a/arch/arm/boot/dts/mt6580.dtsi +++ b/arch/arm/boot/dts/mt6580.dtsi @@ -7,7 +7,6 @@ #include #include -#include "skeleton.dtsi" / { compatible = "mediatek,mt6580"; diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mt6589-aquaris5.dts index 7bbaa1279a26..1e7079a3b449 100644 --- a/arch/arm/boot/dts/mt6589-aquaris5.dts +++ b/arch/arm/boot/dts/mt6589-aquaris5.dts @@ -18,6 +18,7 @@ }; memory { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index 28df8495686a..f3ccb70c0779 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -7,9 +7,10 @@ #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; compatible = "mediatek,mt6589"; interrupt-parent = <&sysirq>; diff --git a/arch/arm/boot/dts/mt6592-evb.dts b/arch/arm/boot/dts/mt6592-evb.dts index 02849f6548e3..5e00c1cca2d1 100644 --- a/arch/arm/boot/dts/mt6592-evb.dts +++ b/arch/arm/boot/dts/mt6592-evb.dts @@ -13,7 +13,7 @@ compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; memory { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; }; - diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mt6592.dtsi index 8696ac891d60..3716f8db951c 100644 --- a/arch/arm/boot/dts/mt6592.dtsi +++ b/arch/arm/boot/dts/mt6592.dtsi @@ -7,9 +7,10 @@ #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; compatible = "mediatek,mt6592"; interrupt-parent = <&sysirq>; diff --git a/arch/arm/boot/dts/mt8127-moose.dts b/arch/arm/boot/dts/mt8127-moose.dts index 308829b2da86..560687af87dc 100644 --- a/arch/arm/boot/dts/mt8127-moose.dts +++ b/arch/arm/boot/dts/mt8127-moose.dts @@ -13,6 +13,7 @@ compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; memory { + device_type = "memory"; reg = <0 0x80000000 0 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi index 3adfc6f7859c..aced173c2a52 100644 --- a/arch/arm/boot/dts/mt8127.dtsi +++ b/arch/arm/boot/dts/mt8127.dtsi @@ -7,9 +7,10 @@ #include #include -#include "skeleton64.dtsi" / { + #address-cells = <2>; + #size-cells = <2>; compatible = "mediatek,mt8127"; interrupt-parent = <&sysirq>; diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts index 0ace7a40a60d..f6147fe62f41 100644 --- a/arch/arm/boot/dts/mt8135-evbp1.dts +++ b/arch/arm/boot/dts/mt8135-evbp1.dts @@ -13,6 +13,7 @@ compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135"; memory { + device_type = "memory"; reg = <0 0x80000000 0 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi index 688069dc1533..0e4e835026db 100644 --- a/arch/arm/boot/dts/mt8135.dtsi +++ b/arch/arm/boot/dts/mt8135.dtsi @@ -9,10 +9,11 @@ #include #include #include -#include "skeleton64.dtsi" #include "mt8135-pinfunc.h" / { + #address-cells = <2>; + #size-cells = <2>; compatible = "mediatek,mt8135"; interrupt-parent = <&sysirq>; diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index 1a5ae4cd107f..5a3c1f9d1832 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -9,9 +9,9 @@ * */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&intc>; cpus { diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts index 8c2449da6f00..422958d13d42 100644 --- a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts +++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts @@ -19,6 +19,7 @@ compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x"; memory { + device_type = "memory"; reg = <0x00000000 0x4000000>; /* 64 MB */ }; diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index b545d0f228a5..0043e0040153 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -25,6 +25,7 @@ compatible = "lacie,ethernet-disk-mini-v2", "marvell,orion5x-88f5182", "marvell,orion5x"; memory { + device_type = "memory"; reg = <0x00000000 0x4000000>; /* 64 MB */ }; diff --git a/arch/arm/boot/dts/orion5x-lswsgl.dts b/arch/arm/boot/dts/orion5x-lswsgl.dts index 0d97ded66257..2fbc17d6dfa4 100644 --- a/arch/arm/boot/dts/orion5x-lswsgl.dts +++ b/arch/arm/boot/dts/orion5x-lswsgl.dts @@ -55,6 +55,7 @@ compatible = "buffalo,lswsgl", "marvell,orion5x-88f5182", "marvell,orion5x"; memory { + device_type = "memory"; reg = <0x00000000 0x8000000>; /* 128 MB */ }; diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts index 0324cb54939d..0ca6208a267d 100644 --- a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts +++ b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts @@ -19,6 +19,7 @@ compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x"; memory { + device_type = "memory"; reg = <0x00000000 0x4000000>; /* 64 MB */ }; diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts index 9f6ae4e1de06..ea081afa469d 100644 --- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts @@ -21,6 +21,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x2000000>; /* 32 MB */ }; diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts index d1817af53e0b..487324f7c54e 100644 --- a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts +++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts @@ -16,6 +16,7 @@ compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x"; memory { + device_type = "memory"; reg = <0x00000000 0x4000000>; /* 64 MB */ }; diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index fbccfbbab223..61e631b3fd8b 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -6,11 +6,11 @@ * warranty of any kind, whether express or implied. */ -#include "skeleton.dtsi" - #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { + #address-cells = <1>; + #size-cells = <1>; model = "Marvell Orion5x SoC"; compatible = "marvell,orion5x"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi index c2b48a1838eb..3a26650de4eb 100644 --- a/arch/arm/boot/dts/ox810se.dtsi +++ b/arch/arm/boot/dts/ox810se.dtsi @@ -6,11 +6,12 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" #include #include / { + #address-cells = <1>; + #size-cells = <1>; compatible = "oxsemi,ox810se"; cpus { @@ -25,6 +26,7 @@ }; memory { + device_type = "memory"; /* Max 256MB @ 0x48000000 */ reg = <0x48000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi index 085bbd33eadc..f3239586f38d 100644 --- a/arch/arm/boot/dts/ox820.dtsi +++ b/arch/arm/boot/dts/ox820.dtsi @@ -6,12 +6,13 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; compatible = "oxsemi,ox820"; cpus { @@ -35,6 +36,7 @@ }; memory { + device_type = "memory"; /* Max 512MB @ 0x60000000 */ reg = <0x60000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi index a1266cf8776c..291a28f34762 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi @@ -10,7 +10,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -/include/ "skeleton.dtsi" / { model = "Picochip picoXcell PC3X2"; compatible = "picochip,pc3x2"; diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi index d78cd207eca1..bf9a39ea76b0 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi @@ -10,7 +10,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -/include/ "skeleton.dtsi" / { model = "Picochip picoXcell PC3X3"; compatible = "picochip,pc3x3"; diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts index 57286b4e7b87..55594b3bbc99 100644 --- a/arch/arm/boot/dts/prima2-evb.dts +++ b/arch/arm/boot/dts/prima2-evb.dts @@ -15,6 +15,7 @@ compatible = "sirf,prima2", "sirf,prima2-cb"; memory { + device_type = "memory"; reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 1ca1a9aa953f..54d4f8850e22 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -6,7 +6,6 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" / { compatible = "sirf,prima2"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index b899e25cbb1b..7137f3550183 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi @@ -7,10 +7,12 @@ * publishhed by the Free Software Foundation. */ -#include "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { serial0 = &uart1; serial1 = &uart2; diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index e83879d97aea..bd6bf6d9300f 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -6,7 +6,6 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include "dt-bindings/clock/pxa-clock.h" #define PMGROUP(pin) #pin @@ -29,6 +28,8 @@ } / { + #address-cells = <1>; + #size-cells = <1>; model = "Marvell PXA2xx family SoC"; compatible = "marvell,pxa2xx"; interrupt-parent = <&pxairq>; diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi index 0868f6729be1..c88553a8ee29 100644 --- a/arch/arm/boot/dts/pxa910.dtsi +++ b/arch/arm/boot/dts/pxa910.dtsi @@ -7,10 +7,12 @@ * publishhed by the Free Software Foundation. */ -#include "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { serial0 = &uart1; serial1 = &uart2; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 48c3cf427610..1374c2e52c20 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -#include "skeleton.dtsi" #include #include #include @@ -10,6 +9,8 @@ #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm APQ8064"; compatible = "qcom,apq8064"; interrupt-parent = <&intc>; @@ -94,6 +95,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + thermal-zones { cpu-thermal0 { polling-delay-passive = <250>; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 899f28533ed7..0a0fb147ebb9 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -1,12 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -#include "skeleton.dtsi" - #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm APQ 8084"; compatible = "qcom,apq8084"; interrupt-parent = <&intc>; @@ -87,6 +87,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + firmware { scm { compatible = "qcom,scm"; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 2d56008d8d6b..707017412be2 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -13,12 +13,13 @@ /dts-v1/; -#include "skeleton.dtsi" #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm Technologies, Inc. IPQ4019"; compatible = "qcom,ipq4019"; interrupt-parent = <&intc>; @@ -133,6 +134,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts = #include #include @@ -11,6 +10,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm IPQ8064"; compatible = "qcom,ipq8064"; interrupt-parent = <&intc>; @@ -45,6 +46,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = ; }; }; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index c852b69229c9..e49f67ad5dbc 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -45,8 +45,6 @@ /dts-v1/; -/include/ "skeleton.dtsi" - #include #include #include @@ -54,6 +52,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm MDM9615"; compatible = "qcom,mdm9615"; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 70698941f64c..1c1a863fa0c2 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -1,14 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -/include/ "skeleton.dtsi" - #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm MSM8660"; compatible = "qcom,msm8660"; interrupt-parent = <&intc>; @@ -39,6 +39,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + cpu-pmu { compatible = "qcom,scorpion-mp-pmu"; interrupts = <1 9 0x304>; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 1733d8f40ab1..f2aeaccdc1ad 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -1,14 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -/include/ "skeleton.dtsi" - #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm MSM8960"; compatible = "qcom,msm8960"; interrupt-parent = <&intc>; @@ -44,6 +44,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 10 0x304>; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index ca266a5f021d..aa5ced5859c7 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -6,9 +6,10 @@ #include #include #include -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; model = "Qualcomm MSM8974"; compatible = "qcom,msm8974"; interrupt-parent = <&intc>; @@ -130,6 +131,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + thermal-zones { cpu-thermal0 { polling-delay-passive = <250>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index dc2280d9127f..d159ee42ef29 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -43,13 +43,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel SAMA5D2 family SoC"; compatible = "atmel,sama5d2"; interrupt-parent = <&aic>; @@ -113,6 +114,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 1408fa4a62e4..02198772eb81 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -8,7 +8,6 @@ * Licensed under GPLv2 or later. */ -#include "skeleton.dtsi" #include #include #include @@ -16,6 +15,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel SAMA5D3 family SoC"; compatible = "atmel,sama5d3", "atmel,sama5"; interrupt-parent = <&aic>; @@ -56,6 +57,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 2604fd07dd53..6c1e41f94549 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -43,7 +43,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include #include #include @@ -51,6 +50,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; model = "Atmel SAMA5D4 family SoC"; compatible = "atmel,sama5d4"; interrupt-parent = <&aic>; @@ -90,6 +91,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/skeleton.dtsi b/arch/arm/boot/dts/skeleton.dtsi deleted file mode 100644 index 34eda68d9ea2..000000000000 --- a/arch/arm/boot/dts/skeleton.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * This file is deprecated, and will be removed once existing users have been - * updated. New dts{,i} files should *not* include skeleton.dtsi, and should - * instead explicitly provide the below nodes only as required. - * - * Skeleton device tree; the bare minimum needed to boot; just include and - * add a compatible value. The bootloader will typically populate the memory - * node. - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - aliases { }; - memory { device_type = "memory"; reg = <0 0>; }; -}; diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi deleted file mode 100644 index 54e637752b9d..000000000000 --- a/arch/arm/boot/dts/skeleton64.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Skeleton device tree in the 64 bits version; the bare minimum - * needed to boot; just include and add a compatible value. The - * bootloader will typically populate the memory node. - */ - -/ { - #address-cells = <2>; - #size-cells = <2>; - chosen { }; - aliases { }; - memory { device_type = "memory"; reg = <0 0 0 0>; }; -}; diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index 086b4b333249..390df643a174 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi @@ -11,9 +11,9 @@ * http://www.gnu.org/copyleft/gpl.html */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&gic>; cpus { diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi index 118135d75899..c47380763cae 100644 --- a/arch/arm/boot/dts/spear3xx.dtsi +++ b/arch/arm/boot/dts/spear3xx.dtsi @@ -11,9 +11,9 @@ * http://www.gnu.org/copyleft/gpl.html */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; interrupt-parent = <&vic>; cpus { diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi index 00166eb9be86..0a634fb07452 100644 --- a/arch/arm/boot/dts/spear600.dtsi +++ b/arch/arm/boot/dts/spear600.dtsi @@ -9,9 +9,9 @@ * http://www.gnu.org/copyleft/gpl.html */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "st,spear600"; cpus { diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index fca76a696d9d..f78b4eabd68c 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -4,13 +4,13 @@ */ #include -#include "skeleton.dtsi" / { #address-cells = <1>; #size-cells = <1>; memory { + device_type = "memory"; reg = <0x00000000 0x04000000>, <0x08000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts index 1bd1aba3322f..f4e7660fead7 100644 --- a/arch/arm/boot/dts/ste-u300.dts +++ b/arch/arm/boot/dts/ste-u300.dts @@ -4,7 +4,6 @@ */ /dts-v1/; -/include/ "skeleton.dtsi" / { model = "ST-Ericsson U300"; @@ -22,6 +21,7 @@ }; memory { + device_type = "memory"; reg = <0x48000000 0x03c00000>; }; diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index ed7d7f46465e..73ea84df7bf4 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -61,6 +61,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x2000000>; }; diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index 8c081eaf20fe..d90b0d1e18c7 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -55,6 +55,7 @@ }; memory { + device_type = "memory"; reg = <0xc0000000 0x2000000>; }; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 5ceb2cf3777f..e19d0fe7dbda 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -60,6 +60,7 @@ }; memory { + device_type = "memory"; reg = <0x90000000 0x800000>; }; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 8d6f028ae285..c29aa9d2f6d3 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -45,12 +45,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" #include #include / { + #address-cells = <1>; + #size-cells = <1>; + clocks { clk_hse: clk-hse { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 7937b43d7788..a3ff04940aec 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -61,6 +61,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x1000000>; }; diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts index e3a7bd338d61..0ba9c5b08ab9 100644 --- a/arch/arm/boot/dts/stm32f746-disco.dts +++ b/arch/arm/boot/dts/stm32f746-disco.dts @@ -56,6 +56,7 @@ }; memory { + device_type = "memory"; reg = <0xC0000000 0x800000>; }; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index f48d06a80d1d..a25b7000a3a1 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -40,12 +40,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" #include #include / { + #address-cells = <1>; + #size-cells = <1>; + clocks { clk_hse: clk-hse { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts index 483d896e2bc1..3c7216844a9b 100644 --- a/arch/arm/boot/dts/stm32f769-disco.dts +++ b/arch/arm/boot/dts/stm32f769-disco.dts @@ -56,6 +56,7 @@ }; memory { + device_type = "memory"; reg = <0xC0000000 0x1000000>; }; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index cbdd69ca9e7a..299af0723790 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -40,13 +40,15 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" #include #include #include / { + #address-cells = <1>; + #size-cells = <1>; + clocks { clk_hse: clk-hse { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts index 45e088c55741..f8040356fe2d 100644 --- a/arch/arm/boot/dts/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/stm32h743i-disco.dts @@ -54,6 +54,7 @@ }; memory { + device_type = "memory"; reg = <0xd0000000 0x2000000>; }; diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts index 3f8e0c4a998d..ef34fa2f79ea 100644 --- a/arch/arm/boot/dts/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/stm32h743i-eval.dts @@ -54,6 +54,7 @@ }; memory { + device_type = "memory"; reg = <0xd0000000 0x2000000>; }; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index c3ecb1e10d94..2890204680ba 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -17,6 +17,7 @@ }; memory@c0000000 { + device_type = "memory"; reg = <0xC0000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts index 6f4f60ba5429..269e6bf99ccb 100644 --- a/arch/arm/boot/dts/versatile-ab.dts +++ b/arch/arm/boot/dts/versatile-ab.dts @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -/include/ "skeleton.dtsi" / { model = "ARM Versatile AB"; @@ -21,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x0 0x08000000>; }; diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi index 1929ad390d88..8b5af039b072 100644 --- a/arch/arm/boot/dts/vt8500.dtsi +++ b/arch/arm/boot/dts/vt8500.dtsi @@ -6,9 +6,9 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "via,vt8500"; cpus { @@ -21,6 +21,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + aliases { serial0 = &uart0; serial1 = &uart1; diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index e9ef539e13d3..cca6747304c4 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -6,9 +6,9 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "wm,wm8505"; cpus { @@ -21,6 +21,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + aliases { serial0 = &uart0; serial1 = &uart1; diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi index e12213d16693..00d01769a68f 100644 --- a/arch/arm/boot/dts/wm8650.dtsi +++ b/arch/arm/boot/dts/wm8650.dtsi @@ -6,9 +6,9 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "wm,wm8650"; cpus { @@ -21,6 +21,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + aliases { serial0 = &uart0; serial1 = &uart1; diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi index 46d076d7302b..54d8f7d9bb33 100644 --- a/arch/arm/boot/dts/wm8750.dtsi +++ b/arch/arm/boot/dts/wm8750.dtsi @@ -6,9 +6,9 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "wm,wm8750"; cpus { @@ -21,6 +21,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + aliases { serial0 = &uart0; serial1 = &uart1; diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi index 8fbccfbe75f3..c572d777077f 100644 --- a/arch/arm/boot/dts/wm8850.dtsi +++ b/arch/arm/boot/dts/wm8850.dtsi @@ -6,9 +6,9 @@ * Licensed under GPLv2 or later */ -/include/ "skeleton.dtsi" - / { + #address-cells = <1>; + #size-cells = <1>; compatible = "wm,wm8850"; cpus { @@ -22,6 +22,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x0 0x0>; + }; + aliases { serial0 = &uart0; serial1 = &uart1; diff --git a/arch/arm/boot/dts/zx296702-ad1.dts b/arch/arm/boot/dts/zx296702-ad1.dts index eedd3fcbc002..bd9400840023 100644 --- a/arch/arm/boot/dts/zx296702-ad1.dts +++ b/arch/arm/boot/dts/zx296702-ad1.dts @@ -14,6 +14,7 @@ }; memory { + device_type = "memory"; reg = <0x50000000 0x20000000>; }; }; diff --git a/arch/arm/boot/dts/zx296702.dtsi b/arch/arm/boot/dts/zx296702.dtsi index 240e7a23d81f..afd98de029be 100644 --- a/arch/arm/boot/dts/zx296702.dtsi +++ b/arch/arm/boot/dts/zx296702.dtsi @@ -1,10 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 -#include "skeleton.dtsi" #include #include / { + #address-cells = <1>; + #size-cells = <1>; + cpus { #address-cells = <1>; #size-cells = <0>; From 31af04cd60d3162a58213363fd740a2b0cf0a08e Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 14 Jan 2019 11:45:33 -0600 Subject: [PATCH 293/506] arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek Cc: Mark Rutland Cc: Will Deacon Acked-by: Antoine Tenart Acked-by: Nishanth Menon Acked-by: Maxime Ripard Acked-by: Manivannan Sadhasivam Acked-by: Chanho Min Acked-by: Krzysztof Kozlowski Acked-by: Masahiro Yamada Acked-by: Gregory CLEMENT Acked-by: Thierry Reding Acked-by: Heiko Stuebner Acked-by: Simon Horman Acked-by: Tero Kristo Acked-by: Wei Xu Acked-by: Liviu Dudau Acked-by: Matthias Brugger Acked-by: Michal Simek Acked-by: Scott Branden Acked-by: Kevin Hilman Acked-by: Chunyan Zhang Acked-by: Robert Richter Acked-by: Jisheng Zhang Acked-by: Dinh Nguyen Signed-off-by: Rob Herring Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/actions/s700.dtsi | 8 +- arch/arm64/boot/dts/actions/s900.dtsi | 8 +- arch/arm64/boot/dts/al/alpine-v2.dtsi | 8 +- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 +- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 8 +- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 +- .../boot/dts/altera/socfpga_stratix10.dtsi | 8 +- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 8 +- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 8 +- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 +- arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 8 +- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 16 +-- arch/arm64/boot/dts/apm/apm-storm.dtsi | 16 +-- arch/arm64/boot/dts/arm/juno-r1.dts | 12 +- arch/arm64/boot/dts/arm/juno-r2.dts | 12 +- arch/arm64/boot/dts/arm/juno.dts | 12 +- .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 4 +- .../boot/dts/broadcom/northstar2/ns2.dtsi | 8 +- .../boot/dts/broadcom/stingray/stingray.dtsi | 16 +-- arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 96 ++++++------- arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 8 +- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 16 +-- arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 +- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 16 +-- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 16 +-- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 16 +-- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 32 ++--- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 32 ++--- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 128 +++++++++--------- arch/arm64/boot/dts/lg/lg1312.dtsi | 8 +- arch/arm64/boot/dts/lg/lg1313.dtsi | 8 +- arch/arm64/boot/dts/marvell/armada-372x.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- .../boot/dts/marvell/armada-ap806-dual.dtsi | 4 +- .../boot/dts/marvell/armada-ap806-quad.dtsi | 8 +- .../marvell/armada-ap810-ap0-octa-core.dtsi | 16 +-- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 4 +- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 12 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 16 +-- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 8 +- arch/arm64/boot/dts/qcom/msm8992.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- arch/arm64/boot/dts/realtek/rtd1295.dtsi | 8 +- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 +- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 16 +-- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 12 +- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 4 +- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 4 +- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 8 +- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 4 +- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 2 +- arch/arm64/boot/dts/rockchip/px30.dtsi | 8 +- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 8 +- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 16 +-- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 +- .../boot/dts/socionext/uniphier-ld11.dtsi | 4 +- .../boot/dts/socionext/uniphier-ld20.dtsi | 8 +- .../boot/dts/socionext/uniphier-pxs3.dtsi | 8 +- arch/arm64/boot/dts/sprd/sc9836.dtsi | 8 +- arch/arm64/boot/dts/sprd/sc9860.dtsi | 16 +-- arch/arm64/boot/dts/synaptics/as370.dtsi | 8 +- arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 8 +- arch/arm64/boot/dts/ti/k3-am654.dtsi | 8 +- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 +- arch/arm64/boot/dts/zte/zx296718.dtsi | 8 +- 67 files changed, 427 insertions(+), 427 deletions(-) diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi index 192c7b39c8c1..273a1b169efc 100644 --- a/arch/arm64/boot/dts/actions/s700.dtsi +++ b/arch/arm64/boot/dts/actions/s700.dtsi @@ -18,28 +18,28 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; }; cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; }; cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; }; diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index 491ddccc9038..9e75782b438f 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -18,28 +18,28 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; }; cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; }; cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; }; diff --git a/arch/arm64/boot/dts/al/alpine-v2.dtsi b/arch/arm64/boot/dts/al/alpine-v2.dtsi index 5b7bef684256..d5e7e2bb4e6c 100644 --- a/arch/arm64/boot/dts/al/alpine-v2.dtsi +++ b/arch/arm64/boot/dts/al/alpine-v2.dtsi @@ -47,28 +47,28 @@ #size-cells = <0>; cpu@0 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; }; cpu@1 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; }; cpu@2 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; }; cpu@3 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 837a03dee875..1583afd034ae 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -84,7 +84,7 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0>; enable-method = "psci"; @@ -92,7 +92,7 @@ }; cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <1>; enable-method = "psci"; @@ -100,7 +100,7 @@ }; cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <2>; enable-method = "psci"; @@ -108,7 +108,7 @@ }; cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <3>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index c22621b4b8e9..96acafd3a852 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -48,28 +48,28 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0>; enable-method = "psci"; }; cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <1>; enable-method = "psci"; }; cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <2>; enable-method = "psci"; }; cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <3>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index d93a7add67e7..48e170a2b141 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -22,28 +22,28 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0>; enable-method = "psci"; }; cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <1>; enable-method = "psci"; }; cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <2>; enable-method = "psci"; }; cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <3>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index b2c9bb664595..af4d00741644 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -42,28 +42,28 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x0>; }; cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; }; cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; }; cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index fffd55787981..1b69efabd49a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -68,7 +68,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; @@ -77,7 +77,7 @@ cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; @@ -86,7 +86,7 @@ cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; @@ -95,7 +95,7 @@ cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 3b82a975c663..10418e4b048a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -20,7 +20,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; @@ -28,7 +28,7 @@ cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; @@ -36,7 +36,7 @@ cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; @@ -44,7 +44,7 @@ cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 44c5c51ff1fa..3b63ead4f4ed 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -56,7 +56,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; @@ -65,7 +65,7 @@ cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; @@ -74,7 +74,7 @@ cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; @@ -83,7 +83,7 @@ cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi index 247888d68a3a..ed3a3d5adf31 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi @@ -44,7 +44,7 @@ cpu4: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&l2>; @@ -53,7 +53,7 @@ cpu5: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x101>; enable-method = "psci"; next-level-cache = <&l2>; @@ -62,7 +62,7 @@ cpu6: cpu@102 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x102>; enable-method = "psci"; next-level-cache = <&l2>; @@ -71,7 +71,7 @@ cpu7: cpu@103 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x103>; enable-method = "psci"; next-level-cache = <&l2>; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index d8ecd1661461..7faea28a37b0 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -21,7 +21,7 @@ cpu@0 { device_type = "cpu"; - compatible = "apm,strega", "arm,armv8"; + compatible = "apm,strega"; reg = <0x0 0x000>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -31,7 +31,7 @@ }; cpu@1 { device_type = "cpu"; - compatible = "apm,strega", "arm,armv8"; + compatible = "apm,strega"; reg = <0x0 0x001>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -41,7 +41,7 @@ }; cpu@100 { device_type = "cpu"; - compatible = "apm,strega", "arm,armv8"; + compatible = "apm,strega"; reg = <0x0 0x100>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -51,7 +51,7 @@ }; cpu@101 { device_type = "cpu"; - compatible = "apm,strega", "arm,armv8"; + compatible = "apm,strega"; reg = <0x0 0x101>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -61,7 +61,7 @@ }; cpu@200 { device_type = "cpu"; - compatible = "apm,strega", "arm,armv8"; + compatible = "apm,strega"; reg = <0x0 0x200>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -71,7 +71,7 @@ }; cpu@201 { device_type = "cpu"; - compatible = "apm,strega", "arm,armv8"; + compatible = "apm,strega"; reg = <0x0 0x201>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -81,7 +81,7 @@ }; cpu@300 { device_type = "cpu"; - compatible = "apm,strega", "arm,armv8"; + compatible = "apm,strega"; reg = <0x0 0x300>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -91,7 +91,7 @@ }; cpu@301 { device_type = "cpu"; - compatible = "apm,strega", "arm,armv8"; + compatible = "apm,strega"; reg = <0x0 0x301>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 00e82b8e9a19..94d637d17262 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -21,7 +21,7 @@ cpu@0 { device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; + compatible = "apm,potenza"; reg = <0x0 0x000>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -29,7 +29,7 @@ }; cpu@1 { device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; + compatible = "apm,potenza"; reg = <0x0 0x001>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -37,7 +37,7 @@ }; cpu@100 { device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; + compatible = "apm,potenza"; reg = <0x0 0x100>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -45,7 +45,7 @@ }; cpu@101 { device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; + compatible = "apm,potenza"; reg = <0x0 0x101>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -53,7 +53,7 @@ }; cpu@200 { device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; + compatible = "apm,potenza"; reg = <0x0 0x200>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -61,7 +61,7 @@ }; cpu@201 { device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; + compatible = "apm,potenza"; reg = <0x0 0x201>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -69,7 +69,7 @@ }; cpu@300 { device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; + compatible = "apm,potenza"; reg = <0x0 0x300>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; @@ -77,7 +77,7 @@ }; cpu@301 { device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; + compatible = "apm,potenza"; reg = <0x0 0x301>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index b2b7ced633cf..5f290090b0cf 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -85,7 +85,7 @@ }; A57_0: cpu@0 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x0 0x0>; device_type = "cpu"; enable-method = "psci"; @@ -102,7 +102,7 @@ }; A57_1: cpu@1 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x0 0x1>; device_type = "cpu"; enable-method = "psci"; @@ -119,7 +119,7 @@ }; A53_0: cpu@100 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x100>; device_type = "cpu"; enable-method = "psci"; @@ -136,7 +136,7 @@ }; A53_1: cpu@101 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x101>; device_type = "cpu"; enable-method = "psci"; @@ -153,7 +153,7 @@ }; A53_2: cpu@102 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x102>; device_type = "cpu"; enable-method = "psci"; @@ -170,7 +170,7 @@ }; A53_3: cpu@103 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x103>; device_type = "cpu"; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index ab77adb4f3c2..4e693bd957b2 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -85,7 +85,7 @@ }; A72_0: cpu@0 { - compatible = "arm,cortex-a72","arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x0>; device_type = "cpu"; enable-method = "psci"; @@ -102,7 +102,7 @@ }; A72_1: cpu@1 { - compatible = "arm,cortex-a72","arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x1>; device_type = "cpu"; enable-method = "psci"; @@ -119,7 +119,7 @@ }; A53_0: cpu@100 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x100>; device_type = "cpu"; enable-method = "psci"; @@ -136,7 +136,7 @@ }; A53_1: cpu@101 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x101>; device_type = "cpu"; enable-method = "psci"; @@ -153,7 +153,7 @@ }; A53_2: cpu@102 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x102>; device_type = "cpu"; enable-method = "psci"; @@ -170,7 +170,7 @@ }; A53_3: cpu@103 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x103>; device_type = "cpu"; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index 08d4ba1716c3..148eb533f7a0 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -84,7 +84,7 @@ }; A57_0: cpu@0 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x0 0x0>; device_type = "cpu"; enable-method = "psci"; @@ -101,7 +101,7 @@ }; A57_1: cpu@1 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x0 0x1>; device_type = "cpu"; enable-method = "psci"; @@ -118,7 +118,7 @@ }; A53_0: cpu@100 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x100>; device_type = "cpu"; enable-method = "psci"; @@ -135,7 +135,7 @@ }; A53_1: cpu@101 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x101>; device_type = "cpu"; enable-method = "psci"; @@ -152,7 +152,7 @@ }; A53_2: cpu@102 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x102>; device_type = "cpu"; enable-method = "psci"; @@ -169,7 +169,7 @@ }; A53_3: cpu@103 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x103>; device_type = "cpu"; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts index 8981c3d2ff18..22383c26bb03 100644 --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts @@ -43,14 +43,14 @@ cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 0>; next-level-cache = <&L2_0>; }; cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 1>; next-level-cache = <&L2_0>; }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index ea854f689fda..15f7b0ed3836 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -47,7 +47,7 @@ A57_0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0 0>; enable-method = "psci"; next-level-cache = <&CLUSTER0_L2>; @@ -55,7 +55,7 @@ A57_1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0 1>; enable-method = "psci"; next-level-cache = <&CLUSTER0_L2>; @@ -63,7 +63,7 @@ A57_2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0 2>; enable-method = "psci"; next-level-cache = <&CLUSTER0_L2>; @@ -71,7 +71,7 @@ A57_3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0 3>; enable-method = "psci"; next-level-cache = <&CLUSTER0_L2>; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index cfeaa855bd05..35c4670c00d1 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -44,7 +44,7 @@ cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&CLUSTER0_L2>; @@ -52,7 +52,7 @@ cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&CLUSTER0_L2>; @@ -60,7 +60,7 @@ cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&CLUSTER1_L2>; @@ -68,7 +68,7 @@ cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x101>; enable-method = "psci"; next-level-cache = <&CLUSTER1_L2>; @@ -76,7 +76,7 @@ cpu@200 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x200>; enable-method = "psci"; next-level-cache = <&CLUSTER2_L2>; @@ -84,7 +84,7 @@ cpu@201 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x201>; enable-method = "psci"; next-level-cache = <&CLUSTER2_L2>; @@ -92,7 +92,7 @@ cpu@300 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x300>; enable-method = "psci"; next-level-cache = <&CLUSTER3_L2>; @@ -100,7 +100,7 @@ cpu@301 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x301>; enable-method = "psci"; next-level-cache = <&CLUSTER3_L2>; diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi index 1a9103b269cb..e0a71795261b 100644 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi @@ -64,289 +64,289 @@ cpu@0 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x000>; enable-method = "psci"; }; cpu@1 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x001>; enable-method = "psci"; }; cpu@2 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x002>; enable-method = "psci"; }; cpu@3 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x003>; enable-method = "psci"; }; cpu@4 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x004>; enable-method = "psci"; }; cpu@5 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x005>; enable-method = "psci"; }; cpu@6 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x006>; enable-method = "psci"; }; cpu@7 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x007>; enable-method = "psci"; }; cpu@8 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x008>; enable-method = "psci"; }; cpu@9 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x009>; enable-method = "psci"; }; cpu@a { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x00a>; enable-method = "psci"; }; cpu@b { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x00b>; enable-method = "psci"; }; cpu@c { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x00c>; enable-method = "psci"; }; cpu@d { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x00d>; enable-method = "psci"; }; cpu@e { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x00e>; enable-method = "psci"; }; cpu@f { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x00f>; enable-method = "psci"; }; cpu@100 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x100>; enable-method = "psci"; }; cpu@101 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x101>; enable-method = "psci"; }; cpu@102 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x102>; enable-method = "psci"; }; cpu@103 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x103>; enable-method = "psci"; }; cpu@104 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x104>; enable-method = "psci"; }; cpu@105 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x105>; enable-method = "psci"; }; cpu@106 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x106>; enable-method = "psci"; }; cpu@107 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x107>; enable-method = "psci"; }; cpu@108 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x108>; enable-method = "psci"; }; cpu@109 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x109>; enable-method = "psci"; }; cpu@10a { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x10a>; enable-method = "psci"; }; cpu@10b { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x10b>; enable-method = "psci"; }; cpu@10c { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x10c>; enable-method = "psci"; }; cpu@10d { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x10d>; enable-method = "psci"; }; cpu@10e { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x10e>; enable-method = "psci"; }; cpu@10f { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x10f>; enable-method = "psci"; }; cpu@200 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x200>; enable-method = "psci"; }; cpu@201 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x201>; enable-method = "psci"; }; cpu@202 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x202>; enable-method = "psci"; }; cpu@203 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x203>; enable-method = "psci"; }; cpu@204 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x204>; enable-method = "psci"; }; cpu@205 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x205>; enable-method = "psci"; }; cpu@206 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x206>; enable-method = "psci"; }; cpu@207 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x207>; enable-method = "psci"; }; cpu@208 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x208>; enable-method = "psci"; }; cpu@209 { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x209>; enable-method = "psci"; }; cpu@20a { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x20a>; enable-method = "psci"; }; cpu@20b { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x20b>; enable-method = "psci"; }; cpu@20c { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x20c>; enable-method = "psci"; }; cpu@20d { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x20d>; enable-method = "psci"; }; cpu@20e { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x20e>; enable-method = "psci"; }; cpu@20f { device_type = "cpu"; - compatible = "cavium,thunder", "arm,armv8"; + compatible = "cavium,thunder"; reg = <0x0 0x20f>; enable-method = "psci"; }; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi index ff5c4c47b22b..0b7c935a4778 100644 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi @@ -27,28 +27,28 @@ cpu@0 { device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + compatible = "cavium,thunder2", "brcm,vulcan"; reg = <0x0 0x0>; enable-method = "psci"; }; cpu@1 { device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + compatible = "cavium,thunder2", "brcm,vulcan"; reg = <0x0 0x1>; enable-method = "psci"; }; cpu@2 { device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + compatible = "cavium,thunder2", "brcm,vulcan"; reg = <0x0 0x2>; enable-method = "psci"; }; cpu@3 { device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + compatible = "cavium,thunder2", "brcm,vulcan"; reg = <0x0 0x3>; enable-method = "psci"; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index e7cd3b67d818..a04e80327b6e 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -29,7 +29,7 @@ cpu0: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x100>; clock-frequency = <1300000000>; @@ -41,7 +41,7 @@ cpu1: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x101>; clock-frequency = <1300000000>; @@ -51,7 +51,7 @@ cpu2: cpu@102 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x102>; clock-frequency = <1300000000>; @@ -61,7 +61,7 @@ cpu3: cpu@103 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x103>; clock-frequency = <1300000000>; @@ -71,7 +71,7 @@ cpu4: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; enable-method = "psci"; reg = <0x0>; clock-frequency = <1900000000>; @@ -83,7 +83,7 @@ cpu5: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; enable-method = "psci"; reg = <0x1>; clock-frequency = <1900000000>; @@ -93,7 +93,7 @@ cpu6: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; enable-method = "psci"; reg = <0x2>; clock-frequency = <1900000000>; @@ -103,7 +103,7 @@ cpu7: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; enable-method = "psci"; reg = <0x3>; clock-frequency = <1900000000>; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 75ad724c487e..967558a93d82 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -34,28 +34,28 @@ cpu_atlas0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x0>; enable-method = "psci"; }; cpu_atlas1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x1>; enable-method = "psci"; }; cpu_atlas2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x2>; enable-method = "psci"; }; cpu_atlas3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x3>; enable-method = "psci"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 20ae40df61d5..2f19e0e5b7cf 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -56,7 +56,7 @@ }; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; @@ -70,7 +70,7 @@ }; cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; @@ -83,7 +83,7 @@ }; cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; @@ -96,7 +96,7 @@ }; cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; @@ -109,7 +109,7 @@ }; cpu4: cpu@100 { - compatible = "arm,cortex-a73", "arm,armv8"; + compatible = "arm,cortex-a73"; device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; @@ -123,7 +123,7 @@ }; cpu5: cpu@101 { - compatible = "arm,cortex-a73", "arm,armv8"; + compatible = "arm,cortex-a73"; device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; @@ -136,7 +136,7 @@ }; cpu6: cpu@102 { - compatible = "arm,cortex-a73", "arm,armv8"; + compatible = "arm,cortex-a73"; device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; @@ -149,7 +149,7 @@ }; cpu7: cpu@103 { - compatible = "arm,cortex-a73", "arm,armv8"; + compatible = "arm,cortex-a73"; device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index a5bd6d80b226..2ed06e4588b8 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -56,56 +56,56 @@ }; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; }; cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; }; cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; }; cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; }; cpu4: cpu@100 { - compatible = "arm,cortex-a73", "arm,armv8"; + compatible = "arm,cortex-a73"; device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; }; cpu5: cpu@101 { - compatible = "arm,cortex-a73", "arm,armv8"; + compatible = "arm,cortex-a73"; device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; }; cpu6: cpu@102 { - compatible = "arm,cortex-a73", "arm,armv8"; + compatible = "arm,cortex-a73"; device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; }; cpu7: cpu@103 { - compatible = "arm,cortex-a73", "arm,armv8"; + compatible = "arm,cortex-a73"; device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index aec9e371c2a7..732a9db45b23 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -81,7 +81,7 @@ }; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; @@ -94,7 +94,7 @@ }; cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; @@ -107,7 +107,7 @@ }; cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; @@ -120,7 +120,7 @@ }; cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; @@ -133,7 +133,7 @@ }; cpu4: cpu@100 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; @@ -146,7 +146,7 @@ }; cpu5: cpu@101 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; @@ -159,7 +159,7 @@ }; cpu6: cpu@102 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; @@ -172,7 +172,7 @@ }; cpu7: cpu@103 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 4b472a302cd8..d321edc09c3f 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -87,7 +87,7 @@ cpu0: cpu@20000 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20000>; enable-method = "psci"; next-level-cache = <&cluster0_l2>; @@ -95,7 +95,7 @@ cpu1: cpu@20001 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20001>; enable-method = "psci"; next-level-cache = <&cluster0_l2>; @@ -103,7 +103,7 @@ cpu2: cpu@20002 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20002>; enable-method = "psci"; next-level-cache = <&cluster0_l2>; @@ -111,7 +111,7 @@ cpu3: cpu@20003 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20003>; enable-method = "psci"; next-level-cache = <&cluster0_l2>; @@ -119,7 +119,7 @@ cpu4: cpu@20100 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20100>; enable-method = "psci"; next-level-cache = <&cluster1_l2>; @@ -127,7 +127,7 @@ cpu5: cpu@20101 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20101>; enable-method = "psci"; next-level-cache = <&cluster1_l2>; @@ -135,7 +135,7 @@ cpu6: cpu@20102 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20102>; enable-method = "psci"; next-level-cache = <&cluster1_l2>; @@ -143,7 +143,7 @@ cpu7: cpu@20103 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20103>; enable-method = "psci"; next-level-cache = <&cluster1_l2>; @@ -151,7 +151,7 @@ cpu8: cpu@20200 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20200>; enable-method = "psci"; next-level-cache = <&cluster2_l2>; @@ -159,7 +159,7 @@ cpu9: cpu@20201 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20201>; enable-method = "psci"; next-level-cache = <&cluster2_l2>; @@ -167,7 +167,7 @@ cpu10: cpu@20202 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20202>; enable-method = "psci"; next-level-cache = <&cluster2_l2>; @@ -175,7 +175,7 @@ cpu11: cpu@20203 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20203>; enable-method = "psci"; next-level-cache = <&cluster2_l2>; @@ -183,7 +183,7 @@ cpu12: cpu@20300 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20300>; enable-method = "psci"; next-level-cache = <&cluster3_l2>; @@ -191,7 +191,7 @@ cpu13: cpu@20301 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20301>; enable-method = "psci"; next-level-cache = <&cluster3_l2>; @@ -199,7 +199,7 @@ cpu14: cpu@20302 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20302>; enable-method = "psci"; next-level-cache = <&cluster3_l2>; @@ -207,7 +207,7 @@ cpu15: cpu@20303 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x20303>; enable-method = "psci"; next-level-cache = <&cluster3_l2>; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index d78a6a755d03..56625587b6de 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -87,7 +87,7 @@ cpu0: cpu@10000 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10000>; enable-method = "psci"; next-level-cache = <&cluster0_l2>; @@ -95,7 +95,7 @@ cpu1: cpu@10001 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10001>; enable-method = "psci"; next-level-cache = <&cluster0_l2>; @@ -103,7 +103,7 @@ cpu2: cpu@10002 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10002>; enable-method = "psci"; next-level-cache = <&cluster0_l2>; @@ -111,7 +111,7 @@ cpu3: cpu@10003 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10003>; enable-method = "psci"; next-level-cache = <&cluster0_l2>; @@ -119,7 +119,7 @@ cpu4: cpu@10100 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10100>; enable-method = "psci"; next-level-cache = <&cluster1_l2>; @@ -127,7 +127,7 @@ cpu5: cpu@10101 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10101>; enable-method = "psci"; next-level-cache = <&cluster1_l2>; @@ -135,7 +135,7 @@ cpu6: cpu@10102 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10102>; enable-method = "psci"; next-level-cache = <&cluster1_l2>; @@ -143,7 +143,7 @@ cpu7: cpu@10103 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10103>; enable-method = "psci"; next-level-cache = <&cluster1_l2>; @@ -151,7 +151,7 @@ cpu8: cpu@10200 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10200>; enable-method = "psci"; next-level-cache = <&cluster2_l2>; @@ -159,7 +159,7 @@ cpu9: cpu@10201 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10201>; enable-method = "psci"; next-level-cache = <&cluster2_l2>; @@ -167,7 +167,7 @@ cpu10: cpu@10202 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10202>; enable-method = "psci"; next-level-cache = <&cluster2_l2>; @@ -175,7 +175,7 @@ cpu11: cpu@10203 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10203>; enable-method = "psci"; next-level-cache = <&cluster2_l2>; @@ -183,7 +183,7 @@ cpu12: cpu@10300 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10300>; enable-method = "psci"; next-level-cache = <&cluster3_l2>; @@ -191,7 +191,7 @@ cpu13: cpu@10301 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10301>; enable-method = "psci"; next-level-cache = <&cluster3_l2>; @@ -199,7 +199,7 @@ cpu14: cpu@10302 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10302>; enable-method = "psci"; next-level-cache = <&cluster3_l2>; @@ -207,7 +207,7 @@ cpu15: cpu@10303 { device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x10303>; enable-method = "psci"; next-level-cache = <&cluster3_l2>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index c33adefc3061..28bd4389441f 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -270,7 +270,7 @@ cpu0: cpu@10000 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10000>; enable-method = "psci"; next-level-cache = <&cluster0_l2>; @@ -279,7 +279,7 @@ cpu1: cpu@10001 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10001>; enable-method = "psci"; next-level-cache = <&cluster0_l2>; @@ -288,7 +288,7 @@ cpu2: cpu@10002 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10002>; enable-method = "psci"; next-level-cache = <&cluster0_l2>; @@ -297,7 +297,7 @@ cpu3: cpu@10003 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10003>; enable-method = "psci"; next-level-cache = <&cluster0_l2>; @@ -306,7 +306,7 @@ cpu4: cpu@10100 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10100>; enable-method = "psci"; next-level-cache = <&cluster1_l2>; @@ -315,7 +315,7 @@ cpu5: cpu@10101 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10101>; enable-method = "psci"; next-level-cache = <&cluster1_l2>; @@ -324,7 +324,7 @@ cpu6: cpu@10102 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10102>; enable-method = "psci"; next-level-cache = <&cluster1_l2>; @@ -333,7 +333,7 @@ cpu7: cpu@10103 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10103>; enable-method = "psci"; next-level-cache = <&cluster1_l2>; @@ -342,7 +342,7 @@ cpu8: cpu@10200 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10200>; enable-method = "psci"; next-level-cache = <&cluster2_l2>; @@ -351,7 +351,7 @@ cpu9: cpu@10201 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10201>; enable-method = "psci"; next-level-cache = <&cluster2_l2>; @@ -360,7 +360,7 @@ cpu10: cpu@10202 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10202>; enable-method = "psci"; next-level-cache = <&cluster2_l2>; @@ -369,7 +369,7 @@ cpu11: cpu@10203 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10203>; enable-method = "psci"; next-level-cache = <&cluster2_l2>; @@ -378,7 +378,7 @@ cpu12: cpu@10300 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10300>; enable-method = "psci"; next-level-cache = <&cluster3_l2>; @@ -387,7 +387,7 @@ cpu13: cpu@10301 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10301>; enable-method = "psci"; next-level-cache = <&cluster3_l2>; @@ -396,7 +396,7 @@ cpu14: cpu@10302 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10302>; enable-method = "psci"; next-level-cache = <&cluster3_l2>; @@ -405,7 +405,7 @@ cpu15: cpu@10303 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x10303>; enable-method = "psci"; next-level-cache = <&cluster3_l2>; @@ -414,7 +414,7 @@ cpu16: cpu@30000 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30000>; enable-method = "psci"; next-level-cache = <&cluster4_l2>; @@ -423,7 +423,7 @@ cpu17: cpu@30001 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30001>; enable-method = "psci"; next-level-cache = <&cluster4_l2>; @@ -432,7 +432,7 @@ cpu18: cpu@30002 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30002>; enable-method = "psci"; next-level-cache = <&cluster4_l2>; @@ -441,7 +441,7 @@ cpu19: cpu@30003 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30003>; enable-method = "psci"; next-level-cache = <&cluster4_l2>; @@ -450,7 +450,7 @@ cpu20: cpu@30100 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30100>; enable-method = "psci"; next-level-cache = <&cluster5_l2>; @@ -459,7 +459,7 @@ cpu21: cpu@30101 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30101>; enable-method = "psci"; next-level-cache = <&cluster5_l2>; @@ -468,7 +468,7 @@ cpu22: cpu@30102 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30102>; enable-method = "psci"; next-level-cache = <&cluster5_l2>; @@ -477,7 +477,7 @@ cpu23: cpu@30103 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30103>; enable-method = "psci"; next-level-cache = <&cluster5_l2>; @@ -486,7 +486,7 @@ cpu24: cpu@30200 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30200>; enable-method = "psci"; next-level-cache = <&cluster6_l2>; @@ -495,7 +495,7 @@ cpu25: cpu@30201 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30201>; enable-method = "psci"; next-level-cache = <&cluster6_l2>; @@ -504,7 +504,7 @@ cpu26: cpu@30202 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30202>; enable-method = "psci"; next-level-cache = <&cluster6_l2>; @@ -513,7 +513,7 @@ cpu27: cpu@30203 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30203>; enable-method = "psci"; next-level-cache = <&cluster6_l2>; @@ -522,7 +522,7 @@ cpu28: cpu@30300 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30300>; enable-method = "psci"; next-level-cache = <&cluster7_l2>; @@ -531,7 +531,7 @@ cpu29: cpu@30301 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30301>; enable-method = "psci"; next-level-cache = <&cluster7_l2>; @@ -540,7 +540,7 @@ cpu30: cpu@30302 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30302>; enable-method = "psci"; next-level-cache = <&cluster7_l2>; @@ -549,7 +549,7 @@ cpu31: cpu@30303 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x30303>; enable-method = "psci"; next-level-cache = <&cluster7_l2>; @@ -558,7 +558,7 @@ cpu32: cpu@50000 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50000>; enable-method = "psci"; next-level-cache = <&cluster8_l2>; @@ -567,7 +567,7 @@ cpu33: cpu@50001 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50001>; enable-method = "psci"; next-level-cache = <&cluster8_l2>; @@ -576,7 +576,7 @@ cpu34: cpu@50002 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50002>; enable-method = "psci"; next-level-cache = <&cluster8_l2>; @@ -585,7 +585,7 @@ cpu35: cpu@50003 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50003>; enable-method = "psci"; next-level-cache = <&cluster8_l2>; @@ -594,7 +594,7 @@ cpu36: cpu@50100 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50100>; enable-method = "psci"; next-level-cache = <&cluster9_l2>; @@ -603,7 +603,7 @@ cpu37: cpu@50101 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50101>; enable-method = "psci"; next-level-cache = <&cluster9_l2>; @@ -612,7 +612,7 @@ cpu38: cpu@50102 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50102>; enable-method = "psci"; next-level-cache = <&cluster9_l2>; @@ -621,7 +621,7 @@ cpu39: cpu@50103 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50103>; enable-method = "psci"; next-level-cache = <&cluster9_l2>; @@ -630,7 +630,7 @@ cpu40: cpu@50200 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50200>; enable-method = "psci"; next-level-cache = <&cluster10_l2>; @@ -639,7 +639,7 @@ cpu41: cpu@50201 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50201>; enable-method = "psci"; next-level-cache = <&cluster10_l2>; @@ -648,7 +648,7 @@ cpu42: cpu@50202 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50202>; enable-method = "psci"; next-level-cache = <&cluster10_l2>; @@ -657,7 +657,7 @@ cpu43: cpu@50203 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50203>; enable-method = "psci"; next-level-cache = <&cluster10_l2>; @@ -666,7 +666,7 @@ cpu44: cpu@50300 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50300>; enable-method = "psci"; next-level-cache = <&cluster11_l2>; @@ -675,7 +675,7 @@ cpu45: cpu@50301 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50301>; enable-method = "psci"; next-level-cache = <&cluster11_l2>; @@ -684,7 +684,7 @@ cpu46: cpu@50302 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50302>; enable-method = "psci"; next-level-cache = <&cluster11_l2>; @@ -693,7 +693,7 @@ cpu47: cpu@50303 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x50303>; enable-method = "psci"; next-level-cache = <&cluster11_l2>; @@ -702,7 +702,7 @@ cpu48: cpu@70000 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70000>; enable-method = "psci"; next-level-cache = <&cluster12_l2>; @@ -711,7 +711,7 @@ cpu49: cpu@70001 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70001>; enable-method = "psci"; next-level-cache = <&cluster12_l2>; @@ -720,7 +720,7 @@ cpu50: cpu@70002 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70002>; enable-method = "psci"; next-level-cache = <&cluster12_l2>; @@ -729,7 +729,7 @@ cpu51: cpu@70003 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70003>; enable-method = "psci"; next-level-cache = <&cluster12_l2>; @@ -738,7 +738,7 @@ cpu52: cpu@70100 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70100>; enable-method = "psci"; next-level-cache = <&cluster13_l2>; @@ -747,7 +747,7 @@ cpu53: cpu@70101 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70101>; enable-method = "psci"; next-level-cache = <&cluster13_l2>; @@ -756,7 +756,7 @@ cpu54: cpu@70102 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70102>; enable-method = "psci"; next-level-cache = <&cluster13_l2>; @@ -765,7 +765,7 @@ cpu55: cpu@70103 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70103>; enable-method = "psci"; next-level-cache = <&cluster13_l2>; @@ -774,7 +774,7 @@ cpu56: cpu@70200 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70200>; enable-method = "psci"; next-level-cache = <&cluster14_l2>; @@ -783,7 +783,7 @@ cpu57: cpu@70201 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70201>; enable-method = "psci"; next-level-cache = <&cluster14_l2>; @@ -792,7 +792,7 @@ cpu58: cpu@70202 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70202>; enable-method = "psci"; next-level-cache = <&cluster14_l2>; @@ -801,7 +801,7 @@ cpu59: cpu@70203 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70203>; enable-method = "psci"; next-level-cache = <&cluster14_l2>; @@ -810,7 +810,7 @@ cpu60: cpu@70300 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70300>; enable-method = "psci"; next-level-cache = <&cluster15_l2>; @@ -819,7 +819,7 @@ cpu61: cpu@70301 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70301>; enable-method = "psci"; next-level-cache = <&cluster15_l2>; @@ -828,7 +828,7 @@ cpu62: cpu@70302 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70302>; enable-method = "psci"; next-level-cache = <&cluster15_l2>; @@ -837,7 +837,7 @@ cpu63: cpu@70303 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x70303>; enable-method = "psci"; next-level-cache = <&cluster15_l2>; diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index 4bde7b6f2b11..c8dc9c20fba3 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -21,27 +21,27 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&L2_0>; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi index 16ced1ff1ad3..82c6645b58b7 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -21,27 +21,27 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&L2_0>; diff --git a/arch/arm64/boot/dts/marvell/armada-372x.dtsi b/arch/arm64/boot/dts/marvell/armada-372x.dtsi index 6800945a88ad..5ce55bdbb995 100644 --- a/arch/arm64/boot/dts/marvell/armada-372x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-372x.dtsi @@ -18,7 +18,7 @@ cpus { cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x1>; clocks = <&nb_periph_clk 16>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index e05594ea15fb..3087da80c72b 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -42,7 +42,7 @@ #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0>; clocks = <&nb_periph_clk 16>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index d3c0636558ff..861fd21922c4 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -17,13 +17,13 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x000>; enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x001>; enable-method = "psci"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi index 01ea662afba8..2baafe12ebd4 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi @@ -17,25 +17,25 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x000>; enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x001>; enable-method = "psci"; }; cpu2: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x100>; enable-method = "psci"; }; cpu3: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x101>; enable-method = "psci"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi index b788cb63caf2..d1a7143ef3d4 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi @@ -15,49 +15,49 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x000>; enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x001>; enable-method = "psci"; }; cpu2: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x100>; enable-method = "psci"; }; cpu3: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x101>; enable-method = "psci"; }; cpu4: cpu@200 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x200>; enable-method = "psci"; }; cpu5: cpu@201 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x201>; enable-method = "psci"; }; cpu6: cpu@300 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x300>; enable-method = "psci"; }; cpu7: cpu@301 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x301>; enable-method = "psci"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 8fc4aa77f012..0806daa12541 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -70,7 +70,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; clocks = <&infracfg CLK_INFRA_MUX1_SEL>, <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; @@ -84,7 +84,7 @@ cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; clocks = <&infracfg CLK_INFRA_MUX1_SEL>, <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index fa5a7c4bc807..631a7f77c386 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -1082,13 +1082,13 @@ cpu@0 { device_type = "cpu"; - compatible = "nvidia,denver", "arm,armv8"; + compatible = "nvidia,denver"; reg = <0>; }; cpu@1 { device_type = "cpu"; - compatible = "nvidia,denver", "arm,armv8"; + compatible = "nvidia,denver"; reg = <1>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 22815db4a3ed..66ea7e7c79f5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -982,37 +982,37 @@ #size-cells = <0>; cpu@0 { - compatible = "nvidia,tegra186-denver", "arm,armv8"; + compatible = "nvidia,tegra186-denver"; device_type = "cpu"; reg = <0x000>; }; cpu@1 { - compatible = "nvidia,tegra186-denver", "arm,armv8"; + compatible = "nvidia,tegra186-denver"; device_type = "cpu"; reg = <0x001>; }; cpu@2 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; device_type = "cpu"; reg = <0x100>; }; cpu@3 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; device_type = "cpu"; reg = <0x101>; }; cpu@4 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; device_type = "cpu"; reg = <0x102>; }; cpu@5 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; device_type = "cpu"; reg = <0x103>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 6dfa1ca0b851..35e290c35550 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -871,56 +871,56 @@ #size-cells = <0>; cpu@0 { - compatible = "nvidia,tegra194-carmel", "arm,armv8"; + compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x10000>; enable-method = "psci"; }; cpu@1 { - compatible = "nvidia,tegra194-carmel", "arm,armv8"; + compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x10001>; enable-method = "psci"; }; cpu@2 { - compatible = "nvidia,tegra194-carmel", "arm,armv8"; + compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x100>; enable-method = "psci"; }; cpu@3 { - compatible = "nvidia,tegra194-carmel", "arm,armv8"; + compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x101>; enable-method = "psci"; }; cpu@4 { - compatible = "nvidia,tegra194-carmel", "arm,armv8"; + compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x200>; enable-method = "psci"; }; cpu@5 { - compatible = "nvidia,tegra194-carmel", "arm,armv8"; + compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x201>; enable-method = "psci"; }; cpu@6 { - compatible = "nvidia,tegra194-carmel", "arm,armv8"; + compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x10300>; enable-method = "psci"; }; cpu@7 { - compatible = "nvidia,tegra194-carmel", "arm,armv8"; + compatible = "nvidia,tegra194-carmel"; device_type = "cpu"; reg = <0x10301>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 18226980f7c3..aea1dbc3f53e 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -441,7 +441,7 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0>; next-level-cache = <&L2_0>; enable-method = "psci"; @@ -449,7 +449,7 @@ CPU1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x1>; next-level-cache = <&L2_0>; @@ -457,7 +457,7 @@ CPU2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x2>; next-level-cache = <&L2_0>; @@ -465,7 +465,7 @@ CPU3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x3>; next-level-cache = <&L2_0>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index c5348c3da5a2..bfa61ca1b1c5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -106,7 +106,7 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0>; next-level-cache = <&L2_0>; enable-method = "psci"; @@ -118,7 +118,7 @@ CPU1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x1>; next-level-cache = <&L2_0>; enable-method = "psci"; @@ -130,7 +130,7 @@ CPU2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x2>; next-level-cache = <&L2_0>; enable-method = "psci"; @@ -142,7 +142,7 @@ CPU3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x3>; next-level-cache = <&L2_0>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index cf5cacdd624d..50cefb822d6d 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -38,7 +38,7 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; next-level-cache = <&L2_0>; L2_0: l2-cache { diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index f33c41d01c86..6a4049aae0c3 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -40,7 +40,7 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0>; next-level-cache = <&L2_0>; L2_0: l2-cache { diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi index 8d9ac05d17dc..41d7858da826 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi @@ -17,28 +17,28 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; next-level-cache = <&l2>; }; cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; next-level-cache = <&l2>; }; cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; next-level-cache = <&l2>; }; cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; next-level-cache = <&l2>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 20745a8528c5..2c11b18b7d78 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -61,7 +61,7 @@ #size-cells = <0>; a57_0: cpu@0 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x0>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; @@ -71,7 +71,7 @@ }; a57_1: cpu@1 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x1>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; @@ -81,7 +81,7 @@ }; a53_0: cpu@100 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x100>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; @@ -91,7 +91,7 @@ }; a53_1: cpu@101 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x101>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; @@ -101,7 +101,7 @@ }; a53_2: cpu@102 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x102>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; @@ -111,7 +111,7 @@ }; a53_3: cpu@103 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x103>; device_type = "cpu"; power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index af9605d5db27..4bb8a877cdf8 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -149,7 +149,7 @@ }; a57_0: cpu@0 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x0>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA57_CPU0>; @@ -162,7 +162,7 @@ }; a57_1: cpu@1 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x1>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA57_CPU1>; @@ -175,7 +175,7 @@ }; a57_2: cpu@2 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x2>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA57_CPU2>; @@ -188,7 +188,7 @@ }; a57_3: cpu@3 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x3>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA57_CPU3>; @@ -201,7 +201,7 @@ }; a53_0: cpu@100 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x100>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA53_CPU0>; @@ -213,7 +213,7 @@ }; a53_1: cpu@101 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x101>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA53_CPU1>; @@ -225,7 +225,7 @@ }; a53_2: cpu@102 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x102>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA53_CPU2>; @@ -237,7 +237,7 @@ }; a53_3: cpu@103 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x103>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA53_CPU3>; diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index afedbf5728ec..f613d3cefab2 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -154,7 +154,7 @@ }; a57_0: cpu@0 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x0>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA57_CPU0>; @@ -167,7 +167,7 @@ }; a57_1: cpu@1 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x1>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA57_CPU1>; @@ -180,7 +180,7 @@ }; a53_0: cpu@100 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x100>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA53_CPU0>; @@ -192,7 +192,7 @@ }; a53_1: cpu@101 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x101>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA53_CPU1>; @@ -204,7 +204,7 @@ }; a53_2: cpu@102 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x102>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA53_CPU2>; @@ -216,7 +216,7 @@ }; a53_3: cpu@103 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x103>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA53_CPU3>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 6dc9b1fef830..979f14d1fcc4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -105,7 +105,7 @@ #size-cells = <0>; a57_0: cpu@0 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x0>; device_type = "cpu"; power-domains = <&sysc R8A77965_PD_CA57_CPU0>; @@ -116,7 +116,7 @@ }; a57_1: cpu@1 { - compatible = "arm,cortex-a57", "arm,armv8"; + compatible = "arm,cortex-a57"; reg = <0x1>; device_type = "cpu"; power-domains = <&sysc R8A77965_PD_CA57_CPU1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 563428d1cdc2..5b6164d4b8e3 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -37,7 +37,7 @@ a53_0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0>; clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; power-domains = <&sysc R8A77970_PD_CA53_CPU0>; @@ -47,7 +47,7 @@ a53_1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <1>; clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; power-domains = <&sysc R8A77970_PD_CA53_CPU1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 5bd9b2547c36..4081622d548a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -38,7 +38,7 @@ a53_0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0>; clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; power-domains = <&sysc R8A77980_PD_CA53_CPU0>; @@ -48,7 +48,7 @@ a53_1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <1>; clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; power-domains = <&sysc R8A77980_PD_CA53_CPU1>; @@ -58,7 +58,7 @@ a53_2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <2>; clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; power-domains = <&sysc R8A77980_PD_CA53_CPU2>; @@ -68,7 +68,7 @@ a53_3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <3>; clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; power-domains = <&sysc R8A77980_PD_CA53_CPU3>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index b2f606e286ce..5ce2dcea5136 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -60,7 +60,7 @@ #size-cells = <0>; a53_0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A77990_PD_CA53_CPU0>; @@ -69,7 +69,7 @@ }; a53_1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <1>; device_type = "cpu"; power-domains = <&sysc R8A77990_PD_CA53_CPU1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 8530d9fc1371..5bf3af246e14 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -27,7 +27,7 @@ #size-cells = <0>; a53_0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0>; device_type = "cpu"; power-domains = <&sysc R8A77995_PD_CA53_CPU0>; diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 9aa8d5ef9e45..eb992d60e6ba 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -40,7 +40,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; clocks = <&cru ARMCLK>; @@ -52,7 +52,7 @@ cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; clocks = <&cru ARMCLK>; @@ -64,7 +64,7 @@ cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x2>; enable-method = "psci"; clocks = <&cru ARMCLK>; @@ -76,7 +76,7 @@ cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; + compatible = "arm,cortex-a35"; reg = <0x0 0x3>; enable-method = "psci"; clocks = <&cru ARMCLK>; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index ecd7f19c3542..0f72bb33ce86 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -37,7 +37,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; clocks = <&cru ARMCLK>; #cooling-cells = <2>; @@ -49,7 +49,7 @@ cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; clocks = <&cru ARMCLK>; #cooling-cells = <2>; @@ -61,7 +61,7 @@ cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; clocks = <&cru ARMCLK>; #cooling-cells = <2>; @@ -73,7 +73,7 @@ cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; clocks = <&cru ARMCLK>; #cooling-cells = <2>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 7014d10b954c..06e7c31d7d07 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -73,7 +73,7 @@ cpu_l0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ @@ -81,7 +81,7 @@ cpu_l1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ @@ -89,7 +89,7 @@ cpu_l2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ @@ -97,7 +97,7 @@ cpu_l3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ @@ -105,7 +105,7 @@ cpu_b0: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x100>; enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ @@ -113,7 +113,7 @@ cpu_b1: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x101>; enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ @@ -121,7 +121,7 @@ cpu_b2: cpu@102 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x102>; enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ @@ -129,7 +129,7 @@ cpu_b3: cpu@103 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x103>; enable-method = "psci"; #cooling-cells = <2>; /* min followed by max */ diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 6cc1c9fa4ea6..db9d948c0b03 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -68,7 +68,7 @@ cpu_l0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; clocks = <&cru ARMCLKL>; @@ -79,7 +79,7 @@ cpu_l1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; clocks = <&cru ARMCLKL>; @@ -90,7 +90,7 @@ cpu_l2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; clocks = <&cru ARMCLKL>; @@ -101,7 +101,7 @@ cpu_l3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; clocks = <&cru ARMCLKL>; @@ -112,7 +112,7 @@ cpu_b0: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x100>; enable-method = "psci"; clocks = <&cru ARMCLKB>; @@ -123,7 +123,7 @@ cpu_b1: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x101>; enable-method = "psci"; clocks = <&cru ARMCLKB>; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 31ba52b14e99..a3cd475b48d2 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -33,7 +33,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 0x000>; clocks = <&sys_clk 33>; enable-method = "psci"; @@ -42,7 +42,7 @@ cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 0x001>; clocks = <&sys_clk 33>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 4a0c46cb11cd..7a68ee1a35d5 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -43,7 +43,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0 0x000>; clocks = <&sys_clk 32>; enable-method = "psci"; @@ -53,7 +53,7 @@ cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0 0x001>; clocks = <&sys_clk 32>; enable-method = "psci"; @@ -63,7 +63,7 @@ cpu2: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 0x100>; clocks = <&sys_clk 33>; enable-method = "psci"; @@ -73,7 +73,7 @@ cpu3: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 0x101>; clocks = <&sys_clk 33>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 4f57c9e9d7a8..152c89a64da5 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -39,7 +39,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 0x000>; clocks = <&sys_clk 33>; enable-method = "psci"; @@ -48,7 +48,7 @@ cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 0x001>; clocks = <&sys_clk 33>; enable-method = "psci"; @@ -57,7 +57,7 @@ cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 0x002>; clocks = <&sys_clk 33>; enable-method = "psci"; @@ -66,7 +66,7 @@ cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 0x003>; clocks = <&sys_clk 33>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/sprd/sc9836.dtsi b/arch/arm64/boot/dts/sprd/sc9836.dtsi index 4bcdbb709c01..286d7173f94f 100644 --- a/arch/arm64/boot/dts/sprd/sc9836.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9836.dtsi @@ -18,28 +18,28 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; }; cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; }; cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; }; diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index 5f57bf055cde..b25d19977170 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -50,7 +50,7 @@ CPU0: cpu@530000 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x530000>; enable-method = "psci"; cpu-idle-states = <&CORE_PD &CLUSTER_PD>; @@ -58,7 +58,7 @@ CPU1: cpu@530001 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x530001>; enable-method = "psci"; cpu-idle-states = <&CORE_PD &CLUSTER_PD>; @@ -66,7 +66,7 @@ CPU2: cpu@530002 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x530002>; enable-method = "psci"; cpu-idle-states = <&CORE_PD &CLUSTER_PD>; @@ -74,7 +74,7 @@ CPU3: cpu@530003 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x530003>; enable-method = "psci"; cpu-idle-states = <&CORE_PD &CLUSTER_PD>; @@ -82,7 +82,7 @@ CPU4: cpu@530100 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x530100>; enable-method = "psci"; cpu-idle-states = <&CORE_PD &CLUSTER_PD>; @@ -90,7 +90,7 @@ CPU5: cpu@530101 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x530101>; enable-method = "psci"; cpu-idle-states = <&CORE_PD &CLUSTER_PD>; @@ -98,7 +98,7 @@ CPU6: cpu@530102 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x530102>; enable-method = "psci"; cpu-idle-states = <&CORE_PD &CLUSTER_PD>; @@ -106,7 +106,7 @@ CPU7: cpu@530103 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x530103>; enable-method = "psci"; cpu-idle-states = <&CORE_PD &CLUSTER_PD>; diff --git a/arch/arm64/boot/dts/synaptics/as370.dtsi b/arch/arm64/boot/dts/synaptics/as370.dtsi index 7331acf3874e..addeb0efc616 100644 --- a/arch/arm64/boot/dts/synaptics/as370.dtsi +++ b/arch/arm64/boot/dts/synaptics/as370.dtsi @@ -23,7 +23,7 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0>; enable-method = "psci"; @@ -32,7 +32,7 @@ }; cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x1>; enable-method = "psci"; @@ -41,7 +41,7 @@ }; cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x2>; enable-method = "psci"; @@ -50,7 +50,7 @@ }; cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x3>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi index 216767e2edf6..15625b99e336 100644 --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi @@ -27,7 +27,7 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0>; enable-method = "psci"; @@ -36,7 +36,7 @@ }; cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x1>; enable-method = "psci"; @@ -45,7 +45,7 @@ }; cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x2>; enable-method = "psci"; @@ -54,7 +54,7 @@ }; cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x3>; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/ti/k3-am654.dtsi b/arch/arm64/boot/dts/ti/k3-am654.dtsi index 2affa6f6617e..b221abf43ac2 100644 --- a/arch/arm64/boot/dts/ti/k3-am654.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am654.dtsi @@ -34,7 +34,7 @@ }; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x000>; device_type = "cpu"; enable-method = "psci"; @@ -48,7 +48,7 @@ }; cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x001>; device_type = "cpu"; enable-method = "psci"; @@ -62,7 +62,7 @@ }; cpu2: cpu@100 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x100>; device_type = "cpu"; enable-method = "psci"; @@ -76,7 +76,7 @@ }; cpu3: cpu@101 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x101>; device_type = "cpu"; enable-method = "psci"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index fa4fd777d90e..9aa67340a4d8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -22,7 +22,7 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; @@ -31,7 +31,7 @@ }; cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; @@ -40,7 +40,7 @@ }; cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; @@ -49,7 +49,7 @@ }; cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi index 6eef64761009..cc54837ff4ba 100644 --- a/arch/arm64/boot/dts/zte/zx296718.dtsi +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi @@ -86,7 +86,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; clocks = <&topcrm A53_GATE>; @@ -95,7 +95,7 @@ cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; clocks = <&topcrm A53_GATE>; @@ -104,7 +104,7 @@ cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; clocks = <&topcrm A53_GATE>; @@ -113,7 +113,7 @@ cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; clocks = <&topcrm A53_GATE>; From 87988511cef05ef152987057d166e4d2d3d35152 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Wed, 23 Jan 2019 12:30:37 -0800 Subject: [PATCH 294/506] arm64: dts: hikey: Add DMA entries for Bluetooth UART Add dma0 references for bluetooth uart to enable dma for bt transfers. Cc: Manivannan Sadhasivam Cc: Ryan Grachek Cc: Wei Xu Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: John Stultz Acked-by: Manivannan Sadhasivam Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index aec9e371c2a7..fa15a0887f83 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -319,6 +319,8 @@ clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; + dmas = <&dma0 8 &dma0 9>; + dma-names = "rx", "tx"; status = "disabled"; }; From 11d1447e954b1101ac955688ed9c7575951e9af9 Mon Sep 17 00:00:00 2001 From: Vincent Guittot Date: Mon, 14 Jan 2019 09:24:34 +0100 Subject: [PATCH 295/506] arm64: dts: hikey960: fix SDcard detection The SDcard detection of hikey960 is active low so cd-inverted is wrong. Instead of adding cd-inverted, we should better set correctly cd-gpios to use GPIO_ACTIVE_LOW. Signed-off-by: Vincent Guittot Reviewed-by: Linus Walleij Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 46435466f1ab..e035cf195b19 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -581,8 +581,7 @@ sd-uhs-sdr50; sd-uhs-sdr104; disable-wp; - cd-inverted; - cd-gpios = <&gpio25 3 0>; + cd-gpios = <&gpio25 3 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func From ae4eba836555a03a053b0951dedf3597c8f4fff0 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 18 Jan 2019 08:54:04 +0800 Subject: [PATCH 296/506] arm64: dts: hi3798cv200: fix malformed SPDX license identifier It fixes malformed SPDX license identifier in Hi3798CV200 and Poplar DTS, accroding to Documentation/process/license-rules.rst. Signed-off-by: Shawn Guo Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts | 4 +--- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts index 32716c96b457..c563d3eb2d98 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * DTS File for HiSilicon Poplar Development Board * * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. - * - * Released under the GPLv2 only. - * SPDX-License-Identifier: GPL-2.0 */ /dts-v1/; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 7c0fddd7c8cf..13821a0ff524 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -1,10 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * DTS File for HiSilicon Hi3798cv200 SoC. * * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. - * - * Released under the GPLv2 only. - * SPDX-License-Identifier: GPL-2.0 */ #include From 1ffeef4eeecbdb394f344546659e8176409fafbf Mon Sep 17 00:00:00 2001 From: Yogesh Narayan Gaur Date: Tue, 15 Jan 2019 12:00:26 +0000 Subject: [PATCH 297/506] arm64: dts: lx2160a: add FlexSPI node property Add fspi node property for LX2160A SoC for FlexSPI driver. Property added for the FlexSPI controller and for the connected slave device for the LX2160ARDB target. This is having two SPI-NOR flash device, mt35xu512aba, connected at CS0 and CS1. Signed-off-by: Yogesh Narayan Gaur Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-lx2160a-rdb.dts | 22 +++++++++++++++++++ .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 13 +++++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 6481e5f20e69..70658946fbbe 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -50,6 +50,28 @@ status = "okay"; }; +&fspi { + status = "okay"; + + mt35xu512aba0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,m25p80"; + m25p,fast-read; + spi-max-frequency = <50000000>; + reg = <0>; + }; + + mt35xu512aba1: flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,m25p80"; + m25p,fast-read; + spi-max-frequency = <50000000>; + reg = <1>; + }; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 3f6521c47f51..fe87204850b5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -543,6 +543,19 @@ status = "disabled"; }; + fspi: spi@20c0000 { + compatible = "nxp,lx2160a-fspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "fspi_en", "fspi"; + status = "disabled"; + }; + esdhc0: esdhc@2140000 { compatible = "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; From a69ab6ad2ee07f98920a45d41cf51a3c2479b6e9 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 22 Jan 2019 09:51:43 +0530 Subject: [PATCH 298/506] dt-bindings: arm: fsl: Fix bindings for LS1012A and LS1021A based boards Fix devicetree bindings for Freescale LS1012A and LS1021A SoC based boards. Fixes: a1a38e1f4d1d ("dt-bindings: arm: Convert FSL board/soc bindings to json-schema") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 8a571c7dc11a..af973dc3ee89 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -176,12 +176,20 @@ properties: - fsl,vf610 - fsl,vf610m4 - - description: LS1021A based Boards + - description: LS1012A based Boards items: - enum: - fsl,ls1012a-rdb - fsl,ls1012a-frdm - fsl,ls1012a-qds + - const: fsl,ls1012a + + - description: LS1021A based Boards + items: + - enum: + - fsl,ls1021a-moxa-uc-8410a + - fsl,ls1021a-qds + - fsl,ls1021a-twr - const: fsl,ls1021a - description: LS1043A based Boards From 8cf0c53c307a03202fca34793c5a291d948e191c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 22 Jan 2019 09:51:45 +0530 Subject: [PATCH 299/506] dt-bindings: vendor-prefixes: Add EBS-SYSTART GmbH Vendor Prefix Add vendor prefix for EBS-SYSTART GmbH. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index a81de3134724..4b04ebbdabd0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -109,6 +109,7 @@ dongwoon Dongwoon Anatech dptechnics DPTechnics dragino Dragino Technology Co., Limited ea Embedded Artists AB +ebs-systart EBS-SYSTART GmbH ebv EBV Elektronik eckelmann Eckelmann AG edt Emerging Display Technologies From ce1bcf148a127e712671584cfe634a87eebc0cdd Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 22 Jan 2019 09:51:46 +0530 Subject: [PATCH 300/506] dt-bindings: arm: fsl: Add devicetree binding for Oxalis Add devicetree binding for LS1012A SoC based Oxalis board. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index af973dc3ee89..7e2cd6ad26bd 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -179,6 +179,7 @@ properties: - description: LS1012A based Boards items: - enum: + - ebs-systart,oxalis - fsl,ls1012a-rdb - fsl,ls1012a-frdm - fsl,ls1012a-qds From 809e0db57c2ce8cae5c60ef9ef6e4218b2968528 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 22 Jan 2019 09:51:47 +0530 Subject: [PATCH 301/506] arm64: dts: freescale: Add devicetree for Oxalis Add devicetree support for Oxalis SoM board from EBS-SYSTART. This board is one of the 96Boards Enterprise Edition platform. Below are some of the key features of this board: * SoC: NXP Layerscape LS1012A * RAM: 1GB DDR3L * PMU: NXP VR5100 * Storage: 64MByte SPI Flash for bootloader and RCW, MicroSD Card, SATA * Connectivity: 2x Ethernet * USB: 2x USB3.0 More information about this board can be found in 96Boards product page: https://www.96boards.org/product/oxalis/ Ethernet and SPI flash are not supported yet! Signed-off-by: Manivannan Sadhasivam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/fsl-ls1012a-oxalis.dts | 96 +++++++++++++++++++ 2 files changed, 97 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 0db6e37a0dab..13604e558dc1 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts new file mode 100644 index 000000000000..7c726267ec8f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Oxalis + * + * Copyright (c) 2019 Manivannan Sadhasivam + * + */ + +/dts-v1/; + +#include "fsl-ls1012a.dtsi" + +/ { + model = "Oxalis"; + compatible = "ebs-systart,oxalis", "fsl,ls1012a"; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + frame-master; + bitclock-master; + system-clock-frequency = <25000000>; + }; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + codec: audio-codec@a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0xa>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_1p8v>; + clocks = <&sys_mclk>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; From 7b25c1c56c62edbe112262c9bfc56290c968dd49 Mon Sep 17 00:00:00 2001 From: Yogesh Narayan Gaur Date: Tue, 15 Jan 2019 10:05:35 +0000 Subject: [PATCH 302/506] arm64: dts: lx2160a: update fspi node Flash mt35xu512aba connected to FlexSPI controller supports 1-1-8/1-8-8 protocol. Added flag spi-rx-bus-width and spi-tx-bus-width with values as 8 and 8 respectively for both flashes connected at CS0 and CS1. Signed-off-by: Yogesh Narayan Gaur Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 70658946fbbe..9df37b159415 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -60,6 +60,8 @@ m25p,fast-read; spi-max-frequency = <50000000>; reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <8>; }; mt35xu512aba1: flash@1 { @@ -69,6 +71,8 @@ m25p,fast-read; spi-max-frequency = <50000000>; reg = <1>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <8>; }; }; From 40a17923367118e32e5e413a952736dd83635b32 Mon Sep 17 00:00:00 2001 From: Hao Dong Date: Sun, 20 Jan 2019 23:33:27 +0100 Subject: [PATCH 303/506] ARM: dts: BCM5301X: Add basic DT for Phicomm K3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This router has BCM4709C0 SoC, 128 MiB NAND flash (MX30LF1G18AC-TI), 512 MiB memory and 3 x LAN and 1 x WAN ports. WiFi chips are BCM4366C0 x 2. The router has a small LCD and 3 capactive keys driven by a PIC microcontroller, which is in turn wired to UART1 of main board. Signed-off-by: Hao Dong [rmilecki: drop chosen { }, fix whitespaces, update commit message] Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm47094-phicomm-k3.dts | 71 +++++++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 arch/arm/boot/dts/bcm47094-phicomm-k3.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..bbc0f4527c39 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -115,6 +115,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm47094-luxul-xwr-3100.dtb \ bcm47094-luxul-xwr-3150-v1.dtb \ bcm47094-netgear-r8500.dtb \ + bcm47094-phicomm-k3.dtb \ bcm94708.dtb \ bcm94709.dtb \ bcm953012er.dtb \ diff --git a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts new file mode 100644 index 000000000000..ec09c0426d16 --- /dev/null +++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2017 Hamster Tian + * Copyright (C) 2019 Hao Dong + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch4.dtsi" + +/ { + compatible = "phicomm,k3", "brcm,bcm47094", "brcm,bcm4708"; + model = "Phicomm K3"; + + memory { + reg = <0x00000000 0x08000000 + 0x88000000 0x18000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart1 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&nandcs { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x0000000 0x0080000>; + read-only; + }; + + partition@80000 { + label = "nvram"; + reg = <0x0080000 0x0100000>; + }; + + partition@180000{ + label = "phicomm"; + reg = <0x0180000 0x0280000>; + read-only; + }; + + partition@400000 { + label = "firmware"; + reg = <0x0400000 0x7C00000>; + compatible = "brcm,trx"; + }; + }; +}; From 95f2aac6223aed0f81b208c10fad19ee32762b4c Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Thu, 24 Jan 2019 13:22:32 +0000 Subject: [PATCH 304/506] dt-bindings: fsl: scu: add fallback compatible string for clock SCU clock can be used in a similar way by IMX8QXP and IMX8QM SoCs. Let's add a "fsl,scu-clk" fallback compatible string to allow other SoCs to reuse the common part. Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Michael Turquette Acked-by: Stephen Boyd Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 27784b6edfed..5ec6dcafa7c9 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -70,7 +70,9 @@ Clock bindings based on SCU Message Protocol This binding uses the common clock binding[1]. Required properties: -- compatible: Should be "fsl,imx8qxp-clock". +- compatible: Should be one of: + "fsl,imx8qxp-clock" + followed by "fsl,scu-clk" - #clock-cells: Should be 1. Contains the Clock ID value. - clocks: List of clock specifiers, must contain an entry for each required entry in clock-names @@ -137,7 +139,7 @@ firmware { &lsio_mu1 1 3>; clk: clk { - compatible = "fsl,imx8qxp-clk"; + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; #clock-cells = <1>; }; From 2a005397117019cbd4e4a09ab5cf896a16b652c5 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Thu, 24 Jan 2019 13:22:36 +0000 Subject: [PATCH 305/506] dt-bindings: fsl: scu: add imx8qm scu clock support Add imx8qm scu clock support Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Michael Turquette Acked-by: Stephen Boyd Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 5ec6dcafa7c9..cef5ee83fbc1 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -71,6 +71,7 @@ This binding uses the common clock binding[1]. Required properties: - compatible: Should be one of: + "fsl,imx8qm-clock" "fsl,imx8qxp-clock" followed by "fsl,scu-clk" - #clock-cells: Should be 1. Contains the Clock ID value. From c412123f2fa31bb032efa5f6f66b951de8714ab8 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 25 Jan 2019 17:20:33 +0100 Subject: [PATCH 306/506] arm64: dts: imx8mq: properly describe IRQ hierarchy The GPCv2 sits between most of the peripherals and the GIC and functions as a wakeup controller for the CPU cores. Signed-off-by: Lucas Stach Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 892063a7c26c..603b2ec80ed6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -11,8 +11,7 @@ #include "imx8mq-pinfunc.h" / { - /* This should really be the GPC, but we need a driver for this first */ - interrupt-parent = <&gic>; + interrupt-parent = <&gpc>; #address-cells = <2>; #size-cells = <2>; @@ -257,6 +256,9 @@ gpc: gpc@303a0000 { compatible = "fsl,imx8mq-gpc"; reg = <0x303a0000 0x10000>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; pgc { #address-cells = <1>; From 5e00e9a240391541e389c33bc5447e0a477d3037 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Thu, 17 Jan 2019 15:14:23 +0530 Subject: [PATCH 307/506] arm64: dts: ti: k3-am654: Add Support for eMMC host controller Add support for the Secure Digital Host Controller Interface (SDHCI) present on TI's AM654 SOCs. It is compatible with eMMC5.1 Host Specifications. Enable only upto HS200 speed mode. Signed-off-by: Faiz Abbas Acked-by: Nishanth Menon Signed-off-by: Tero Kristo --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 272cf8fc8d30..9338315b0ca9 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -191,4 +191,18 @@ #address-cells = <1>; #size-cells = <0>; }; + + sdhci0: sdhci@4f80000 { + compatible = "ti,am654-sdhci-5.1"; + reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; + power-domains = <&k3_pds 47>; + clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; + clock-names = "clk_ahb", "clk_xin"; + interrupts = ; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + ti,otap-del-sel = <0x2>; + ti,trm-icp = <0x8>; + dma-coherent; + }; }; From fd58466a3876ddaed2773556fef616159e5c3844 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Thu, 17 Jan 2019 15:14:24 +0530 Subject: [PATCH 308/506] arm64: dts: ti: k3-am654-base-board: Add eMMC Support On the am654x-evm, sdhci0 node is connected to an eMMC. Add node and pinmux for the same. Signed-off-by: Faiz Abbas Acked-by: Nishanth Menon Signed-off-by: Tero Kristo --- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index e41fc3a5987b..11e9a2a43dfc 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -69,6 +69,23 @@ AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */ >; }; + + main_mmc0_pins_default: main-mmc0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ + AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ + AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ + AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ + AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ + AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ + AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ + AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ + AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ + AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ + AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ + AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ + >; + }; }; &main_pmx1 { @@ -163,3 +180,11 @@ #size-cells= <1>; }; }; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + bus-width = <8>; + non-removable; + ti,driver-strength-ohm = <50>; +}; From 560ff039b521712f8cd73b544e1bfe0412a91d71 Mon Sep 17 00:00:00 2001 From: Cezary Gapinski Date: Fri, 1 Feb 2019 11:45:00 +0100 Subject: [PATCH 309/506] ARM: dts: stm32: add SPI support on STM32F429 SoC This patch adds all SPI instances of the STM32F429 SoC. Signed-off-by: Cezary Gapinski Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429.dtsi | 60 ++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 8d6f028ae285..0b1b77e59c41 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -314,6 +314,26 @@ status = "disabled"; }; + spi2: spi@40003800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40003800 0x400>; + interrupts = <36>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>; + status = "disabled"; + }; + + spi3: spi@40003c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40003c00 0x400>; + interrupts = <51>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>; + status = "disabled"; + }; + usart2: serial@40004400 { compatible = "st,stm32-uart"; reg = <0x40004400 0x400>; @@ -523,6 +543,26 @@ status = "disabled"; }; + spi1: spi@40013000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40013000 0x400>; + interrupts = <35>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>; + status = "disabled"; + }; + + spi4: spi@40013400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40013400 0x400>; + interrupts = <84>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>; + status = "disabled"; + }; + syscfg: system-config@40013800 { compatible = "syscon"; reg = <0x40013800 0x400>; @@ -587,6 +627,26 @@ }; }; + spi5: spi@40015000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40015000 0x400>; + interrupts = <85>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; + status = "disabled"; + }; + + spi6: spi@40015400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40015400 0x400>; + interrupts = <86>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>; + status = "disabled"; + }; + pwrcfg: power-config@40007000 { compatible = "syscon"; reg = <0x40007000 0x400>; From 38576a320578392d8ba7aaf4ca723450dc2430c3 Mon Sep 17 00:00:00 2001 From: David Hernandez Sanchez Date: Fri, 1 Feb 2019 11:48:10 +0100 Subject: [PATCH 310/506] ARM: dts: stm32: Enable thermal sensor support on STM32MP157c-ed1 Enable STM32 Digital Thermal Sensor (dts) driver for STM32MP157c-ed1 board. Signed-off-by: David Hernandez Sanchez Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index c3ecb1e10d94..98ef7a061230 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -49,6 +49,10 @@ }; }; +&dts { + status = "okay"; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; From b9e176e0f9c949ccb30fc28d4fc29c92207354cf Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Fri, 28 Dec 2018 23:09:25 +0100 Subject: [PATCH 311/506] dt-bindings: bcm: Add Raspberry Pi 3 A+ This adds the root properties for the Raspberry Pi 3 A+ . Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt index 0dcc3ea5adff..245328f36580 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt @@ -30,6 +30,10 @@ Raspberry Pi 2 Model B Required root node properties: compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; +Raspberry Pi 3 Model A+ +Required root node properties: +compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837"; + Raspberry Pi 3 Model B Required root node properties: compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; From 0040cf8dc9257049f9d4c11f1d38c82886cd391f Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Fri, 28 Dec 2018 23:09:26 +0100 Subject: [PATCH 312/506] ARM: dts: add Raspberry Pi 3 A+ The Raspberry Pi 3 A+ is similar to the Pi 3 B+ but has only 512 MB RAM, 1 USB 2.0 port and no Ethernet. Compared to the Raspberry Pi 3 B it isn't possible to control BT_ON and WL_ON separately. Signed-off-by: Stefan Wahren Acked-by: Eric Anholt --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts | 175 +++++++++++++++++++++ 2 files changed, 176 insertions(+) create mode 100644 arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..d98d51d358f7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2835-rpi-a-plus.dtb \ bcm2835-rpi-cm1-io1.dtb \ bcm2836-rpi-2-b.dtb \ + bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ bcm2837-rpi-cm3-io3.dtb \ diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts new file mode 100644 index 000000000000..e9fadd338227 --- /dev/null +++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837"; + model = "Raspberry Pi 3 Model A+"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + memory { + reg = <0 0x20000000>; + }; + + leds { + act { + gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; + }; + + pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&firmware { + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "", + "BT_WL_ON", + "STATUS_LED_R", + "", + "", + "CAM_GPIO0", + "CAM_GPIO1", + ""; + status = "okay"; + }; +}; + +&gpio { + /* + * This is mostly based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_G", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "", /* GPIO42 */ + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; +}; + +&hdmi { + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; + status = "okay"; +}; + +/* + * SDHCI is used to control the SDIO for wireless + * + * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven + * by a single GPIO. We can't give GPIO control to one of the drivers, + * otherwise the other part would get unexpectedly disturbed. + */ +&sdhci { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_gpio34>; + status = "okay"; + bus-width = <4>; + non-removable; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SDHOST is used to drive the SD card */ +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + status = "okay"; + bus-width = <4>; +}; + +/* uart0 communicates with the BT module */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + }; +}; + +/* uart1 is mapped to the pin header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; From f090e1bd7b05f17d35b6e2d0e946d8a8085d264f Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 30 Dec 2018 11:51:22 +0100 Subject: [PATCH 313/506] ARM: dts: bcm283x: Fix DTC warning for memory node Compiling the bcm283x DTS with W=1 leads to the following warning: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name Fix this by adding the unit address. Signed-off-by: Stefan Wahren Tested-by: Peter Robinson Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi.dtsi | 2 +- arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 2 +- arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts | 2 +- arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 2 +- arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 2 +- arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index 29f970f864dc..a8b175a9e229 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -1,7 +1,7 @@ #include / { - memory { + memory@0 { device_type = "memory"; reg = <0 0x10000000>; }; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index ac4408b34b58..871fc4a558cf 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -9,7 +9,7 @@ compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; model = "Raspberry Pi 2 Model B"; - memory { + memory@0 { reg = <0 0x40000000>; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts index e9fadd338227..7f4437a8eedb 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts @@ -13,7 +13,7 @@ stdout-path = "serial1:115200n8"; }; - memory { + memory@0 { reg = <0 0x20000000>; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index 42bb09044cc7..7d65013f5a4b 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -14,7 +14,7 @@ stdout-path = "serial1:115200n8"; }; - memory { + memory@0 { reg = <0 0x40000000>; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index 0c155dd4f396..9abb9c55e6e4 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -14,7 +14,7 @@ stdout-path = "serial1:115200n8"; }; - memory { + memory@0 { reg = <0 0x40000000>; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi index 4a89a1885a3d..81399b2c5af9 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi @@ -4,7 +4,7 @@ #include "bcm2836-rpi.dtsi" / { - memory { + memory@0 { reg = <0 0x40000000>; }; From 592f50f0f97ae790650219d682f9c88e4f999267 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 30 Dec 2018 12:07:16 +0100 Subject: [PATCH 314/506] ARM: dts: bcm2835-rpi: Drop unnecessary #address-cells/#size-cells Compiling the bcm2835-rpi.dtsi with W=1 leads to the following warning: Warning (avoid_unnecessary_addr_size): /soc/firmware: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Fix this by removing these unnecessary properties. Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index a8b175a9e229..9d11cb759b5b 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -19,8 +19,6 @@ soc { firmware: firmware { compatible = "raspberrypi,bcm2835-firmware", "simple-bus"; - #address-cells = <0>; - #size-cells = <0>; mboxes = <&mailbox>; }; From b02d6197c28e157f5839d8ebf87e758095cc4944 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 30 Dec 2018 17:28:35 +0100 Subject: [PATCH 315/506] ARM: dts: bcm2835: Fix labels for GPIO 0,1 According to the schematics for all RPis with a 40 pin header, the GPIOs 0 and 1 are labeled as ID_SD and ID_SC. In order to clarify that is a I2C bus, append the third letter. Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 4 ++-- arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 4 ++-- arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 4 ++-- arch/arm/boot/dts/bcm2835-rpi-zero.dts | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index 2cd9c5e4f892..db8a6017f220 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -31,8 +31,8 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "SDA0", - "SCL0", + gpio-line-names = "ID_SDA", + "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index cfbdaacbaeba..1e40d672b055 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -33,8 +33,8 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "SDA0", - "SCL0", + gpio-line-names = "ID_SDA", + "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index 644d907bafbb..5765d3411fd6 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -40,8 +40,8 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "GPIO0", - "GPIO1", + gpio-line-names = "ID_SDA", + "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index 00323ba8f7de..3b35a8a4a55f 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -28,8 +28,8 @@ * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ - gpio-line-names = "SDA0", - "SCL0", + gpio-line-names = "ID_SDA", + "ID_SCL", "SDA1", "SCL1", "GPIO_GCLK", From 74a04e07f9d5add08920d8db0779ddd676f392a0 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 30 Dec 2018 12:50:30 +0100 Subject: [PATCH 316/506] ARM: dts: bcm2837-rpi-3-b: Use consistent label for HDMI hotplug This make the GPIO label for HDMI hotplug more consistent to the other boards. Signed-off-by: Stefan Wahren Tested-by: Peter Robinson Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index 9abb9c55e6e4..31b1c03e0ff7 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -39,7 +39,7 @@ "WL_ON", "STATUS_LED", "LAN_RUN", - "HPD_N", + "HDMI_HPD_N", "CAM_GPIO0", "CAM_GPIO1", "PWR_LOW_N"; From ef528c37e4c5e6c00e2f211559569002786bd6a2 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Thu, 10 Jan 2019 20:22:55 +0100 Subject: [PATCH 317/506] ARM: dts: bcm2837-rpi-3-b-plus: Clarify label for STATUS_LED The RPI 3 B+ provides control to both LEDs (PWR and ACT). So append the first letter of the LED color (like in the schematics) in order to clarify this. Signed-off-by: Stefan Wahren Tested-by: Peter Robinson Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index 7d65013f5a4b..d3ec6cd86bfc 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -42,7 +42,7 @@ #gpio-cells = <2>; gpio-line-names = "BT_ON", "WL_ON", - "STATUS_LED", + "STATUS_LED_R", "LAN_RUN", "", "CAM_GPIO0", From 0b559d5c5baf2577bc23cc9e323e3dad45fef99d Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 1 Jan 2019 18:29:08 +0100 Subject: [PATCH 318/506] ARM: dts: bcm283x: Add missing GPIO line names The GPIO sysfs is deprecated and disabled in the defconfig files. So in order to motivate the usage of the new GPIO character device API add the missing GPIO line names for Raspberry Pi 2 and 3. In the lack of full schematics i would leave all undocumented pins as unnamed. Signed-off-by: Stefan Wahren Tested-by: Peter Robinson Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 66 ++++++++++++++++++++ arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 70 ++++++++++++++++++++++ arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 70 ++++++++++++++++++++++ 3 files changed, 206 insertions(+) diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index 871fc4a558cf..7b4e651bafdd 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -28,6 +28,72 @@ }; &gpio { + /* + * Taken from rpi_SCH_2b_1p2_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "", /* GPIO30 */ + "LAN_RUN", + "CAM_GPIO1", + "", /* GPIO33 */ + "", /* GPIO34 */ + "PWR_LOW_N", + "", /* GPIO36 */ + "", /* GPIO37 */ + "USB_LIMIT", + "", /* GPIO39 */ + "PWM0_OUT", + "CAM_GPIO0", + "SMPS_SCL", + "SMPS_SDA", + "ETHCLK", + "PWM1_OUT", + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index d3ec6cd86bfc..c6fa34c24100 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -52,6 +52,76 @@ }; }; +&gpio { + /* + * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_G", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "ETHCLK", + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; +}; + &hdmi { hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index 31b1c03e0ff7..ce71f578c51a 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -47,6 +47,76 @@ }; }; +&gpio { + /* + * Taken from rpi_SCH_3b_1p2_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "", /* GPIO 28 */ + "LAN_RUN_BOOT", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "ETHCLK", + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; +}; + &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; From ab1b4ef966af90ad79fa3c4c124e47915cddde10 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sat, 19 Jan 2019 17:35:47 +0100 Subject: [PATCH 319/506] ARM: dts: bcm2835-rpi-zero-w: Drop unnecessary pinctrl There is no need to specify a pinctrl for the reset GPIO. So we better remove this avoid a potential conflict between pinctrl and pwrseq after the pinmux driver has been changed to strict: pinctrl-bcm2835 20200000.gpio: pin gpio41 already requested by wifi-pwrseq; cannot claim for pinctrl-bcm2835:499 pinctrl-bcm2835 20200000.gpio: pin-41 (pinctrl-bcm2835:499) status -22 pwrseq_simple: probe of wifi-pwrseq failed with error -22 Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index 5765d3411fd6..ba0167df6c5f 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -25,8 +25,6 @@ wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wl_on>; reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; }; }; @@ -98,11 +96,6 @@ "SD_DATA3_R"; pinctrl-0 = <&gpioout &alt0>; - - wl_on: wl-on { - brcm,pins = <41>; - brcm,function = ; - }; }; &hdmi { From ad37549cb5dca27d0d6d9e603dd2510a6504a7b4 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 25 Jan 2019 17:25:58 +0100 Subject: [PATCH 320/506] arm64: dts: imx8mq: add USB nodes It adds USB device and phy nodes for imx8mq SoC. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 64 +++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 603b2ec80ed6..c2c5f3ee3ce3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -516,6 +516,70 @@ }; }; + usb_dwc3_0: usb@38100000 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + reg = <0x38100000 0x10000>; + clocks = <&clk IMX8MQ_CLK_USB_BUS>, + <&clk IMX8MQ_CLK_USB_CORE_REF>, + <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>; + clock-names = "bus_early", "ref", "suspend"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, + <&clk IMX8MQ_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <500000000>, <100000000>; + interrupts = ; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + power-domains = <&pgc_otg1>; + usb3-resume-missing-cas; + status = "disabled"; + }; + + usb3_phy0: usb-phy@381f0040 { + compatible = "fsl,imx8mq-usb-phy"; + reg = <0x381f0040 0x40>; + clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <100000000>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb_dwc3_1: usb@38200000 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + reg = <0x38200000 0x10000>; + clocks = <&clk IMX8MQ_CLK_USB_BUS>, + <&clk IMX8MQ_CLK_USB_CORE_REF>, + <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>; + clock-names = "bus_early", "ref", "suspend"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, + <&clk IMX8MQ_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <500000000>, <100000000>; + interrupts = ; + phys = <&usb3_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + power-domains = <&pgc_otg2>; + usb3-resume-missing-cas; + status = "disabled"; + }; + + usb3_phy1: usb-phy@382f0040 { + compatible = "fsl,imx8mq-usb-phy"; + reg = <0x382f0040 0x40>; + clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <100000000>; + #phy-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ From 49e6d2b2f9b1cf339f69a70e83416444ee8332cd Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 25 Jan 2019 17:25:59 +0100 Subject: [PATCH 321/506] arm64: dts: imx8mq-evk: enable USB nodes for USB3 host It enables USB3 host device support for imx8mq-evk board. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 64acccc4bfcb..35955be53209 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -137,6 +137,15 @@ status = "okay"; }; +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; From 55b0b15a0220bb933a30a20e848837de3f5e180e Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 28 Jan 2019 09:52:11 +0000 Subject: [PATCH 322/506] arm64: dts: imx8mq-evk: add missing MDIO / PHY nodes Populate the fec1 node with the missing MDIO and PHY entries. Signed-off-by: Carlo Caione Reviewed-by: Fabio Estevam Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 35955be53209..d4b5335de071 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -37,7 +37,18 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; }; &i2c1 { From f196ef19fb1a4ebe75bc7700f7c39161176c7410 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 28 Jan 2019 09:52:12 +0000 Subject: [PATCH 323/506] arm64: dts: imx8mq-evk: Add fsl,magic-packet property Add the fsl,magic-packet property in the fec node. Signed-off-by: Carlo Caione Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index d4b5335de071..00b2904e16eb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -38,6 +38,7 @@ pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; + fsl,magic-packet; status = "okay"; mdio { From 25f6f54ff025f17e573a473d1e4b0f58950b331e Mon Sep 17 00:00:00 2001 From: Harald Geyer Date: Wed, 30 Jan 2019 11:11:58 +0000 Subject: [PATCH 324/506] arm64: dts: allwinner: a64: teres-i: enable power supplies TERES-I has ACIN connector and battery. Signed-off-by: Harald Geyer Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index f9eede0a8bd3..7b7b14ba58e6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -145,6 +145,14 @@ #include "axp803.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <2800000>; From bd80be88e05792db948bf3567a216743fdea5027 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Fri, 28 Dec 2018 23:09:26 +0100 Subject: [PATCH 325/506] ARM: dts: add Raspberry Pi 3 A+ The Raspberry Pi 3 A+ is similar to the Pi 3 B+ but has only 512 MB RAM, 1 USB 2.0 port and no Ethernet. Compared to the Raspberry Pi 3 B it isn't possible to control BT_ON and WL_ON separately. Signed-off-by: Stefan Wahren Acked-by: Eric Anholt --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts | 175 +++++++++++++++++++++ 2 files changed, 176 insertions(+) create mode 100644 arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..d98d51d358f7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2835-rpi-a-plus.dtb \ bcm2835-rpi-cm1-io1.dtb \ bcm2836-rpi-2-b.dtb \ + bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ bcm2837-rpi-cm3-io3.dtb \ diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts new file mode 100644 index 000000000000..e9fadd338227 --- /dev/null +++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837"; + model = "Raspberry Pi 3 Model A+"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + memory { + reg = <0 0x20000000>; + }; + + leds { + act { + gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; + }; + + pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&firmware { + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "", + "BT_WL_ON", + "STATUS_LED_R", + "", + "", + "CAM_GPIO0", + "CAM_GPIO1", + ""; + status = "okay"; + }; +}; + +&gpio { + /* + * This is mostly based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_G", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + "PWM0_OUT", + "PWM1_OUT", + "", /* GPIO42 */ + "WIFI_CLK", + "SDA0", + "SCL0", + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; +}; + +&hdmi { + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; + status = "okay"; +}; + +/* + * SDHCI is used to control the SDIO for wireless + * + * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven + * by a single GPIO. We can't give GPIO control to one of the drivers, + * otherwise the other part would get unexpectedly disturbed. + */ +&sdhci { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_gpio34>; + status = "okay"; + bus-width = <4>; + non-removable; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SDHOST is used to drive the SD card */ +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + status = "okay"; + bus-width = <4>; +}; + +/* uart0 communicates with the BT module */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + }; +}; + +/* uart1 is mapped to the pin header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; From 441d8020d8fc8654698f5518cdf76832f84101f4 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Fri, 28 Dec 2018 23:09:27 +0100 Subject: [PATCH 326/506] arm64: dts: broadcom: Add reference to RPi 3 A+ This adds a reference to the dts of the Raspberry Pi 3 A+, so we don't need to maintain the content in arm64. Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt --- arch/arm64/boot/dts/broadcom/Makefile | 3 ++- arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index 667ca989c11b..d1d31ccad758 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb \ +dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-a-plus.dtb \ + bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ bcm2837-rpi-cm3-io3.dtb diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts new file mode 100644 index 000000000000..f0ec56a1c4d7 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arm/bcm2837-rpi-3-a-plus.dts" From 026dad8f5873859178e360ac622ef7d168843799 Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Mon, 21 Jan 2019 14:33:28 -0700 Subject: [PATCH 327/506] arm64: dts: qcom: msm8998: Add USB-related nodes Add nodes for USB and related PHYs. Signed-off-by: Jeffrey Hugo Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 22 ++++++ arch/arm64/boot/dts/qcom/msm8998.dtsi | 92 +++++++++++++++++++++++ 2 files changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi index 288adbfe9086..f0901067b043 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi @@ -65,6 +65,13 @@ status = "okay"; }; +&qusb2phy { + status = "okay"; + + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +}; + &rpm_requests { pm8998-regulators { compatible = "qcom,rpm-pm8998-regulators"; @@ -259,3 +266,18 @@ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; }; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "host"; /* Force to host until we have Type-C hooked up */ +}; + +&usb3phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 7136ab14df42..ffc4a88232d6 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -540,6 +540,11 @@ reg = <0x780000 0x621c>; #address-cells = <1>; #size-cells = <1>; + + qusb2_hstx_trim: hstx-trim@423a { + reg = <0x423a 0x1>; + bits = <0 4>; + }; }; gcc: clock-controller@100000 { @@ -607,6 +612,93 @@ #mbox-cells = <1>; }; + usb3: usb@a8f8800 { + compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; + reg = <0x0a8f8800 0x400>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_AGGRE1_USB3_AXI_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + interrupts = , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc USB_30_GDSC>; + + resets = <&gcc GCC_USB_30_BCR>; + + usb3_dwc3: dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xcd00>; + interrupts = ; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&qusb2phy>, <&usb1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + }; + }; + + usb3phy: phy@c010000 { + compatible = "qcom,msm8998-qmp-usb3-phy"; + reg = <0x0c010000 0x18c>; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_CLKREF_CLK>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy", "common"; + + usb1_ssphy: lane@c010200 { + reg = <0xc010200 0x128>, + <0xc010400 0x200>, + <0xc010c00 0x20c>, + <0xc010600 0x128>, + <0xc010800 0x200>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; + + qusb2phy: phy@c012000 { + compatible = "qcom,msm8998-qusb2-phy"; + reg = <0x0c012000 0x2a8>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + nvmem-cells = <&qusb2_hstx_trim>; + }; + sdhc2: sdhci@c0a4900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>; From 1fb28636e83f50ca1f6eab294f2e13971994f8ec Mon Sep 17 00:00:00 2001 From: Marc Gonzalez Date: Wed, 30 Jan 2019 17:24:10 +0100 Subject: [PATCH 328/506] arm64: dts: qcom: msm8998: Add rpmcc node Add MSM8998 Resource Power Manager Clock Controller DT node. Tested-by: Sai Prakash Ranjan Reviewed-by: Jeffrey Hugo Reviewed-by: Bjorn Andersson Signed-off-by: Marc Gonzalez Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index ffc4a88232d6..5091ac07a2af 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -3,6 +3,7 @@ #include #include +#include #include / { @@ -266,6 +267,11 @@ rpm_requests: rpm-requests { compatible = "qcom,rpm-msm8998"; qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; + #clock-cells = <1>; + }; }; }; From bf75731dbc97556bf3defdb4b152fd7707acc14c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 25 Jan 2019 10:14:22 -0800 Subject: [PATCH 329/506] arm64: dts: qcom: qcs404: Add rpmcc node Add the rpm clock controller node, to provide the low-noise baseband clock for the USB PHYs, among other things. Reviewed-by: Niklas Cassel Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 76699435c8bd..e8fd26633d57 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -3,6 +3,7 @@ #include #include +#include / { interrupt-parent = <&intc>; @@ -224,6 +225,11 @@ rpm_requests: glink-channel { compatible = "qcom,rpm-qcs404"; qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-qcs404"; + #clock-cells = <1>; + }; }; }; From 4cce115f128ae6402cfbdda05cc654c5a9744c01 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 31 Jan 2019 12:20:55 -0800 Subject: [PATCH 330/506] arm64: dts: qcom: msm8996: Disabled VFE SMMU Initializing the SMMU trips a security violation, so disable the VFE SMMU for now. Fixes: f3442ab97257 ("arm64: dts: qcom: msm8996: Add VFE SMMU node") Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 6ba96916c66d..c761269caf80 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1000,7 +1000,7 @@ clock-names = "iface", "bus"; #iommu-cells = <1>; - status = "ok"; + status = "disabled"; }; camss: camss@a00000 { From 5e8204893f62792ebeed88ae505cf658b216eaa0 Mon Sep 17 00:00:00 2001 From: David Dai Date: Wed, 16 Jan 2019 18:11:01 +0200 Subject: [PATCH 331/506] arm64: dts: sdm845: Add interconnect provider DT nodes Add RSC (Resource State Coordinator) provider dictating network-on-chip interconnect bus performance found on SDM845-based platforms. Signed-off-by: David Dai Signed-off-by: Georgi Djakov Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0ec827394e92..2194794fe84d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2124,6 +2124,11 @@ }; }; }; + + rsc_hlos: interconnect { + compatible = "qcom,sdm845-rsc-hlos"; + #interconnect-cells = <1>; + }; }; intc: interrupt-controller@17a00000 { From 803346a8efc9062da732c9d3e0b8e7079096f1ad Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Tue, 29 Jan 2019 08:33:24 -0300 Subject: [PATCH 332/506] arm64: dts: rockchip: Enable HDMI audio devices on rk3399-rock960 This commit enable the hdmi-sound and i2s2 devices needed to have audio over HDMI on both rock960 and the related ficus board. Signed-off-by: Ezequiel Garcia Acked-by: Manivannan Sadhasivam Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi index 56abbb08c133..fecb133b0ed2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi @@ -94,6 +94,10 @@ status = "okay"; }; +&hdmi_sound { + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; @@ -336,6 +340,10 @@ status = "okay"; }; +&i2s2 { + status = "okay"; +}; + &io_domains { bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ From 2670712c83db0b9c92251b450ec5f81222b80935 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrius=20=C5=A0tikonas?= Date: Fri, 1 Feb 2019 22:55:06 +0000 Subject: [PATCH 333/506] arm64: dts: rockchip: enable mali power supply on rk3399-rockpro64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the gpu node and add the supplying regulator Signed-off-by: Andrius Štikonas Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts index be78172abc09..ae87a84327f2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts @@ -212,6 +212,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; From b86e2f24414259413b193647e3634f9391747ea6 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 31 Jan 2019 10:47:07 -0200 Subject: [PATCH 334/506] ARM: dts: rockchip: Fix vcc5/6-supply representation on rv1108-elgin On rv1108-elgin-r1 board the RK805 VCC5 and VCC6 supplies come from the BUCK2 regulator at 2.2V, so fix the representation in the device tree. While at it, rename it from vdd_cam to vdd_buck2, which is a better name for the regulator label. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108-elgin-r1.dts | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts index 658057d871af..66688fdf4fd8 100644 --- a/arch/arm/boot/dts/rv1108-elgin-r1.dts +++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts @@ -74,8 +74,8 @@ vcc2-supply = <&vcc_sys>; vcc3-supply = <&vcc_sys>; vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; + vcc5-supply = <&vdd_buck2>; + vcc6-supply = <&vdd_buck2>; regulators { vdd_core: DCDC_REG1 { @@ -90,10 +90,12 @@ }; }; - vdd_cam: DCDC_REG2 { - regulator-name= "vdd_cam"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <2000000>; + vdd_buck2: DCDC_REG2 { + regulator-name= "vdd_buck2"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-state-disabled; }; From fac33118110029402faa68d5ddfce21d771407c5 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 31 Jan 2019 10:47:08 -0200 Subject: [PATCH 335/506] ARM: dts: rockchip: Use the correct regulator properties on rv1108-elgin The following properties: - regulator-state-enabled - regulator-state-disabled - regulator-state-uv are not valid ones as per Documentation/devicetree/bindings/regulator/regulator.txt Fix it by using the correct properties as per the dt bindings. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108-elgin-r1.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts index 66688fdf4fd8..1c4507b66fdd 100644 --- a/arch/arm/boot/dts/rv1108-elgin-r1.dts +++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts @@ -85,8 +85,8 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; - regulator-state-uv = <900000>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; }; }; @@ -97,7 +97,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-disabled; + regulator-off-in-suspend; }; }; @@ -106,7 +106,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; + regulator-on-in-suspend; }; }; @@ -117,8 +117,8 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; - regulator-state-uv = <3300000>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; }; }; @@ -129,7 +129,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-disabled; + regulator-off-in-suspend; }; }; @@ -140,7 +140,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-disabled; + regulator-off-in-suspend; }; }; @@ -151,8 +151,8 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; - regulator-state-uv = <1000000>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; }; }; }; From 085e42fbbd34419f95c4a3a26eca59a1a39a730c Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 31 Jan 2019 10:47:09 -0200 Subject: [PATCH 336/506] ARM: dts: rockchip: Use the correct regulator properties on rv1108-evb The following properties: - regulator-state-enabled - regulator-state-disabled - regulator-state-uv are not valid ones as per Documentation/devicetree/bindings/regulator/regulator.txt Fix it by using the correct properties as per the dt bindings. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108-evb.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts index 203d83e3bbf5..30f3d0470ad9 100644 --- a/arch/arm/boot/dts/rv1108-evb.dts +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -97,8 +97,8 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; - regulator-state-uv = <900000>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; }; }; @@ -107,7 +107,7 @@ regulator-min-microvolt = <700000>; regulator-max-microvolt = <2000000>; regulator-state-mem { - regulator-state-disabled; + regulator-off-in-suspend; }; }; @@ -116,7 +116,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; + regulator-on-in-suspend; }; }; @@ -127,8 +127,8 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; - regulator-state-uv = <3300000>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; }; }; @@ -139,7 +139,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-disabled; + regulator-off-in-suspend; }; }; @@ -150,7 +150,7 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-disabled; + regulator-off-in-suspend; }; }; @@ -161,8 +161,8 @@ regulator-always-on; regulator-boot-on; regulator-state-mem { - regulator-state-enabled; - regulator-state-uv = <1000000>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; }; }; }; From 3e3380d0675d5e20b0af067d60cb947a4348bf9b Mon Sep 17 00:00:00 2001 From: Mathieu Malaterre Date: Fri, 15 Dec 2017 13:46:39 +0100 Subject: [PATCH 337/506] ARM: dts: lpc32xx: Remove leading 0x and 0s from bindings notation Improve the DTS files by removing all the leading "0x" and zeros to fix the following dtc warnings: Warning (unit_address_format): Node /XXX unit name should not have leading "0x" and Warning (unit_address_format): Node /XXX unit name should not have leading 0s Converted using the following command: find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec sed -i -e "s/@\([0-9a-fA-FxX\.;:#]+\)\s*{/@\L\1 {/g" -e "s/@0x\(.*\) {/@\1 {/g" -e "s/@0+\(.*\) {/@\1 {/g" {} + For simplicity, two sed expressions were used to solve each warnings separately. To make the regex expression more robust a few other issues were resolved, namely setting unit-address to lower case, and adding a whitespace before the opening curly brace: https://elinux.org/Device_Tree_Linux#Linux_conventions This will solve as a side effect warning: Warning (simple_bus_reg): Node /XXX@ simple-bus unit address format error, expected "" This is a follow up to commit 4c9847b7375a ("dt-bindings: Remove leading 0x from bindings notation") Reported-by: David Daney Suggested-by: Rob Herring Signed-off-by: Mathieu Malaterre [vzapolskiy: fixed commit message to pass checkpatch.pl test] Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index b7303a4e4236..ed0d6fb20122 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -230,7 +230,7 @@ status = "disabled"; }; - i2s1: i2s@2009C000 { + i2s1: i2s@2009c000 { compatible = "nxp,lpc3220-i2s"; reg = <0x2009C000 0x1000>; }; @@ -273,7 +273,7 @@ status = "disabled"; }; - i2c1: i2c@400A0000 { + i2c1: i2c@400a0000 { compatible = "nxp,pnx-i2c"; reg = <0x400A0000 0x100>; interrupt-parent = <&sic1>; @@ -284,7 +284,7 @@ clocks = <&clk LPC32XX_CLK_I2C1>; }; - i2c2: i2c@400A8000 { + i2c2: i2c@400a8000 { compatible = "nxp,pnx-i2c"; reg = <0x400A8000 0x100>; interrupt-parent = <&sic1>; @@ -295,7 +295,7 @@ clocks = <&clk LPC32XX_CLK_I2C2>; }; - mpwm: mpwm@400E8000 { + mpwm: mpwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400E8000 0x78>; status = "disabled"; @@ -394,7 +394,7 @@ #gpio-cells = <3>; /* bank, pin, flags */ }; - timer4: timer@4002C000 { + timer4: timer@4002c000 { compatible = "nxp,lpc3220-timer"; reg = <0x4002C000 0x1000>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; @@ -412,7 +412,7 @@ status = "disabled"; }; - watchdog: watchdog@4003C000 { + watchdog: watchdog@4003c000 { compatible = "nxp,pnx4008-wdt"; reg = <0x4003C000 0x1000>; clocks = <&clk LPC32XX_CLK_WDOG>; @@ -451,7 +451,7 @@ status = "disabled"; }; - timer1: timer@4004C000 { + timer1: timer@4004c000 { compatible = "nxp,lpc3220-timer"; reg = <0x4004C000 0x1000>; interrupts = <17 IRQ_TYPE_LEVEL_LOW>; @@ -475,7 +475,7 @@ status = "disabled"; }; - pwm1: pwm@4005C000 { + pwm1: pwm@4005c000 { compatible = "nxp,lpc3220-pwm"; reg = <0x4005C000 0x4>; clocks = <&clk LPC32XX_CLK_PWM1>; @@ -484,7 +484,7 @@ status = "disabled"; }; - pwm2: pwm@4005C004 { + pwm2: pwm@4005c004 { compatible = "nxp,lpc3220-pwm"; reg = <0x4005C004 0x4>; clocks = <&clk LPC32XX_CLK_PWM2>; From 623cdcc76d2fb50696c6d7523029b6aeebbb19b7 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 11 Oct 2018 15:31:03 +0300 Subject: [PATCH 338/506] ARM: dts: Add DT for MYIR Tech MYD-LPC4357 Development Board Add support for MYIR Tech MYD-LPC4357 Development Board and MY-LCD70TP-C 7" TFT LCD module with Innolux AT070TN82 panel. The board contains quite rich periferals, the list features NXP LPC4357 SoC, 32 MB SDRAM, 4 MB SPI Flash, audio input/output interface, LCD panel, micro SD card slot, USB, USB OTG, Ethernet, 2 CAN ports, 4 UARTs, I2C and SPI interfaces routed to external interface. More information can be found on http://www.myirtech.com/list.asp?id=422 Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/lpc4357-myd-lpc4357.dts | 619 ++++++++++++++++++++++ 2 files changed, 621 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/lpc4357-myd-lpc4357.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..a30a912f0282 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -313,7 +313,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ dtb-$(CONFIG_ARCH_LPC18XX) += \ lpc4337-ciaa.dtb \ lpc4350-hitex-eval.dtb \ - lpc4357-ea4357-devkit.dtb + lpc4357-ea4357-devkit.dtb \ + lpc4357-myd-lpc4357.dtb dtb-$(CONFIG_ARCH_LPC32XX) += \ lpc3250-ea3250.dtb \ lpc3250-phy3250.dtb diff --git a/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts new file mode 100644 index 000000000000..1f84654df50c --- /dev/null +++ b/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts @@ -0,0 +1,619 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel + * + * Copyright (C) 2016-2018 Vladimir Zapolskiy + */ + +/dts-v1/; + +#include "lpc18xx.dtsi" +#include "lpc4357.dtsi" + +#include + +/ { + model = "MYIR Tech LPC4357 Development Board"; + compatible = "myir,myd-lpc4357", "nxp,lpc4357"; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + memory@28000000 { + device_type = "memory"; + reg = <0x28000000 0x2000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led1 { + gpios = <&gpio LPC_GPIO(6,15) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + gpios = <&gpio LPC_GPIO(6,16) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + gpios = <&gpio LPC_GPIO(6,17) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led4 { + gpios = <&gpio LPC_GPIO(6,10) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led5 { + gpios = <&gpio LPC_GPIO(7,14) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led6 { + gpios = <&gpio LPC_GPIO(6,14) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + panel: panel { + compatible = "innolux,at070tn92"; + + port { + panel_input: endpoint { + remote-endpoint = <&lcdc_output>; + }; + }; + }; + + vcc: vcc_fixed { + compatible = "regulator-fixed"; + regulator-name = "vcc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vmmc: vmmc_fixed { + compatible = "regulator-fixed"; + regulator-name = "vmmc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&pinctrl { + can0_pins: can0-pins { + can_rd_cfg { + pins = "p3_1"; + function = "can0"; + input-enable; + }; + + can_td_cfg { + pins = "p3_2"; + function = "can0"; + }; + }; + + can1_pins: can1-pins { + can_rd_cfg { + pins = "pe_1"; + function = "can1"; + input-enable; + }; + + can_td_cfg { + pins = "pe_0"; + function = "can1"; + }; + }; + + emc_pins: emc-pins { + emc_addr0_22_cfg { + pins = "p2_9", "p2_10", "p2_11", "p2_12", + "p2_13", "p1_0", "p1_1", "p1_2", + "p2_8", "p2_7", "p2_6", "p2_2", + "p2_1", "p2_0", "p6_8", "p6_7", + "pd_16", "pd_15", "pe_0", "pe_1", + "pe_2", "pe_3", "pe_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_data0_15_cfg { + pins = "p1_7", "p1_8", "p1_9", "p1_10", + "p1_11", "p1_12", "p1_13", "p1_14", + "p5_4", "p5_5", "p5_6", "p5_7", + "p5_0", "p5_1", "p5_2", "p5_3"; + function = "emc"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + emc_we_oe_cfg { + pins = "p1_6", "p1_3"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_cs0_cfg { + pins = "p1_5"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_dqm0_1_cfg { + pins = "p6_12", "p6_10"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_ras_cas_cfg { + pins = "p6_5", "p6_4"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_dycs0_cfg { + pins = "p6_9"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_cke_cfg { + pins = "p6_11"; + function = "emc"; + slew-rate = <1>; + bias-disable; + }; + + emc_sdram_clock_cfg { + pins = "clk0"; + function = "emc"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + }; + + enet_rmii_pins: enet-rmii-pins { + enet_rmii_rxd_cfg { + pins = "p1_15", "p0_0"; + function = "enet"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + enet_rmii_txd_cfg { + pins = "p1_18", "p1_20"; + function = "enet"; + slew-rate = <1>; + bias-disable; + }; + + enet_rmii_rx_dv_cfg { + pins = "p1_16"; + function = "enet"; + input-enable; + input-schmitt-disable; + bias-disable; + }; + + enet_mdio_cfg { + pins = "p1_17"; + function = "enet"; + input-enable; + input-schmitt-disable; + bias-disable; + }; + + enet_mdc_cfg { + pins = "pc_1"; + function = "enet"; + slew-rate = <1>; + bias-disable; + }; + + enet_rmii_tx_en_cfg { + pins = "p0_1"; + function = "enet"; + bias-disable; + }; + + enet_ref_clk_cfg { + pins = "p1_19"; + function = "enet"; + slew-rate = <1>; + input-enable; + input-schmitt-disable; + bias-disable; + }; + }; + + i2c0_pins: i2c0-pins { + i2c0_pins_cfg { + pins = "i2c0_scl", "i2c0_sda"; + function = "i2c0"; + input-enable; + }; + }; + + i2c1_pins: i2c1-pins { + i2c1_pins_cfg { + pins = "pe_15", "pe_13"; + function = "i2c1"; + input-enable; + }; + }; + + lcd_pins: lcd-pins { + lcd_vd0_23_cfg { + pins = "p4_1", "p4_4", "p4_3", "p4_2", + "p8_7", "p8_6", "p8_5", "p8_4", + "p7_5", "p4_8", "p4_10", "p4_9", + "p8_3", "pb_6", "pb_5", "pb_4", + "p7_4", "p7_3", "p7_2", "p7_1", + "pb_3", "pb_2", "pb_1", "pb_0"; + function = "lcd"; + }; + + lcd_vsync_en_dclk_lp_pwr_cfg { + pins = "p4_5", "p4_6", "p4_7", "p7_6", "p7_7"; + function = "lcd"; + }; + }; + + led_pins: led-pins { + led_1_6_cfg { + pins = "pd_1", "pd_2", "pd_3", "pc_11", "pe_14", "pd_0"; + function = "gpio"; + bias-pull-down; + }; + }; + + sdmmc_pins: sdmmc-pins { + sdmmc_clk_cfg { + pins = "pc_0"; + function = "sdmmc"; + slew-rate = <1>; + bias-pull-down; + }; + + sdmmc_cmd_dat0_3_cfg { + pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; + function = "sdmmc"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + sdmmc_cd_cfg { + pins = "pc_8"; + function = "sdmmc"; + input-enable; + bias-pull-down; + }; + }; + + spifi_pins: spifi-pins { + spifi_sck_cfg { + pins = "p3_3"; + function = "spifi"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + spifi_mosi_miso_sio2_sio3_cfg { + pins = "p3_7", "p3_6", "p3_5", "p3_4"; + function = "spifi"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-disable; + }; + + spifi_cs_cfg { + pins = "p3_8"; + function = "spifi"; + bias-disable; + }; + }; + + ssp1_pins: ssp1-pins { + ssp1_sck_cfg { + pins = "pf_4"; + function = "ssp1"; + slew-rate = <1>; + bias-pull-down; + }; + + ssp1_miso_cfg { + pins = "pf_6"; + function = "ssp1"; + input-enable; + input-schmitt-disable; + slew-rate = <1>; + bias-pull-down; + }; + + ssp1_mosi_cfg { + pins = "pf_7"; + function = "ssp1"; + slew-rate = <1>; + bias-pull-down; + }; + + ssp1_ssel_cfg { + pins = "pf_5"; + function = "gpio"; + bias-disable; + }; + }; + + uart0_pins: uart0-pins { + uart0_rxd_cfg { + pins = "pf_11"; + function = "uart0"; + input-enable; + input-schmitt-disable; + bias-disable; + }; + + uart0_clk_dir_txd_cfg { + pins = "pf_8", "pf_9", "pf_10"; + function = "uart0"; + bias-pull-down; + }; + }; + + uart1_pins: uart1-pins { + uart1_rxd_cfg { + pins = "pc_14"; + function = "uart1"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + uart1_dtr_txd_cfg { + pins = "pc_12", "pc_13"; + function = "uart1"; + bias-pull-down; + }; + }; + + uart2_pins: uart2-pins { + uart2_rxd_cfg { + pins = "pa_2"; + function = "uart2"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + uart2_txd_cfg { + pins = "pa_1"; + function = "uart2"; + bias-pull-down; + }; + }; + + uart3_pins: uart3-pins { + uart3_rx_cfg { + pins = "p2_4"; + function = "uart3"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + uart3_tx_cfg { + pins = "p2_3"; + function = "uart3"; + bias-pull-down; + }; + }; + + usb0_pins: usb0-pins { + usb0_pwr_enable_cfg { + pins = "p6_3"; + function = "usb0"; + }; + + usb0_pwr_fault_cfg { + pins = "p8_0"; + function = "usb0"; + bias-disable; + input-enable; + }; + }; +}; + +&adc1 { + status = "okay"; + vref-supply = <&vcc>; +}; + +&can0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins>; +}; + +/* Pin conflict with EMC, muxed by JP5 and JP6 */ +&can1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins>; +}; + +&emc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&emc_pins>; + + cs0 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mpmc,cs = <0>; + mpmc,memory-width = <16>; + mpmc,byte-lane-low; + mpmc,write-enable-delay = <0>; + mpmc,output-enable-delay = <0>; + mpmc,read-access-delay = <70>; + mpmc,page-mode-read-delay = <70>; + + /* SST/Microchip SST39VF1601 */ + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x400000>; + bank-width = <2>; + }; + }; +}; + +&enet_tx_clk { + clock-frequency = <50000000>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + sensor@49 { + compatible = "lm75"; + reg = <0x49>; + }; + + eeprom@50 { + compatible = "atmel,24c512"; + reg = <0x50>; + }; +}; + +&lcdc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + max-memory-bandwidth = <92240000>; + + port { + lcdc_output: endpoint { + remote-endpoint = <&panel_input>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; +}; + +&mac { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&enet_rmii_pins>; + phy-handle = <&phy1>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&mmcsd { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pins>; + bus-width = <4>; + vmmc-supply = <&vmmc>; +}; + +/* Pin conflict with SSP0, the latter is routed to J17 pin header */ +&spifi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifi_pins>; + + /* Atmel AT25DF321A */ + flash { + compatible = "jedec,spi-nor"; + spi-max-frequency = <51000000>; + spi-cpol; + spi-cpha; + }; +}; + +&ssp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp1_pins>; + num-cs = <1>; + cs-gpios = <&gpio LPC_GPIO(7,19) GPIO_ACTIVE_LOW>; +}; + +/* Routed to J17 pin header */ +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +/* RS485 */ +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +/* Routed to J17 pin header */ +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&usb0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; +}; From 3e88bc38b9f6fe4b69cecf81badd3c19fde97f97 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sat, 26 Jan 2019 16:29:20 +0200 Subject: [PATCH 339/506] ARM: dts: lpc32xx: add required clocks property to keypad device node NXP LPC32xx keypad controller requires a clock property to be defined. The change fixes the driver initialization problem: lpc32xx_keys 40050000.key: failed to get clock lpc32xx_keys: probe of 40050000.key failed with error -2 Fixes: 93898eb775e5 ("arm: dts: lpc32xx: add clock properties to device nodes") Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index ed0d6fb20122..d4368eeff1b9 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -462,6 +462,7 @@ key: key@40050000 { compatible = "nxp,lpc3220-key"; reg = <0x40050000 0x1000>; + clocks = <&clk LPC32XX_CLK_KEY>; interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; From 489261c45f0ebbc1c2813f337bbdf858267f5033 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sat, 26 Jan 2019 16:29:21 +0200 Subject: [PATCH 340/506] ARM: dts: lpc32xx: reparent keypad controller to SIC1 After switching to a new interrupt controller scheme by separating SIC1 and SIC2 from MIC interrupt controller just one SoC keypad controller was not taken into account, fix it now: WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:524 irq_domain_associate+0x50/0x1b0 error: hwirq 0x36 is too large for interrupt-controller@40008000 ... lpc32xx_keys 40050000.key: failed to get platform irq lpc32xx_keys: probe of 40050000.key failed with error -22 Fixes: 9b8ad3fb81ae ("ARM: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC") Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index d4368eeff1b9..4f8f671c3343 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -463,7 +463,8 @@ compatible = "nxp,lpc3220-key"; reg = <0x40050000 0x1000>; clocks = <&clk LPC32XX_CLK_KEY>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&sic1>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; From 7a0790a4121cbcd111cc537cdc801c46ccb789ee Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:39 +0200 Subject: [PATCH 341/506] ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller variant ARM PrimeCell PL111 LCD controller is found on On NXP LPC3230 and LPC3250 SoCs variants, the original reference in compatible property to an older one ARM PrimeCell PL110 is invalid. Fixes: e04920d9efcb3 ("ARM: LPC32xx: DTS files for device tree conversion") Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 4f8f671c3343..cfd422e7f774 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -139,7 +139,7 @@ }; clcd: clcd@31040000 { - compatible = "arm,pl110", "arm,primecell"; + compatible = "arm,pl111", "arm,primecell"; reg = <0x31040000 0x1000>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_LCD>; From 30fc01bae3cda747e7d9c352b1aa51ca113c8a9d Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:40 +0200 Subject: [PATCH 342/506] ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller clocks property The originally added ARM PrimeCell PL111 clocks property misses the required "clcdclk" clock, which is the same as a clock to enable the LCD controller on NXP LPC3230 and NXP LPC3250 SoCs. Fixes: 93898eb775e5 ("arm: dts: lpc32xx: add clock properties to device nodes") Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index cfd422e7f774..9ad3df11db0d 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -142,8 +142,8 @@ compatible = "arm,pl111", "arm,primecell"; reg = <0x31040000 0x1000>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_LCD>; - clock-names = "apb_pclk"; + clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>; + clock-names = "clcdclk", "apb_pclk"; status = "disabled"; }; From dc141b99fc36cf910a1d8d5ee30f43f2442fd1bd Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:41 +0200 Subject: [PATCH 343/506] ARM: dts: lpc32xx: phy3250: fix SD card regulator voltage The fixed voltage regulator on Phytec phyCORE-LPC3250 board, which supplies SD/MMC card's power, has a constant output voltage level of either 3.15V or 3.3V, the actual value depends on JP4 position, the power rail is referenced as VCC_SDIO in the board hardware manual. Fixes: d06670e96267 ("arm: dts: phy3250: add SD fixed regulator") Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-phy3250.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index 1e1c2f517a82..ffcf78631b22 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -49,8 +49,8 @@ sd_reg: regulator@2 { compatible = "regulator-fixed"; regulator-name = "sd_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; gpio = <&gpio 5 5 0>; enable-active-high; }; From 55ff232497703501ace5d1bb109a90d480724fd8 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:43 +0200 Subject: [PATCH 344/506] ARM: dts: lpc32xx: phy3250: remove regulators umbrella device node The originally added 'regulators' device node has a number of flaws, to name a few its children has unit addresses but no reg properties, the regulators are not captured by a device driver due to a missing 'simple-bus' compatible, the regulator names are selected by killing either alphabetical order or device node grouping property. The change removes 'regulators' device node and renames the regulators and labels. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-phy3250.dts | 63 +++++++++++++-------------- 1 file changed, 31 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index ffcf78631b22..d2dad2b541ff 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -25,37 +25,6 @@ reg = <0x80000000 0x4000000>; }; - regulators { - backlight_reg: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "backlight_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 4 0>; - enable-active-high; - regulator-boot-on; - }; - - lcd_reg: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "lcd_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 0 0>; - enable-active-high; - regulator-boot-on; - }; - - sd_reg: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "sd_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio 5 5 0>; - enable-active-high; - }; - }; - leds { compatible = "gpio-leds"; @@ -69,6 +38,36 @@ linux,default-trigger = "heartbeat"; }; }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "backlight"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio 5 4 0>; + enable-active-high; + regulator-boot-on; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio 5 0 0>; + enable-active-high; + regulator-boot-on; + }; + + reg_sd: regulator-sd { + compatible = "regulator-fixed"; + regulator-name = "sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio 5 5 0>; + enable-active-high; + regulator-boot-on; + }; }; &clcd { @@ -130,7 +129,7 @@ cd-gpios = <&gpio 3 1 0>; cd-inverted; bus-width = <4>; - vmmc-supply = <&sd_reg>; + vmmc-supply = <®_sd>; status = "okay"; }; From 3d48cda9dce15a6562de210596424f14e7a16d62 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:44 +0200 Subject: [PATCH 345/506] ARM: dts: lpc32xx: phy3250: setup LCD controller to panel interface The change adds description of Sharp LQ035Q7DB03 3.5" 320x240 TFT panel, which is connected to Phytec phyCORE-LPC3250 board, ARM PrimeCell PL111 LCD controller on NXP LPC3250 SoC gets its configuration appropriately to support graphics output to the panel. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-phy3250.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index d2dad2b541ff..aff72f14ad83 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -39,6 +39,17 @@ }; }; + panel: panel { + compatible = "sharp,lq035q7db03"; + power-supply = <®_lcd>; + + port { + panel_input: endpoint { + remote-endpoint = <&cldc_output>; + }; + }; + }; + reg_backlight: regulator-backlight { compatible = "regulator-fixed"; regulator-name = "backlight"; @@ -71,7 +82,15 @@ }; &clcd { + max-memory-bandwidth = <18710000>; status = "okay"; + + port { + cldc_output: endpoint { + remote-endpoint = <&panel_input>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; }; &i2c1 { From e5d48e7db11f717629b21291128e13c99d28eb94 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:45 +0200 Subject: [PATCH 346/506] ARM: dts: lpc32xx: phy3250: add unit address to memory device node The change adds a unit address to memory device node, the issue was reported as a unit_address_vs_reg warning by dtc. Root device node properties #address-cells and #size-cells were removed as inherited from lpc32xx.dtsi. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-phy3250.dts | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index aff72f14ad83..ebd19258e22b 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -1,6 +1,7 @@ /* * PHYTEC phyCORE-LPC3250 board * + * Copyright (C) 2015-2019 Vladimir Zapolskiy * Copyright 2012 Roland Stigge * * The code contained herein is licensed under the GNU General Public @@ -17,10 +18,8 @@ / { model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; compatible = "phytec,phy3250", "nxp,lpc3250"; - #address-cells = <1>; - #size-cells = <1>; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x4000000>; }; From ec54b138b170649ac33dfaaf7ade69727aef6ad1 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:46 +0200 Subject: [PATCH 347/506] ARM: dts: lpc32xx: ea3250: add unit address to memory device node The change adds a unit address to memory device node, the issue was reported as a unit_address_vs_reg warning by dtc. Root device node properties #address-cells and #size-cells were removed as inherited from lpc32xx.dtsi. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-ea3250.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts index 58ea0a4e7afa..ef6b3e74cd9f 100644 --- a/arch/arm/boot/dts/lpc3250-ea3250.dts +++ b/arch/arm/boot/dts/lpc3250-ea3250.dts @@ -17,10 +17,8 @@ / { model = "Embedded Artists LPC3250 board based on NXP LPC3250"; compatible = "ea,ea3250", "nxp,lpc3250"; - #address-cells = <1>; - #size-cells = <1>; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x4000000>; }; From 0293adf76ae96cea6e1690e79d9912c690bccde3 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 29 Jan 2019 21:20:47 +0200 Subject: [PATCH 348/506] ARM: dts: lpc32xx: ea3250: beautify gpio keys children nodes Regarding the 'gpio_keys' device node a dtc reports a couple of warnings: Warning (avoid_unnecessary_addr_size): /gpio_keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Warning (unit_address_vs_reg): /gpio_keys/button@21: node has a unit name, but no reg property The change fixes these issues and adds empty lines between adjacent children device nodes. The device node itself is renamed by substituting an underscore by hyphen to follow the standard naming convention of device tree nodes. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-ea3250.dts | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts index ef6b3e74cd9f..f46a11827ef6 100644 --- a/arch/arm/boot/dts/lpc3250-ea3250.dts +++ b/arch/arm/boot/dts/lpc3250-ea3250.dts @@ -23,56 +23,64 @@ reg = <0x80000000 0x4000000>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@21 { + + button { label = "Interrupt Key"; linux,code = <103>; gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ }; + key1 { label = "KEY1"; linux,code = <1>; gpios = <&pca9532 0 0>; }; + key2 { label = "KEY2"; linux,code = <2>; gpios = <&pca9532 1 0>; }; + key3 { label = "KEY3"; linux,code = <3>; gpios = <&pca9532 2 0>; }; + key4 { label = "KEY4"; linux,code = <4>; gpios = <&pca9532 3 0>; }; + joy0 { label = "Joystick Key 0"; linux,code = <10>; gpios = <&gpio 2 0 0>; /* P2.0 */ }; + joy1 { label = "Joystick Key 1"; linux,code = <11>; gpios = <&gpio 2 1 0>; /* P2.1 */ }; + joy2 { label = "Joystick Key 2"; linux,code = <12>; gpios = <&gpio 2 2 0>; /* P2.2 */ }; + joy3 { label = "Joystick Key 3"; linux,code = <13>; gpios = <&gpio 2 3 0>; /* P2.3 */ }; + joy4 { label = "Joystick Key 4"; linux,code = <14>; From 83b944174ad79825ae84a47af1a0354485b24602 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Thu, 24 Jan 2019 08:52:33 +0100 Subject: [PATCH 349/506] arm64: dts: hikey: Give wifi some time after power-on Somewhere along recent changes to power control of the wl1835, power-on became very unreliable on the hikey, failing like this: wl1271_sdio: probe of mmc2:0001:1 failed with error -16 wl1271_sdio: probe of mmc2:0001:2 failed with error -16 After playing with some dt parameters and comparing to other users of this chip, it turned out we need some power-on delay to make things stable again. In contrast to those other users which define 200 ms, the hikey would already be happy with 1 ms. Still, we use the safer 10 ms, like on the Ultra96. Fixes: ea452678734e ("arm64: dts: hikey: Fix WiFi support") Cc: #4.12+ Signed-off-by: Jan Kiszka Acked-by: Ulf Hansson Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 610235028cc7..ba946543dd0a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -118,6 +118,7 @@ reset-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; clocks = <&pmic>; clock-names = "ext_clock"; + post-power-on-delay-ms = <10>; power-off-delay-us = <10>; }; From 8d26c1390aec795d492b8de5e4437751e8805a1d Mon Sep 17 00:00:00 2001 From: Alistair Strachan Date: Wed, 23 Jan 2019 12:06:06 -0800 Subject: [PATCH 350/506] arm64: dts: hikey: Revert "Enable HS200 mode on eMMC" This reverts commit abd7d0972a192ee653efc7b151a6af69db58f2bb. This change was already partially reverted by John Stultz in commit 9c6d26df1fae ("arm64: dts: hikey: Fix eMMC corruption regression"). This change appears to cause controller resets and block read failures which prevents successful booting on some hikey boards. Cc: Ryan Grachek Cc: Wei Xu Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: stable #4.17+ Signed-off-by: Alistair Strachan Signed-off-by: John Stultz Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index ba946543dd0a..c14205cd6bf5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -301,7 +301,6 @@ dwmmc_0: dwmmc0@f723d000 { cap-mmc-highspeed; - mmc-hs200-1_8v; non-removable; bus-width = <0x8>; vmmc-supply = <&ldo19>; From a3f3332f412fe26fee186fb8abdcb4c8770dcd91 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 12 Dec 2018 10:36:44 +0100 Subject: [PATCH 351/506] arm64: dts: marvell: add interrupt support to ap806 thermal node Add interrupt properties in the thermal node as well as a critical trip point in the thermal-zone. Signed-off-by: Miquel Raynal Acked-by: Eduardo Valentin Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index 7d94c1fa592a..faca07de4d84 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -266,6 +266,8 @@ ap_thermal: thermal-sensor@80 { compatible = "marvell,armada-ap806-thermal"; reg = <0x80 0x10>; + interrupt-parent = <&sei>; + interrupts = <18>; #thermal-sensor-cells = <1>; }; }; @@ -276,16 +278,26 @@ * The thermal IP features one internal sensor plus, if applicable, one * remote channel wired to one sensor per CPU. * + * Only one thermal zone per AP/CP may trigger interrupts at a time, the + * first one that will have a critical trip point will be chosen. + * * The cooling maps are always empty as there are no cooling devices. */ thermal-zones { ap_thermal_ic: ap-thermal-ic { - polling-delay-passive = <1000>; - polling-delay = <1000>; + polling-delay-passive = <0>; /* Interrupt driven */ + polling-delay = <0>; /* Interrupt driven */ thermal-sensors = <&ap_thermal 0>; - trips { }; + trips { + ap_crit: ap-crit { + temperature = <100000>; /* mC degrees */ + hysteresis = <2000>; /* mC degrees */ + type = "critical"; + }; + }; + cooling-maps { }; }; From 47041b9780f14caa7fe696e22d041f05f5973ee7 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 12 Dec 2018 10:36:45 +0100 Subject: [PATCH 352/506] arm64: dts: marvell: add interrupt support to cp110 thermal node Add interrupt properties in the thermal node as well as a critical trip point in the thermal-zone. Signed-off-by: Miquel Raynal Acked-by: Eduardo Valentin Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index b9d9f31e3ba1..4d6e4a097f72 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -28,12 +28,19 @@ */ thermal-zones { CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) { - polling-delay-passive = <1000>; - polling-delay = <1000>; + polling-delay-passive = <0>; /* Interrupt driven */ + polling-delay = <0>; /* Interrupt driven */ thermal-sensors = <&CP110_LABEL(thermal) 0>; - trips { }; + trips { + CP110_LABEL(crit): crit { + temperature = <100000>; /* mC degrees */ + hysteresis = <2000>; /* mC degrees */ + type = "critical"; + }; + }; + cooling-maps { }; }; }; @@ -259,6 +266,8 @@ CP110_LABEL(thermal): thermal-sensor@70 { compatible = "marvell,armada-cp110-thermal"; reg = <0x70 0x10>; + interrupts-extended = + <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>; #thermal-sensor-cells = <1>; }; }; From d68def52498ebaca071da2b9fb3222f46262d89e Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 8 Jan 2019 17:31:23 +0100 Subject: [PATCH 353/506] arm64: dts: marvell: armada-37xx: fix SATA node scope Fix the SATA IP memory area which is only 0x178 bytes long (from Marvell A3700 specification). Actually, starting from the offset 0xe0178, there is an area dedicated to the COMPHY driver. Suggested-by: Grzegorz Jaszczyk Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index e05594ea15fb..6f5058a4f149 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -368,7 +368,7 @@ sata: sata@e0000 { compatible = "marvell,armada-3700-ahci"; - reg = <0xe0000 0x2000>; + reg = <0xe0000 0x178>; interrupts = ; status = "disabled"; }; From 02967b85b3ea0c09b8276f1a84933768409e34cc Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 4 Dec 2018 20:28:30 +0100 Subject: [PATCH 354/506] arm64: dts: marvell: armada-37xx: declare SATA clock The SATA IP get its clock from the north-bridge. Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 6f5058a4f149..e832ea597a16 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -370,6 +370,7 @@ compatible = "marvell,armada-3700-ahci"; reg = <0xe0000 0x178>; interrupts = ; + clocks = <&nb_periph_clk 1>; status = "disabled"; }; From b3ad58bcad7ea384a6efaf60df3a763a0ff41c40 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 29 Jan 2019 10:36:33 +0100 Subject: [PATCH 355/506] arm64: dts: marvell: armada-37xx: fix USB2 memory region The specification splits the USB2 memory region into three sections: 1/ 0xD005E000-0xD005EFFF: USB2 Host Controller Registers 2/ 0xD005F000-0xD005F7FF: USB2 UTMI PHY Registers 3/ 0xD005F800-0xD005FFFF: USB2 Host Miscellaneous Registers Section 1/ belongs to the USB2 node but section 2/ belongs to the UTMI PHY node. Section 3/ can be accessed by both the USB controller and the PHY because of the miscaellaneous nature of the registers inside so a specific node will be created to cover the area and a handle to it will be added in both the USB controller and the PHY node. Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index e832ea597a16..27f780bae6ea 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -312,7 +312,7 @@ usb2: usb@5e000 { compatible = "marvell,armada-3700-ehci"; - reg = <0x5e000 0x2000>; + reg = <0x5e000 0x1000>; interrupts = ; status = "disabled"; }; From 05d168a56fae8ff50432d5dfe6e7423b989455a8 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 29 Jan 2019 10:36:34 +0100 Subject: [PATCH 356/506] arm64: dts: marvell: armada-37xx: declare USB2 UTMI PHYs On Marvell Armada 3700 SoCs there are two USB2 UTMI PHYs. They are both very similar but only one has OTG/charging capabilities. Because there are USB host registers and PHY registers mixed in a single area, a system controller is also created and referenced from both the USB host node and the PHY node. Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 28 ++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 27f780bae6ea..48f85dc1c0a1 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -305,18 +305,46 @@ compatible = "marvell,armada3700-xhci", "generic-xhci"; reg = <0x58000 0x4000>; + marvell,usb-misc-reg = <&usb32_syscon>; interrupts = ; clocks = <&sb_periph_clk 12>; status = "disabled"; }; + usb2_utmi_otg_phy: phy@5d000 { + compatible = "marvell,a3700-utmi-otg-phy"; + reg = <0x5d000 0x800>; + marvell,usb-misc-reg = <&usb32_syscon>; + #phy-cells = <0>; + }; + + usb32_syscon: system-controller@5d800 { + compatible = "marvell,armada-3700-usb2-host-device-misc", + "syscon"; + reg = <0x5d800 0x800>; + }; + usb2: usb@5e000 { compatible = "marvell,armada-3700-ehci"; reg = <0x5e000 0x1000>; + marvell,usb-misc-reg = <&usb2_syscon>; interrupts = ; status = "disabled"; }; + usb2_utmi_host_phy: phy@5f000 { + compatible = "marvell,a3700-utmi-host-phy"; + reg = <0x5f000 0x800>; + marvell,usb-misc-reg = <&usb2_syscon>; + #phy-cells = <0>; + }; + + usb2_syscon: system-controller@5f800 { + compatible = "marvell,armada-3700-usb2-host-misc", + "syscon"; + reg = <0x5f800 0x800>; + }; + xor@60900 { compatible = "marvell,armada-3700-xor"; reg = <0x60900 0x100>, From a5470af981a0cc14a650af8da5186668971a4fc8 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 8 Jan 2019 17:24:39 +0100 Subject: [PATCH 357/506] arm64: dts: marvell: armada-37xx: declare PCIe reset pin One pin can be muxed as PCIe endpoint card reset. Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 48f85dc1c0a1..b278b64b73e3 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -276,6 +276,15 @@ function = "sdio"; }; + pcie_reset_pins: pcie-reset-pins { + groups = "pcie1"; + function = "pcie"; + }; + + pcie_clkreq_pins: pcie-clkreq-pins { + groups = "pcie1_clkreq"; + function = "pcie"; + }; }; eth0: ethernet@30000 { From c54932d42a4e39b9d68bba4e766ccb7a95ff7746 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 8 Jan 2019 17:24:40 +0100 Subject: [PATCH 358/506] arm64: dts: marvell: armada-3720-espressobin: declare PCIe warm reset pin Ensure the PCIe endpoint card reset that is toggled by the PCIe controller itself is muxed correctly on the EspressoBin. Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index 846003bb480c..18938d133ae3 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -46,6 +46,8 @@ /* J9 */ &pcie0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; }; /* J6 */ From a24270afa7f7ba800567a03ea9d34f500738e4c8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 Feb 2019 23:00:40 +0800 Subject: [PATCH 359/506] arm64: dts: allwinner: a64: Enable PMIC power supplies on various boards On these A64 devices, the DC input jacks are wired to the ACIN pins of the PMIC, which is represented by the AC power supply. With the exception of the Nanopi A64, all devices include LiPo batteries or have connectors for them, which are represented by the battery power supply. Enable these power supplies in the device tree. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 8 ++++++++ arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 4 ++++ arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts | 8 ++++++++ arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 8 ++++++++ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++ 5 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 9d0afd7d50ec..7793ebb5d2b8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -222,6 +222,14 @@ #include "axp803.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { /* * This regulator also drives the PE pingroup GPIOs, diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts index 31884dbc8838..f4e78531f639 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts @@ -186,6 +186,10 @@ #include "axp803.dtsi" +&ac_power_supply { + status = "okay"; +}; + ®_aldo2 { regulator-always-on; regulator-min-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts index f7a4bccaa5d4..01a9a52edae4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts @@ -177,6 +177,14 @@ #include "axp803.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <2800000>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts index b0c64f75792c..281bf9fe5ca2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts @@ -193,6 +193,14 @@ #include "axp803.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index 216f2f5db5ef..c0b9cc7a6b3a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -169,6 +169,14 @@ #include "axp803.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo2 { regulator-always-on; regulator-min-microvolt = <1800000>; From 0d15a7397ae7e6b03c7024e393051b79b215fed0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 Feb 2019 23:42:25 +0800 Subject: [PATCH 360/506] arm64: dts: allwinner: h5: libretech-all-h3-cc: Mark eMMC HS-DDR 3.3V capable The Libre Computer ALL-H3-CC H5 is one of the few boards that can have its eMMC run at HS-DDR speed mode. Mark it as such. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- .../boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts index 95e113ce8699..d68bdfea2271 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts @@ -12,3 +12,7 @@ model = "Libre Computer Board ALL-H3-CC H5"; compatible = "libretech,all-h3-cc-h5", "allwinner,sun50i-h5"; }; + +&mmc2 { + mmc-ddr-3_3v; +}; From de45b787dab563d4d62b0457e89525be945dae96 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Sun, 16 Aug 2015 08:13:25 +0200 Subject: [PATCH 361/506] ARM: tegra: add "jedec,spi-nor" flash compatible binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Starting with commit 8947e396a829 ("Documentation: dt: mtd: replace "nor-jedec" binding with "jedec, spi-nor"") we have "jedec,spi-nor" binding indicating support for JEDEC identification. Use it for all flashes that are supposed to support READ ID op according to the datasheets. Signed-off-by: Rafał Miłecki Acked-by: Brian Norris Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +- arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +- arch/arm/boot/dts/tegra124-venice2.dts | 2 +- arch/arm/boot/dts/tegra20-trimslice.dts | 2 +- arch/arm/boot/dts/tegra30-beaver.dts | 2 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 1788556b4977..97a5c3504bbe 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1087,7 +1087,7 @@ status = "okay"; spi-max-frequency = <25000000>; spi-flash@0 { - compatible = "winbond,w25q32dw"; + compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 9151b3ebb839..33bbb1c5285d 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1656,7 +1656,7 @@ status = "okay"; spi-max-frequency = <25000000>; spi-flash@0 { - compatible = "winbond,w25q32dw"; + compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; }; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index d5f11d6d987e..4dd4d13aa8f5 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -355,7 +355,7 @@ spi-max-frequency = <25000000>; flash@0 { - compatible = "winbond,w25q32dw"; + compatible = "winbond,w25q32dw", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 82d139648ef1..4882b61fb680 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -879,7 +879,7 @@ status = "okay"; spi-max-frequency = <25000000>; spi-flash@0 { - compatible = "winbond,w25q32dw"; + compatible = "winbond,w25q32dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; }; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 9eb26dc15f6b..3e5ac096d85e 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -287,7 +287,7 @@ status = "okay"; spi-max-frequency = <48000000>; spi-flash@0 { - compatible = "winbond,w25q80bl"; + compatible = "winbond,w25q80bl", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <48000000>; }; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index b0d40ac8ac6e..a3b0f3555cd2 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1886,7 +1886,7 @@ status = "okay"; spi-max-frequency = <25000000>; spi-flash@1 { - compatible = "winbond,w25q32"; + compatible = "winbond,w25q32", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <20000000>; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index fb9222b479d2..7ce61edd52f5 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -360,7 +360,7 @@ status = "okay"; spi-max-frequency = <25000000>; spi-flash@1 { - compatible = "winbond,w25q32"; + compatible = "winbond,w25q32", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <20000000>; }; From 93caec0042659bf17ec217b09857bd5eaeca6804 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Fri, 4 Jan 2019 11:06:43 +0800 Subject: [PATCH 362/506] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Add new properties to configure the DFLL PWM regulator support. Cc: devicetree@vger.kernel.org Signed-off-by: Peter De Schrijver Signed-off-by: Joseph Lo Acked-by: Jon Hunter Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/clock/nvidia,tegra124-dfll.txt | 79 ++++++++++++++++++- 1 file changed, 77 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index dff236f524a7..5558bb5fcf2c 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -8,7 +8,6 @@ the fast CPU cluster. It consists of a free-running voltage controlled oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop control module that will automatically adjust the VDD_CPU voltage by communicating with an off-chip PMIC either via an I2C bus or via PWM signals. -Currently only the I2C mode is supported by these bindings. Required properties: - compatible : should be "nvidia,tegra124-dfll" @@ -45,10 +44,31 @@ Required properties for the control loop parameters: Optional properties for the control loop parameters: - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM. +Optional properties for mode selection: +- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C. + Required properties for I2C mode: - nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode. -Example: +Required properties for PWM mode: +- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds. +- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM + control is disabled and the PWM output is tristated. Note that this voltage is + configured in hardware, typically via a resistor divider. +- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control + is enabled and PWM output is low. Hence, this is the minimum output voltage + that the regulator supports when PWM control is enabled. +- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts + corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th + duty cycle would be: nvidia,pwm-min-microvolts + + nvidia,pwm-voltage-step-microvolts * 2. +- pinctrl-0: I/O pad configuration when PWM control is enabled. +- pinctrl-1: I/O pad configuration when PWM control is disabled. +- pinctrl-names: must include the following entries: + - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled. + - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled. + +Example for I2C: clock@70110000 { compatible = "nvidia,tegra124-dfll"; @@ -76,3 +96,58 @@ clock@70110000 { nvidia,i2c-fs-rate = <400000>; }; + +Example for PWM: + +clock@70110000 { + compatible = "nvidia,tegra124-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, + <&tegra_car TEGRA210_CLK_DFLL_REF>, + <&tegra_car TEGRA124_CLK_I2C5>;; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + + nvidia,sample-rate = <25000>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + + nvidia,pwm-min-microvolts = <708000>; /* 708mV */ + nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ + nvidia,pwm-to-pmic; + nvidia,pwm-tristate-microvolts = <1000000>; + nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */ + + pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; + pinctrl-0 = <&dvfs_pwm_active_state>; + pinctrl-1 = <&dvfs_pwm_inactive_state>; +}; + +/* pinmux nodes added for completeness. Binding doc can be found in: + * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt + */ + +pinmux: pinmux@700008d4 { + dvfs_pwm_active_state: dvfs_pwm_active { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; + dvfs_pwm_inactive_state: dvfs_pwm_inactive { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; +}; From 7e9d10985856dcbcc8f56f97cb103eb3349b3f12 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 11:06:44 +0800 Subject: [PATCH 363/506] dt-bindings: clock: tegra124-dfll: add Tegra210 support Add Tegra210 support for DFLL clock. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter Acked-by: Stephen Boyd Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index 5558bb5fcf2c..958e0ad78c52 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -10,7 +10,9 @@ control module that will automatically adjust the VDD_CPU voltage by communicating with an off-chip PMIC either via an I2C bus or via PWM signals. Required properties: -- compatible : should be "nvidia,tegra124-dfll" +- compatible : should be one of: + - "nvidia,tegra124-dfll": for Tegra124 + - "nvidia,tegra210-dfll": for Tegra210 - reg : Defines the following set of registers, in the order listed: - registers for the DFLL control logic. - registers for the I2C output logic. From 73688f7d535bc3f5b0af2e3fd082a60daa2171be Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 11:06:45 +0800 Subject: [PATCH 364/506] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties The Tegra124 cpufreq driver works only with DFLL clock, which is a hardware-based frequency/voltage controller. The driver doesn't need to control the regulator itself. Hence remove that. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt index b1669fbfb740..031545a29caf 100644 --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt @@ -13,7 +13,6 @@ Required properties: - pll_x: Fast PLL clocksource. - pll_p: Auxiliary PLL used during fast PLL rate changes. - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. -- vdd-cpu-supply: Regulator for CPU voltage Optional properties: - clock-latency: Specify the possible maximum transition latency for clock, @@ -37,7 +36,6 @@ cpus { <&dfll>; clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; - vdd-cpu-supply: <&vdd_cpu>; }; <...> From c79a3ccb191809c356044564859c275fba8e5b0f Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 11:06:46 +0800 Subject: [PATCH 365/506] dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required properties The cpu_lp clock property is only needed when the CPUfreq driver supports CPU cluster switching. But it was not a design for this driver and it didn't handle that as well. So removing this property. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt index 031545a29caf..03196d5ea515 100644 --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt @@ -9,7 +9,6 @@ Required properties: See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - cpu_g: Clock mux for the fast CPU cluster. - - cpu_lp: Clock mux for the low-power CPU cluster. - pll_x: Fast PLL clocksource. - pll_p: Auxiliary PLL used during fast PLL rate changes. - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. @@ -30,11 +29,10 @@ cpus { reg = <0>; clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, - <&tegra_car TEGRA124_CLK_CCLK_LP>, <&tegra_car TEGRA124_CLK_PLL_X>, <&tegra_car TEGRA124_CLK_PLL_P>, <&dfll>; - clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; }; From e4f045ef38e61ba37aa4afc916fce4fc1b37aa19 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Thu, 24 Jan 2019 13:45:08 +0100 Subject: [PATCH 366/506] arm64: dts: msm8916: remove bogus argument to the cpu clock The apcs node has #clock-cells = <0>, which means that those who references it should specify 0 arguments. The apcs reference in the cpu node incorrectly specifies an argument, remove this bogus argument. Fixes: 65afdf458360 ("arm64: dts: qcom: msm8916: Add CPU frequency scaling support") Signed-off-by: Niklas Cassel Reviewed-by: Bjorn Andersson Reviewed-by: Amit Kucheria Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index c5348c3da5a2..60afbf1bab8f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -111,7 +111,7 @@ next-level-cache = <&L2_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SPC>; - clocks = <&apcs 0>; + clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; }; @@ -123,7 +123,7 @@ next-level-cache = <&L2_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SPC>; - clocks = <&apcs 0>; + clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; }; @@ -135,7 +135,7 @@ next-level-cache = <&L2_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SPC>; - clocks = <&apcs 0>; + clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; }; @@ -147,7 +147,7 @@ next-level-cache = <&L2_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SPC>; - clocks = <&apcs 0>; + clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; }; From 97131f85c08e024df49480ed499aae8fb754067f Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Thu, 24 Jan 2019 14:00:47 +0100 Subject: [PATCH 367/506] ARM: dts: qcom: ipq4019: Fix MSI IRQ type The databook clearly states that the MSI IRQ (msi_ctrl_int) is a level triggered interrupt. The msi_ctrl_int will be high for as long as any MSI status bit is set, thus the IRQ type should be set to IRQ_TYPE_LEVEL_HIGH, causing the IRQ handler to keep getting called, as long as any MSI status bit is set. A git grep shows that ipq4019 is the only SoC using snps,dw-pcie that has configured this IRQ incorrectly. Not having the correct IRQ type defined will cause us to lose interrupts, which in turn causes timeouts in the PCIe endpoint drivers. Signed-off-by: Niklas Cassel Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 19635f91e2c4..48b3cb474ba0 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -398,7 +398,7 @@ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000 0x82000000 0 0x40300000 0x40300000 0 0x400000>; - interrupts = ; + interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; From c47fc19887ce7f7797bd78727ba4ff55130876e5 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Wed, 6 Feb 2019 16:04:49 +0530 Subject: [PATCH 368/506] arm64: dts: sdm845: wireup the thermal trip points to cpufreq Since all cpus in the big and little clusters, respectively, are in the same frequency domain, use all of them for mitigation in the cooling-map. We end up with two cooling devices - one each for the big and little clusters. Signed-off-by: Amit Kucheria Acked-by: Eduardo Valentin Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 242 ++++++++++++++++++++++++--- 1 file changed, 218 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2194794fe84d..01a80ada653b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -17,6 +17,8 @@ #include #include #include +#include +#include / { interrupt-parent = <&intc>; @@ -119,6 +121,7 @@ reg = <0x0 0x0>; enable-method = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -135,6 +138,7 @@ reg = <0x0 0x100>; enable-method = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; next-level-cache = <&L2_100>; L2_100: l2-cache { compatible = "cache"; @@ -148,6 +152,7 @@ reg = <0x0 0x200>; enable-method = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; next-level-cache = <&L2_200>; L2_200: l2-cache { compatible = "cache"; @@ -161,6 +166,7 @@ reg = <0x0 0x300>; enable-method = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; next-level-cache = <&L2_300>; L2_300: l2-cache { compatible = "cache"; @@ -174,6 +180,7 @@ reg = <0x0 0x400>; enable-method = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; next-level-cache = <&L2_400>; L2_400: l2-cache { compatible = "cache"; @@ -187,6 +194,7 @@ reg = <0x0 0x500>; enable-method = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; next-level-cache = <&L2_500>; L2_500: l2-cache { compatible = "cache"; @@ -200,6 +208,7 @@ reg = <0x0 0x600>; enable-method = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; next-level-cache = <&L2_600>; L2_600: l2-cache { compatible = "cache"; @@ -213,6 +222,7 @@ reg = <0x0 0x700>; enable-method = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; next-level-cache = <&L2_700>; L2_700: l2-cache { compatible = "cache"; @@ -2250,18 +2260,41 @@ thermal-sensors = <&tsens0 1>; trips { - cpu_alert0: trip0 { - temperature = <75000>; + cpu0_alert0: trip-point@0 { + temperature = <90000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit0: trip1 { + cpu0_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu0_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { @@ -2271,18 +2304,41 @@ thermal-sensors = <&tsens0 2>; trips { - cpu_alert1: trip0 { - temperature = <75000>; + cpu1_alert0: trip-point@0 { + temperature = <90000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit1: trip1 { + cpu1_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { @@ -2292,18 +2348,41 @@ thermal-sensors = <&tsens0 3>; trips { - cpu_alert2: trip0 { - temperature = <75000>; + cpu2_alert0: trip-point@0 { + temperature = <90000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit2: trip1 { + cpu2_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { @@ -2313,18 +2392,41 @@ thermal-sensors = <&tsens0 4>; trips { - cpu_alert3: trip0 { - temperature = <75000>; + cpu3_alert0: trip-point@0 { + temperature = <90000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit3: trip1 { + cpu3_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu4-thermal { @@ -2334,18 +2436,41 @@ thermal-sensors = <&tsens0 7>; trips { - cpu_alert4: trip0 { - temperature = <75000>; + cpu4_alert0: trip-point@0 { + temperature = <90000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit4: trip1 { + cpu4_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu4_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu4_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu5-thermal { @@ -2355,18 +2480,41 @@ thermal-sensors = <&tsens0 8>; trips { - cpu_alert5: trip0 { - temperature = <75000>; + cpu5_alert0: trip-point@0 { + temperature = <90000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit5: trip1 { + cpu5_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu5_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu5_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu6-thermal { @@ -2376,18 +2524,41 @@ thermal-sensors = <&tsens0 9>; trips { - cpu_alert6: trip0 { - temperature = <75000>; + cpu6_alert0: trip-point@0 { + temperature = <90000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit6: trip1 { + cpu6_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu6_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu6_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu7-thermal { @@ -2397,18 +2568,41 @@ thermal-sensors = <&tsens0 10>; trips { - cpu_alert7: trip0 { - temperature = <75000>; + cpu7_alert0: trip-point@0 { + temperature = <90000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit7: trip1 { + cpu7_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu7_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu7_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; }; From 55fae1d552f77600976b8b55142bfbeb2a24fc58 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 4 Feb 2019 16:54:52 -0800 Subject: [PATCH 369/506] arm64: dts: qcom: sdm845: Define IOMMU for sdhc 2 With apps_smmu initializing the SMMU we must specify iommus property for the sdhc controller. Fixes: 4429e57567bb ("arm64: dts: sdm845: Add node for arm,mmu-500") Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 01a80ada653b..ce69872d5a61 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1515,6 +1515,7 @@ clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface", "core"; + iommus = <&apps_smmu 0xa0 0xf>; status = "disabled"; }; From 9a8a9d1791f0b85681514bbdb7bc52f96dca8d6a Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 4 Feb 2019 16:56:08 -0800 Subject: [PATCH 370/506] arm64: dts: qcom: sdm845: Define iommus for USB controllers The USB controllers need to be associated with their respective IOMMU bank, so define this on the dwc3 nodes. Also add dma-ranges to the qcom-dwc3 nodes to make the bus' DMA mask propagate to the dwc3 controller instances. Fixes: 4429e57567bb ("arm64: dts: sdm845: Add node for arm,mmu-500") Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index ce69872d5a61..b4b946d2f9cd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1635,6 +1635,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; + dma-ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -1663,6 +1664,7 @@ compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; interrupts = ; + iommus = <&apps_smmu 0x740 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_ssphy>; @@ -1677,6 +1679,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; + dma-ranges; clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>, @@ -1705,6 +1708,7 @@ compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; interrupts = ; + iommus = <&apps_smmu 0x760 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; phys = <&usb_2_hsphy>, <&usb_2_ssphy>; From 503f5fed1c52f0c0e4c25f5d386c4e426285bffe Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 1 Feb 2019 14:37:32 +0100 Subject: [PATCH 371/506] arm64: dts: meson: fix g12a buses Fix apb, cbus, hiu and periph regions which are not aligned with the documentation and the information provided by Amlogic Fixes: 9c8c52f7cb4f ("arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support") Cc: Jianxin Pan Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 46 +++++++++++---------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 3b82a975c663..349c4e2df1b0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -78,20 +78,28 @@ #size-cells = <2>; ranges; - periphs: periphs@ff634000 { + apb: bus@ff600000 { compatible = "simple-bus"; - reg = <0x0 0xff634000 0x0 0x2000>; + reg = <0x0 0xff600000 0x0 0x200000>; #address-cells = <2>; #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; - }; + ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; - hiubus: bus@ff63c000 { - compatible = "simple-bus"; - reg = <0x0 0xff63c000 0x0 0x1c00>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; + periphs: bus@34400 { + compatible = "simple-bus"; + reg = <0x0 0x34400 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; + }; + + hiu: bus@3c000 { + compatible = "simple-bus"; + reg = <0x0 0x3c000 0x0 0x1400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; + }; }; aobus: bus@ff800000 { @@ -102,7 +110,8 @@ ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; uart_AO: serial@3000 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; reg = <0x0 0x3000 0x0 0x18>; interrupts = ; clocks = <&xtal>, <&xtal>, <&xtal>; @@ -111,7 +120,8 @@ }; uart_AO_B: serial@4000 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; reg = <0x0 0x4000 0x0 0x18>; interrupts = ; clocks = <&xtal>, <&xtal>, <&xtal>; @@ -135,18 +145,10 @@ cbus: bus@ffd00000 { compatible = "simple-bus"; - reg = <0x0 0xffd00000 0x0 0x25000>; + reg = <0x0 0xffd00000 0x0 0x100000>; #address-cells = <2>; #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; - }; - - apb: apb@ffe00000 { - compatible = "simple-bus"; - reg = <0x0 0xffe00000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; + ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; }; }; From b7f456ced7f0e251ba14d8a5a1dd307096bb5306 Mon Sep 17 00:00:00 2001 From: Erin Lo Date: Thu, 24 Jan 2019 16:07:16 +0800 Subject: [PATCH 372/506] dt-bindings: arm: Add bindings for Mediatek MT8183 SoC Platform This adds dt-binding documentation of cpu for Mediatek MT8183. Signed-off-by: Erin Lo Reviewed-by: Rob Herring Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index 8f260e5cfd16..f6d6ed383aa2 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -20,6 +20,7 @@ compatible: Must contain one of "mediatek,mt8127" "mediatek,mt8135" "mediatek,mt8173" + "mediatek,mt8183" Supported boards: @@ -77,3 +78,6 @@ Supported boards: - MTK mt8173 tablet EVB: Required root node properties: - compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; +- Evaluation board for MT8183: + Required root node properties: + - compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; From 705f95153bd466f8be71b5edc69b21331cf01db5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:32 +0800 Subject: [PATCH 373/506] ARM: dts: sun9i: a80-optimus: Add node for AXP809's unused dc1sw regulator The DC1SW output from the AXP809 is unused. Unused regulators should still be listed so as to be considered to be fully constrained. Fixes: aa4a27bc819e ("ARM: dts: sun9i: a80-optimus: Add AXP809 PMIC device node and regulators") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 58a199b0e494..1ee2792b3a27 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -213,6 +213,10 @@ regulator-name = "vdd-cpus-09-usbh"; }; + dc1sw { + /* unused */ + }; + reg_dcdc1: dcdc1 { regulator-always-on; regulator-min-microvolt = <3000000>; From 507b1784b4079d37f506eff94d93ac1788e0fc50 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:33 +0800 Subject: [PATCH 374/506] ARM: dts: sun9i: a80-optimus: Add GPIO pin-bank regulator supplies The A80 Optimus has the PMIC providing voltage to all the pin-bank supply rails from its various regulator outputs. All pin-banks that have supply rails are accounted for. PN pin-bank does not have a supply rail. Also remove any "regulator-always-on" properties from regulators that were only marked to provide pin-bank power. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 1ee2792b3a27..9c25176e69dc 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -172,10 +172,26 @@ clocks = <&ac100_rtc 0>; }; +&pio { + vcc-pa-supply = <®_ldo_io1>; + vcc-pb-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_eldo2>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_ldo_io0>; + vcc-ph-supply = <®_dcdc1>; +}; + &r_ir { status = "okay"; }; +&r_pio { + vcc-pl-supply = <®_dldo2>; + vcc-pm-supply = <®_eldo3>; +}; + &r_rsb { status = "okay"; @@ -264,7 +280,6 @@ }; reg_dldo2: dldo2 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pl"; @@ -283,14 +298,12 @@ }; reg_eldo3: eldo3 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pm-codec-io1"; }; reg_ldo_io0: ldo_io0 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pg"; From b3e1f4be1e4b3f762ba589abb5da1fc4b6faa98f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:34 +0800 Subject: [PATCH 375/506] ARM: dts: sun9i: cubieboard4: Add GPIO pin-bank regulator supplies The Cubieboard 4 has the PMIC providing voltage to all the pin-bank supply rails from its various regulator outputs. All pin-banks that have supply rails are accounted for. PN pin-bank does not have a supply rail. Also remove any "regulator-always-on" properties from regulators that were only marked to provide pin-bank power. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 23 ++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 85da85faf869..0daab9b374e6 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -183,10 +183,26 @@ clocks = <&ac100_rtc 0>; }; +&pio { + vcc-pa-supply = <®_ldo_io1>; + vcc-pb-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dc1sw>; + vcc-pe-supply = <®_eldo2>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_ldo_io0>; + vcc-ph-supply = <®_dcdc1>; +}; + &r_ir { status = "okay"; }; +&r_pio { + vcc-pl-supply = <®_dldo2>; + vcc-pm-supply = <®_eldo3>; +}; + &r_rsb { status = "okay"; @@ -217,6 +233,10 @@ /* unused */ }; + reg_dc1sw: dc1sw { + regulator-name = "vcc-pd"; + }; + reg_dc5ldo: dc5ldo { regulator-always-on; regulator-min-microvolt = <800000>; @@ -271,7 +291,6 @@ }; reg_dldo2: dldo2 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pl"; @@ -290,14 +309,12 @@ }; reg_eldo3: eldo3 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pm-codec-io1"; }; reg_ldo_io0: ldo_io0 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pg"; From e78adcfe48daf7b322c09aa19930b8051adf04c8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:35 +0800 Subject: [PATCH 376/506] ARM: dts: sun9i: Add GMAC clock node The A80 has the same DWMAC hardware as on earlier Allwinner SoCs. The accompanying GMAC clock register has been moved into the "System Control" area. Add a clock node for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index d9532fb1ef65..724ca3b850c8 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -183,6 +183,37 @@ clock-output-names = "osc32k"; }; + /* + * The following two are dummy clocks, placeholders + * used in the gmac_tx clock. The gmac driver will + * choose one parent depending on the PHY interface + * mode, using clk_set_rate auto-reparenting. + * + * The actual TX clock rate is not controlled by the + * gmac_tx clock. + */ + mii_phy_tx_clk: mii_phy_tx_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "mii_phy_tx"; + }; + + gmac_int_tx_clk: gmac_int_tx_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_int_tx"; + }; + + gmac_tx_clk: clk@800030 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-gmac-clk"; + reg = <0x00800030 0x4>; + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; + clock-output-names = "gmac_tx"; + }; + cpus_clk: clk@8001410 { compatible = "allwinner,sun9i-a80-cpus-clk"; reg = <0x08001410 0x4>; From 6fa39a5405db9a2e8621b49fd2d46fd585225853 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:36 +0800 Subject: [PATCH 377/506] ARM: dts: sun9i: Add A80 GMAC gigabit ethernet controller node The A80 has the same GMAC found on the A31 SoC. Add a device node, and an alias for it. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 724ca3b850c8..f0c7acf2d0a4 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -56,6 +56,10 @@ #size-cells = <2>; interrupt-parent = <&gic>; + aliases { + ethernet0 = &gmac; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -314,6 +318,23 @@ }; }; + gmac: ethernet@830000 { + compatible = "allwinner,sun7i-a20-gmac"; + reg = <0x00830000 0x1054>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>; + clock-names = "stmmaceth", "allwinner_gmac_tx"; + resets = <&ccu RST_BUS_GMAC>; + reset-names = "stmmaceth"; + snps,pbl = <2>; + snps,fixed-burst; + snps,force_sf_dma_mode; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ehci0: usb@a00000 { compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; reg = <0x00a00000 0x100>; From 72acaa1343ea2c5c401649e39c21ed83192f8cf3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:37 +0800 Subject: [PATCH 378/506] ARM: dts: sun9i: Add A80 GMAC RGMII pinmux setting The GMAC (gigabit ethernet controller) supports RGMII to connect to the ethernet PHY, for gigabit network speeds. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index f0c7acf2d0a4..6fb292e0b662 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -1000,6 +1000,19 @@ #size-cells = <0>; #gpio-cells = <3>; + gmac_rgmii_pins: gmac-rgmii-pins { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA4", "PA5", "PA7", "PA8", + "PA9", "PA10", "PA12", "PA13", + "PA15", "PA16", "PA17"; + allwinner,function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + drive-strength = <40>; + }; + i2c3_pins: i2c3-pins { pins = "PG10", "PG11"; function = "i2c3"; From bc9bd03a44f900ae30a1d0f425a2fd092444e335 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:38 +0800 Subject: [PATCH 379/506] ARM: dts: sun9i: a80-optimus: Enable GMAC The A80 Optimus has a Realtek RTL8211E ethernet PHY which uses RGMII to talk to the MAC. The PHY is powered by 2 regulators: cldo1 for the PHY's core logic and gpio1-ldo for I/O. The latter also powers the SoC side pins. As there is no binding to model a second regulator supply for the PHY, it is omitted. It is however properly modeled for the PIO. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 9c25176e69dc..864715ec3cb0 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -120,6 +120,19 @@ status = "okay"; }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_cldo1>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -391,6 +404,14 @@ */ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + /* + * The PHY requires 20ms after all voltages + * are applied until core logic is ready and + * 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC + * ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; regulator-name = "vcc-gmac-phy"; }; From 98048143b7f83ee3fc70f4522ff9b8fa11f8b0a5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 6 Feb 2019 11:32:39 +0800 Subject: [PATCH 380/506] ARM: dts: sun9i: cubieboard4: Enable GMAC The Cubieboard4 has a Realtek RTL8211E ethernet PHY which uses RGMII to talk to the MAC. The PHY is powered by 2 regulators: cldo1 for the PHY's core logic and gpio1-ldo for I/O. The latter also powers the SoC side pins. As there is no binding to model a second regulator supply for the PHY, it is omitted. It is however properly modeled for the PIO. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 0daab9b374e6..28c034928d67 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -133,6 +133,19 @@ status = "okay"; }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_cldo1>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; @@ -402,6 +415,14 @@ */ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + /* + * The PHY requires 20ms after all voltages + * are applied until core logic is ready and + * 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC + * ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; regulator-name = "vcc-gmac-phy"; }; From 185401e1dd1656f8a1dff42bb2e4863493fd51f0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 5 Feb 2019 23:00:39 +0800 Subject: [PATCH 381/506] ARM: dts: sun8i: a83t: Enable PMIC power supplies on various boards On the Bananapi M3 and Cubietruck Plus, the DC input jacks are wired to the ACIN pins, which is represented by the AC power supply. Both boards have connectors for LiPo batteries, which are represented by the battery power supply. The H8 Homlet is a set-top box design. The DC input jack is wired to the ACIN pins, but there are no battery connectors. Enable these power supplies in the device tree. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 4 ++++ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 8 ++++++++ arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 8 ++++++++ 3 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index 1c012a4def16..9c006fc18821 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -154,6 +154,10 @@ #include "axp81x.dtsi" +&ac_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts index 7d30d3e530fb..838be7b3715f 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -237,6 +237,14 @@ #include "axp81x.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index a5a9f5a0603e..fcbec3d7ccd7 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -247,6 +247,14 @@ #include "axp81x.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-always-on; regulator-min-microvolt = <1800000>; From dd93f84655777d690bbc4e9f65180fe5e0384734 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Tue, 29 Jan 2019 12:31:14 +0800 Subject: [PATCH 382/506] dt-bindings: arm: mediatek: remove unused "mediatek, mt7623a" As we fallback to use "mediatek,mt7623" for MT7623a, remove unused root node property "mediatek,mt7623a" in the document. Signed-off-by: Ryder Lee Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index f6d6ed383aa2..f96d74a5c43b 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -15,8 +15,7 @@ compatible: Must contain one of "mediatek,mt6795" "mediatek,mt6797" "mediatek,mt7622" - "mediatek,mt7623" which is referred to MT7623N SoC - "mediatek,mt7623a" + "mediatek,mt7623" "mediatek,mt8127" "mediatek,mt8135" "mediatek,mt8173" From 858a6c310f7761314164e3a49c05f25330595d92 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Tue, 29 Jan 2019 12:31:15 +0800 Subject: [PATCH 383/506] dt-bindings: arm: mediatek: add support for MT7622 BPI-R64 and MT7629 RFB Update binding document for MT7622 BPI-R64 and MT7629 reference board. Signed-off-by: Ryder Lee Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index f96d74a5c43b..56ac7896d6d8 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -16,6 +16,7 @@ compatible: Must contain one of "mediatek,mt6797" "mediatek,mt7622" "mediatek,mt7623" + "mediatek,mt7629" "mediatek,mt8127" "mediatek,mt8135" "mediatek,mt8173" @@ -57,6 +58,9 @@ Supported boards: - Reference board variant 1 for MT7622: Required root node properties: - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; +- Bananapi BPI-R64 for MT7622: + Required root node properties: + - compatible = "bananapi,bpi-r64", "mediatek,mt7622"; - Reference board for MT7623a with eMMC: Required root node properties: - compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623"; @@ -68,6 +72,9 @@ Supported boards: - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623"; - Bananapi BPI-R2 board: - compatible = "bananapi,bpi-r2", "mediatek,mt7623"; +- Reference board for MT7629: + Required root node properties: + - compatible = "mediatek,mt7629-rfb", "mediatek,mt7629"; - MTK mt8127 tablet moose EVB: Required root node properties: - compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; From dd80f10320c6d4d57c632ee1f3f9c40d3bad9855 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Tue, 29 Jan 2019 15:45:18 +0100 Subject: [PATCH 384/506] ARM: dts: omap3-gta04a5: Replace LXR reference with a local one MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's no need to use an external link when the file is already here. Signed-off-by: Jonathan Neuschäfer Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04a5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts index bd232b1b24cb..223b47ac596e 100644 --- a/arch/arm/boot/dts/omap3-gta04a5.dts +++ b/arch/arm/boot/dts/omap3-gta04a5.dts @@ -82,7 +82,7 @@ /* * for WL183x module see - * http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt + * Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt */ &wifi_pwrseq { From a3f9c8c78abd283d840d4b22d6e19059ae953d7a Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Thu, 31 Jan 2019 07:23:38 +0100 Subject: [PATCH 385/506] ARM: dts: gta04: add pinctrl settings for wkup domain There is one button and a notifier for incoming phone calls/text messages for which we should wakeup from suspend. Signed-off-by: Andreas Kemnade Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index e53d32691308..2dfa85e2f608 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -224,6 +224,15 @@ }; }; +&omap3_pmx_wkup { + gpio1_pins: pinmux_gpio1_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ + OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_clkout.gpio_10 */ + >; + }; +}; + &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = < @@ -636,6 +645,11 @@ status = "disabled"; }; +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; From 0db02b3bee2a8aa4a2dddff02cbbc578c53e5d2f Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Thu, 31 Jan 2019 19:06:39 +0100 Subject: [PATCH 386/506] ARM: dts: gta04: add ldo 3v3 regulator Required for completeness sake to be able to specify a regulator for devices having a non-optional regulator property. It corresponds to the "3V3" net in the schematics. Signed-off-by: Andreas Kemnade Reviewed-by: Johan Hovold Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 2dfa85e2f608..666dd0288b69 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -32,6 +32,14 @@ display1 = &tv0; }; + ldo_3v3: fixedregulator { + compatible = "regulator-fixed"; + regulator-name = "ldo_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + /* fixed 26MHz oscillator */ hfclk_26m: oscillator { #clock-cells = <0>; From 1f4f84e955342ebba3295f100693073a412c8f46 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Thu, 31 Jan 2019 19:06:40 +0100 Subject: [PATCH 387/506] ARM: dts: gta04: add gps support The GTA04 has a w2sg0004 or w2sg0084 gps chip. Not detectable which one is mounted so use the compatibility entry for w2sg0004 for all which will work for both. Signed-off-by: Andreas Kemnade Reviewed-by: Johan Hovold Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 666dd0288b69..843d8795118d 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -329,6 +329,12 @@ >; }; + gps_pins: pinmux_gps_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* gpio145 */ + >; + }; + hdq_pins: hdq_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */ @@ -666,6 +672,14 @@ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; + gnss: gnss { + compatible = "wi2wi,w2sg0004"; + pinctrl-names = "default"; + pinctrl-0 = <&gps_pins>; + sirf,onoff-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + lna-supply = <&vsim>; + vcc-supply = <&ldo_3v3>; + }; }; &uart3 { From 2ceed59366b1405914631fc389bd46172b48f95d Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 11:06:56 +0800 Subject: [PATCH 388/506] arm64: tegra: Add DFLL clock on Tegra210 Add essential DFLL clock properties for Tegra210. Signed-off-by: Joseph Lo Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 61d2dbe4ce53..09f4d48fac9c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include #include @@ -1131,6 +1132,24 @@ #nvidia,mipi-calibrate-cells = <1>; }; + dfll: clock@70110000 { + compatible = "nvidia,tegra210-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, + <&tegra_car TEGRA210_CLK_DFLL_REF>, + <&tegra_car TEGRA210_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + status = "disabled"; + }; + aconnect@702c0000 { compatible = "nvidia,tegra210-aconnect"; clocks = <&tegra_car TEGRA210_CLK_APE>, From 43b9b402f491cb488eb1d1b2608718585cecfd72 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 11:06:57 +0800 Subject: [PATCH 389/506] arm64: tegra: Add CPU clocks on Tegra210 Add CPU clocks for Tegra210. Signed-off-by: Joseph Lo Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 09f4d48fac9c..b5858b5ea052 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1304,6 +1304,12 @@ device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0>; + clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, + <&tegra_car TEGRA210_CLK_PLL_X>, + <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, + <&dfll>; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; + clock-latency = <300000>; }; cpu@1 { From a5e98b0b371c11bb49be0b661a03a04a5c3b1f44 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 11:06:58 +0800 Subject: [PATCH 390/506] arm64: tegra: Add pinmux for PWM-based DFLL support on P2597 Add pinmux for PWM-based DFLL support. Signed-off-by: Joseph Lo Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index f4bb48d87df7..8780b5b3d2b9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1278,6 +1278,20 @@ nvidia,open-drain = ; }; }; + + dvfs_pwm_active_state: dvfs_pwm_active { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; + + dvfs_pwm_inactive_state: dvfs_pwm_inactive { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; }; pwm@7000a000 { From a1304d352cca26dc80b70c869848d3ea50f6a54f Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 11:06:59 +0800 Subject: [PATCH 391/506] arm64: tegra: Enable DFLL clock on Jetson TX1 Enable DFLL clock for Jetson TX1 platform. Signed-off-by: Joseph Lo Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra210-p2371-2180.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 37e3c46e753f..9fad0d27278e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -78,4 +78,25 @@ }; }; }; + + clock@70110000 { + status = "okay"; + + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,sample-rate = <25000>; + + nvidia,pwm-min-microvolts = <708000>; + nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ + nvidia,pwm-to-pmic; + nvidia,pwm-tristate-microvolts = <1000000>; + nvidia,pwm-voltage-step-microvolts = <19200>; + + pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; + pinctrl-0 = <&dvfs_pwm_active_state>; + pinctrl-1 = <&dvfs_pwm_inactive_state>; + }; }; From f9c8bcc00290e7b46188fc9e87aaec0ebeba0286 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 11:07:00 +0800 Subject: [PATCH 392/506] arm64: tegra: Add CPU power rail regulator on Smaug Add CPU power rail regulator for Smaug board. Signed-off-by: Joseph Lo Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index ed04526f6252..9a8f6b021323 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1340,6 +1340,25 @@ status = "okay"; clock-frequency = <1000000>; + max77621_cpu: max77621@1b { + compatible = "maxim,max77621"; + reg = <0x1b>; + interrupt-parent = <&gpio>; + interrupts = ; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1231250>; + regulator-name = "PPVAR_CPU"; + regulator-ramp-delay = <12500>; + maxim,dvs-default-state = <1>; + maxim,enable-active-discharge; + maxim,enable-bias-control; + maxim,enable-etr; + maxim,enable-gpio = <&max77620 5 0>; + maxim,externally-enable; + }; + max77620: max77620@3c { compatible = "maxim,max77620"; reg = <0x3c>; From d4eb7653a8dcbcff45ace820314d4e8044fe8d38 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 4 Jan 2019 11:07:01 +0800 Subject: [PATCH 393/506] arm64: tegra: Enable DFLL clock on Smaug Enable DFLL clock for Smaug board. Signed-off-by: Joseph Lo Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 9a8f6b021323..a4b8f668a6d4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1698,6 +1698,18 @@ status = "okay"; }; + clock@70110000 { + status = "okay"; + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,i2c-fs-rate = <400000>; + nvidia,sample-rate = <12500>; + vdd-cpu-supply = <&max77621_cpu>; + }; + aconnect@702c0000 { status = "okay"; From a38570c22e9d06bd54f5f439e33caa1589f5925d Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 28 Nov 2018 10:54:19 +0100 Subject: [PATCH 394/506] arm64: tegra: Add nodes for TCU on Tegra194 Add nodes required for communication through the Tegra Combined UART. This includes the AON HSP instance, addition of shared interrupts for the TOP0 HSP instance, and finally the TCU node itself. Also mark the HSP instances as compatible to tegra194-hsp, as the hardware is not identical but is compatible to tegra186-hsp. Signed-off-by: Mikko Perttunen Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 ++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 6dfa1ca0b851..607b5bde94f0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -367,10 +367,35 @@ }; hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra186-hsp"; + compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; reg = <0x03c00000 0xa0000>; - interrupts = ; - interrupt-names = "doorbell"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "doorbell", "shared0", "shared1", "shared2", + "shared3", "shared4", "shared5", "shared6", + "shared7"; + #mbox-cells = <2>; + }; + + hsp_aon: hsp@c150000 { + compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; + reg = <0x0c150000 0xa0000>; + interrupts = , + , + , + ; + /* + * Shared interrupt 0 is routed only to AON/SPE, so + * we only have 4 shared interrupts for the CCPLEX. + */ + interrupt-names = "shared1", "shared2", "shared3", "shared4"; #mbox-cells = <2>; }; @@ -933,6 +958,13 @@ method = "smc"; }; + tcu: tcu { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; + mbox-names = "rx", "tx"; + }; + thermal-zones { cpu { thermal-sensors = <&{/bpmp/thermal} From 6ab6a4d22030c11df3278e9807d17f2e37c6f7fe Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 28 Nov 2018 10:54:20 +0100 Subject: [PATCH 395/506] arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888 The Tegra Combined UART is the proper primary serial port on P2888, so use it. Signed-off-by: Mikko Perttunen Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 22a1c267aed9..246c1ebbd055 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -10,7 +10,7 @@ aliases { sdhci0 = "/cbb/sdhci@3460000"; sdhci1 = "/cbb/sdhci@3400000"; - serial0 = &uartb; + serial0 = &tcu; i2c0 = "/bpmp/i2c"; i2c1 = "/cbb/i2c@3160000"; i2c2 = "/cbb/i2c@c240000"; From 4e0f122991943bcaf88149dbe48fb6c3c42f006f Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Thu, 10 Jan 2019 14:46:02 -0800 Subject: [PATCH 396/506] arm64: tegra: Add SDMMC auto-calibration settings Add SDMMC initial pad offsets used by auto calibration process. Add SDMMC fixed drive strengths for Tegra210, Tegra186 and Tegra194 which are used when calibration timeouts. Fixed drive strengths are based on Pre SI Analysis of the pads. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 34 ++++++++++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 57 +++++++++++++++++++++++- 3 files changed, 91 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 22815db4a3ed..169aee59ceac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -315,6 +315,8 @@ nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; nvidia,default-tap = <0x5>; nvidia,default-trim = <0x9>; nvidia,dqs-trim = <63>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 607b5bde94f0..99eaf9bc3d43 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -303,6 +303,17 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA194_RESET_SDMMC1>; reset-names = "sdhci"; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = + <0x07>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = + <0x07>; + nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; + nvidia,pad-autocal-pull-down-offset-1v8-timeout = + <0x07>; + nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; + nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; + nvidia,default-tap = <0x9>; + nvidia,default-trim = <0x5>; status = "disabled"; }; @@ -314,6 +325,18 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA194_RESET_SDMMC3>; reset-names = "sdhci"; + nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; + nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = + <0x07>; + nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; + nvidia,pad-autocal-pull-down-offset-1v8-timeout = + <0x07>; + nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; + nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; + nvidia,default-tap = <0x9>; + nvidia,default-trim = <0x5>; status = "disabled"; }; @@ -325,6 +348,17 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA194_RESET_SDMMC4>; reset-names = "sdhci"; + nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; + nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; + nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; + nvidia,pad-autocal-pull-down-offset-1v8-timeout = + <0x0a>; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = + <0x0a>; + nvidia,default-tap = <0x8>; + nvidia,default-trim = <0x14>; + nvidia,dqs-trim = <40>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index b5858b5ea052..ef2725f898c2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -477,6 +477,48 @@ compatible = "nvidia,tegra210-pinmux"; reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ <0x0 0x70003000 0x0 0x294>; /* Mux registers */ + sdmmc1_3v3_drv: sdmmc1-3v3-drv { + sdmmc1 { + nvidia,pins = "drive_sdmmc1"; + nvidia,pull-down-strength = <0x8>; + nvidia,pull-up-strength = <0x8>; + }; + }; + sdmmc1_1v8_drv: sdmmc1-1v8-drv { + sdmmc1 { + nvidia,pins = "drive_sdmmc1"; + nvidia,pull-down-strength = <0x4>; + nvidia,pull-up-strength = <0x3>; + }; + }; + sdmmc2_1v8_drv: sdmmc2-1v8-drv { + sdmmc2 { + nvidia,pins = "drive_sdmmc2"; + nvidia,pull-down-strength = <0x10>; + nvidia,pull-up-strength = <0x10>; + }; + }; + sdmmc3_3v3_drv: sdmmc3-3v3-drv { + sdmmc3 { + nvidia,pins = "drive_sdmmc3"; + nvidia,pull-down-strength = <0x8>; + nvidia,pull-up-strength = <0x8>; + }; + }; + sdmmc3_1v8_drv: sdmmc3-1v8-drv { + sdmmc3 { + nvidia,pins = "drive_sdmmc3"; + nvidia,pull-down-strength = <0x4>; + nvidia,pull-up-strength = <0x3>; + }; + }; + sdmmc4_1v8_drv: sdmmc4-1v8-drv { + sdmmc4 { + nvidia,pins = "drive_sdmmc4"; + nvidia,pull-down-strength = <0x10>; + nvidia,pull-up-strength = <0x10>; + }; + }; }; /* @@ -1051,9 +1093,12 @@ clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", + "sdmmc-3v3-drv", "sdmmc-1v8-drv"; pinctrl-0 = <&sdmmc1_3v3>; pinctrl-1 = <&sdmmc1_1v8>; + pinctrl-2 = <&sdmmc1_3v3_drv>; + pinctrl-3 = <&sdmmc1_1v8_drv>; nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; @@ -1076,6 +1121,8 @@ clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; + pinctrl-names = "sdmmc-1v8-drv"; + pinctrl-0 = <&sdmmc2_1v8_drv>; nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; nvidia,default-tap = <0x8>; @@ -1091,9 +1138,12 @@ clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", + "sdmmc-3v3-drv", "sdmmc-1v8-drv"; pinctrl-0 = <&sdmmc3_3v3>; pinctrl-1 = <&sdmmc3_1v8>; + pinctrl-2 = <&sdmmc3_3v3_drv>; + pinctrl-3 = <&sdmmc3_1v8_drv>; nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; @@ -1111,6 +1161,9 @@ clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; + pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; + pinctrl-0 = <&sdmmc4_1v8_drv>; + pinctrl-1 = <&sdmmc4_1v8_drv>; nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; nvidia,default-tap = <0x8>; From dfd3cb6feb73a38777a18fe5b0a91670978f8b4b Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Wed, 23 Jan 2019 11:30:52 -0800 Subject: [PATCH 397/506] arm64: tegra: Add CQE Support for SDMMC4 Add CQE Support for Tegra186 and Tegra194 SDMMC4 controller Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 169aee59ceac..882a2a906eb5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -321,6 +321,7 @@ nvidia,default-trim = <0x9>; nvidia,dqs-trim = <63>; mmc-hs400-1_8v; + supports-cqe; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 99eaf9bc3d43..ae9e593e149e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -359,6 +359,7 @@ nvidia,default-tap = <0x8>; nvidia,default-trim = <0x14>; nvidia,dqs-trim = <40>; + supports-cqe; status = "disabled"; }; From 351648d0cc6d32b38f3e08c143bf637dc934997c Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Thu, 13 Dec 2018 13:14:30 -0800 Subject: [PATCH 398/506] arm64: tegra: Support 200 MHz for SDMMC on Tegra194 Change the SDMMC clock source to support a maximum frequency of 200 MHz on Tegra194. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index ae9e593e149e..560c1b695825 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -346,6 +346,10 @@ interrupts = ; clocks = <&bpmp TEGRA194_CLK_SDMMC4>; clock-names = "sdhci"; + assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, + <&bpmp TEGRA194_CLK_PLLC4>; + assigned-clock-parents = + <&bpmp TEGRA194_CLK_PLLC4>; resets = <&bpmp TEGRA194_RESET_SDMMC4>; reset-names = "sdhci"; nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; From 140723b9816655187ffeff64052a820903eef953 Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Tue, 18 Dec 2018 14:37:04 -0800 Subject: [PATCH 399/506] arm64: tegra: Update compatible for Tegra210 I2C Update I2C device node compatible string to be appropriate. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index ef2725f898c2..6574396d2257 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -597,7 +597,7 @@ }; i2c@7000c000 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; reg = <0x0 0x7000c000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -612,7 +612,7 @@ }; i2c@7000c400 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; reg = <0x0 0x7000c400 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -627,7 +627,7 @@ }; i2c@7000c500 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; reg = <0x0 0x7000c500 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -642,7 +642,7 @@ }; i2c@7000c700 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; reg = <0x0 0x7000c700 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -660,7 +660,7 @@ }; i2c@7000d000 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; reg = <0x0 0x7000d000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -675,7 +675,7 @@ }; i2c@7000d100 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; reg = <0x0 0x7000d100 0x0 0x100>; interrupts = ; #address-cells = <1>; From 250a36c06f95caaeef0da218f87fd452766eefd6 Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Tue, 18 Dec 2018 14:40:56 -0800 Subject: [PATCH 400/506] arm64: tegra: Update compatible for Tegra186 I2C Update I2C Device node compatible string to be appropriate. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 882a2a906eb5..e96275689fca 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -136,7 +136,7 @@ }; gen1_i2c: i2c@3160000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; reg = <0x0 0x03160000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -149,7 +149,7 @@ }; cam_i2c: i2c@3180000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; reg = <0x0 0x03180000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -163,7 +163,7 @@ /* shares pads with dpaux1 */ dp_aux_ch1_i2c: i2c@3190000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; reg = <0x0 0x03190000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -177,7 +177,7 @@ /* controlled by BPMP, should not be enabled */ pwr_i2c: i2c@31a0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; reg = <0x0 0x031a0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -191,7 +191,7 @@ /* shares pads with dpaux0 */ dp_aux_ch0_i2c: i2c@31b0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; reg = <0x0 0x031b0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -204,7 +204,7 @@ }; gen7_i2c: i2c@31c0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; reg = <0x0 0x031c0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -217,7 +217,7 @@ }; gen9_i2c: i2c@31e0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; reg = <0x0 0x031e0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -378,7 +378,7 @@ }; gen2_i2c: i2c@c240000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; reg = <0x0 0x0c240000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -391,7 +391,7 @@ }; gen8_i2c: i2c@c250000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; reg = <0x0 0x0c250000 0x0 0x10000>; interrupts = ; #address-cells = <1>; From fea888bd3359c15b0e96328594e23aa8d7928635 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 18 Jan 2019 11:34:22 +0100 Subject: [PATCH 401/506] arm64: dts: meson: axg: add clk measure support Add the clock measure device to the axg SoC family Signed-off-by: Jerome Brunet Reviewed-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index f044473dc7d0..398b7ac1b107 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1610,6 +1610,11 @@ status = "disabled"; }; + clk_msr: clock-measure@18000 { + compatible = "amlogic,meson-axg-clk-measure"; + reg = <0x0 0x18000 0x0 0x10>; + }; + i2c3: i2c@1c000 { compatible = "amlogic,meson-axg-i2c"; reg = <0x0 0x1c000 0x0 0x20>; From 60d4fdb8f372f75e4108db4e51e5373f023b51b7 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 18 Jan 2019 11:34:23 +0100 Subject: [PATCH 402/506] arm64: dts: meson: g12a: add clk measure support Add the clock measure device to the g12a SoC family Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 349c4e2df1b0..3be649e4efa4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -149,6 +149,11 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; + + clk_msr: clock-measure@18000 { + compatible = "amlogic,meson-g12a-clk-measure"; + reg = <0x0 0x18000 0x0 0x10>; + }; }; }; From bc94e5f4c2d33a1ffe289a62c8b1b9fecabfba89 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Fri, 18 Jan 2019 16:00:15 -0800 Subject: [PATCH 403/506] arm64: dts: sdm845: Add clocks and iommus to WCN3990 WLAN node When commit 022bccb840b7 ("dts: arm64/sdm845: Add WCN3990 WLAN module device node") was posted upstream no clocks were specified. However, when the pack was picked into the Chrome OS kernel tree (allegedly directly from the mailing list post) it had clock properties. I presume that the clock should be there, so let's add it. Fixes: 022bccb840b7 ("dts: arm64/sdm845: Add WCN3990 WLAN module device node") Tested-by: Sibi Sankar Signed-off-by: Douglas Anderson [bjorn: Add also the required iommus property] Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b4b946d2f9cd..e4b69c74fe07 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2241,6 +2241,8 @@ reg = <0 0x18800000 0 0x800000>; reg-names = "membase"; memory-region = <&wlan_msa_mem>; + clock-names = "cxo_ref_clk_pin"; + clocks = <&rpmhcc RPMH_RF_CLK2>; interrupts = , , @@ -2254,6 +2256,7 @@ , , ; + iommus = <&apps_smmu 0x0040 0x1>; }; }; From 5f152018d340d90c185ced8ef6230b7044ea5540 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 22 Jan 2019 15:25:48 +0000 Subject: [PATCH 404/506] ARM: dts: r8a7744: Add DU support Add du node to r8a7744 SoC DT. Boards that want to enable the DU need to specify the output topology. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 8d25a0a0594a..83804aa042c6 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1645,8 +1645,14 @@ }; du: display@feb00000 { - reg = <0 0xfeb00000 0 0x40000>, - <0 0xfeb90000 0 0x1c>; + compatible = "renesas,du-r8a7744"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; + clock-names = "du.0", "du.1"; + status = "disabled"; ports { #address-cells = <1>; @@ -1663,7 +1669,6 @@ }; }; }; - /* placeholder */ }; prr: chipid@ff000044 { From 1feef0ac19a8376d36909af677b531b21bc92bb7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 22 Jan 2019 15:25:49 +0000 Subject: [PATCH 405/506] ARM: dts: r8a7744: Add LVDS support Add LVDS encoder node to r8a7744 SoC DT. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 83804aa042c6..fa74a262107b 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1666,6 +1666,33 @@ port@1 { reg = <1>; du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7744-lvds"; + reg = <0 0xfeb90000 0 0x1c>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { }; }; }; From e536d27e923c090e492b7e83e3f1267f7b74ebb7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Thu, 1 Nov 2018 00:31:25 +0100 Subject: [PATCH 406/506] arm64: dts: renesas: enable HS400 on R-Car Gen3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Successfully tested on H3 ES2.0 and M3-N ES1.0. Transfer rates where >160MB/s for H3 and >200MB/s for M3-N. Signed-off-by: Niklas Söderlund Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 1 + arch/arm64/boot/dts/renesas/ulcb.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index f66d990b92f1..a225c2457274 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -764,6 +764,7 @@ vqmmc-supply = <®_1p8v>; bus-width = <8>; mmc-hs200-1_8v; + mmc-hs400-1_8v; non-removable; fixed-emmc-driver-type = <1>; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index a3878fb3c3f1..e70e1bac2be4 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -463,6 +463,7 @@ vqmmc-supply = <®_1p8v>; bus-width = <8>; mmc-hs200-1_8v; + mmc-hs400-1_8v; non-removable; status = "okay"; }; From dd7188eb4ed128dccc16b1d7dc1d639ddbd8882a Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Tue, 15 Jan 2019 21:02:42 +0900 Subject: [PATCH 407/506] arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices This patch define OOP tables for all CPUs. This allows CPUFreq to function. Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko Tested-by: Simon Horman Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 786178cf1ffd..b42b9c760908 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -55,6 +55,27 @@ clock-frequency = <0>; }; + cluster1_opp: opp_table10 { + compatible = "operating-points-v2"; + opp-shared; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -66,6 +87,8 @@ power-domains = <&sysc R8A77990_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_1: cpu@1 { @@ -75,6 +98,8 @@ power-domains = <&sysc R8A77990_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; L2_CA53: cache-controller-0 { From 231d8908a66fa98f09553d31ad8cd5f382b29959 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 31 Jan 2019 11:34:10 +0000 Subject: [PATCH 408/506] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices This patch defines OOP tables for all CPUs, similarly to what done by Takeshi Kihara and Yoshihiro Kaneko for the R8A77990. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index f2e390f7f1d5..71ff43e3bb41 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -44,6 +44,27 @@ clock-frequency = <0>; }; + cluster1_opp: opp_table10 { + compatible = "operating-points-v2"; + opp-shared; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -55,6 +76,8 @@ power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_1: cpu@1 { @@ -64,6 +87,8 @@ power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; L2_CA53: cache-controller-0 { From fa930bb65cf930c48efc01cc90f928a8db99fa94 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 4 Feb 2019 09:20:04 +0000 Subject: [PATCH 409/506] arm64: dts: renesas: r8a774c0: Add CMT device nodes This patch adds CMT{0|1|2|3} device nodes for r8a774c0 SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 70 +++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 71ff43e3bb41..756f960de519 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -259,6 +259,76 @@ reg = <0 0xe6060000 0 0x508>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a774c0-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a774c0-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a774c0-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a774c0-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a774c0-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; From 2262798c002f9d106d7903a067c59474c59850d1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 4 Feb 2019 09:20:07 +0000 Subject: [PATCH 410/506] arm64: dts: renesas: r8a774c0: Add TMU device nodes This patch adds TMU{0|1|2|3|4} device nodes for r8a774c0 SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 65 +++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 756f960de519..61a0afb74e63 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -378,6 +378,71 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; From aaf6c75c0458122600a20db9d41a0350f0a8dff8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 7 Feb 2019 08:31:49 +0000 Subject: [PATCH 411/506] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges mapping for pciec0 node. Also declare pcie bus clock, since it is generated on the CAT874 main board. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts index 477a56b3273c..96ee0d2c6357 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts @@ -56,6 +56,15 @@ clock-frequency = <48000000>; }; +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec0 { + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; +}; + &pfc { scif2_pins: scif2 { groups = "scif2_data_a"; From ee20aeefb53f6ffabed5b1a3b859294197eeb351 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 7 Feb 2019 08:31:50 +0000 Subject: [PATCH 412/506] arm64: dts: renesas: cat875: Enable PCIe support This patch enables PCIEC0 PCI express controller on the sub board. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/cat875.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi index 805ffa7fb67b..14db66755a89 100644 --- a/arch/arm64/boot/dts/renesas/cat875.dtsi +++ b/arch/arm64/boot/dts/renesas/cat875.dtsi @@ -30,6 +30,10 @@ }; }; +&pciec0 { + status = "okay"; +}; + &pfc { avb_pins: avb { mux { From 60b71a239bbd286232a547349815d6330f10db7c Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Tue, 29 Jan 2019 12:31:17 +0800 Subject: [PATCH 413/506] dt-bindings: interrupt-controller: update bindings for MT7623 This adds missing bindings for MT7623 sysirq. Signed-off-by: Ryder Lee Signed-off-by: Matthias Brugger --- .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt index 33a98eb44949..c5d589108a94 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt @@ -9,6 +9,7 @@ Required properties: "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135 "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127 "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622 + "mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623 "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795 "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797 "mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765 From 0d45062cfc891b4cba27fe017a6f5bcd5d3191f0 Mon Sep 17 00:00:00 2001 From: Vladimir Vid Date: Fri, 25 Jan 2019 18:17:08 +0100 Subject: [PATCH 414/506] arm64: dts: marvell: Add device tree for uDPU board This adds initial support for micro-DPU (uDPU) board which is based on Armada-3720 SoC. micro-DPU is the single-port FTTdp distribution point unit made by Methode Electronics which offers complete modularity with replaceable SFP modules both for uplink and downlink (G.hn over twisted-pair, G.hn over coax, 1G and 2.5G Ethernet over Cat-5e cable). On-board features: - 512 MiB DDR3 - 2 x 2.5G SFP via HSGMII SERDES interface to the A3720 SoC - USB 2.0 Type-C connector - 4GB eMMC - ETSI TS 101548 reverse powering via twisted pair (RJ45) or coax (F Type) Cc: Luka Perkov Cc: Luis Torres Cc: Scott Roberts Cc: Paul Arola Cc: Andrew Lunn Cc: Jason Cooper Cc: Gregory Clement Cc: Sebastian Hesselbarth Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Vladimir Vid Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../boot/dts/marvell/armada-3720-uDPU.dts | 162 ++++++++++++++++++ 2 files changed, 163 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 2eff1f927471..caed4334f27d 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -2,6 +2,7 @@ # Mvebu SoC Family dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts new file mode 100644 index 000000000000..bd4aab6092e0 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree for the uDPU board. + * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3) + * Copyright (C) 2016 Marvell + * Copyright (C) 2019 Methode Electronics + * Copyright (C) 2019 Telus + * + * Vladimir Vid + */ + +/dts-v1/; + +#include +#include "armada-372x.dtsi" + +/ { + model = "Methode uDPU Board"; + compatible = "methode,udpu", "marvell,armada3720"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; + + leds { + pinctrl-names = "default"; + compatible = "gpio-leds"; + + power1 { + label = "udpu:green:power"; + gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; + }; + + power2 { + label = "udpu:red:power"; + gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; + }; + + network1 { + label = "udpu:green:network"; + gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; + }; + + network2 { + label = "udpu:red:network"; + gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; + }; + + alarm1 { + label = "udpu:green:alarm"; + gpios = <&gpionb 15 GPIO_ACTIVE_LOW>; + }; + + alarm2 { + label = "udpu:red:alarm"; + gpios = <&gpionb 16 GPIO_ACTIVE_LOW>; + }; + }; + + sfp_eth0: sfp-eth0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c0>; + los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth1: sfp-eth1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>; + }; +}; + +&sdhci0 { + status = "okay"; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + marvell,pad-type = "fixed-1-8v"; + non-removable; + no-sd; + no-sdio; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_quad_pins>; + + m25p80@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <54000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + /* only bootloader is located on the SPI */ + partition@0 { + label = "uboot"; + reg = <0 0x400000>; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + lm75@48 { + status = "okay"; + compatible = "lm75"; + reg = <0x48>; + }; + + lm75@49 { + status = "okay"; + compatible = "lm75"; + reg = <0x49>; + }; +}; + +ð0 { + phy-mode = "sgmii"; + status = "okay"; + managed = "in-band-status"; + sfp = <&sfp_eth0>; +}; + +ð1 { + phy-mode = "sgmii"; + status = "okay"; + managed = "in-band-status"; + sfp = <&sfp_eth1>; +}; + +&usb3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; From cb92e40411ef8a773675b522d29b6ea82e5fb8e0 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Wed, 6 Feb 2019 19:05:26 +0100 Subject: [PATCH 415/506] arch: arm: dts: Remove disabled marvell,dsa properties These have been disable since the change to probe Marvell Ethernet switches as MDIO devices. Remove the properties now that the code to suppport them will also be removed soon. Signed-off-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-370-rd.dts | 42 -------------- arch/arm/boot/dts/armada-388-clearfog.dts | 58 ------------------- arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 47 --------------- arch/arm/boot/dts/kirkwood-dir665.dts | 47 --------------- arch/arm/boot/dts/kirkwood-linksys-viper.dts | 47 --------------- .../arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 47 --------------- arch/arm/boot/dts/kirkwood-rd88f6281.dtsi | 41 ------------- 7 files changed, 329 deletions(-) diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 2bfb3108b5b2..c910d157a686 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -114,48 +114,6 @@ }; }; }; - - dsa { - status = "disabled"; - - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð1>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; }; &pciec { diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts index 89a354b43978..20f8d4667753 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/armada-388-clearfog.dts @@ -30,64 +30,6 @@ }; }; - dsa@0 { - status = "disabled"; - - compatible = "marvell,dsa"; - dsa,ethernet = <ð1>; - dsa,mii-bus = <&mdio>; - pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; - pinctrl-names = "default"; - #address-cells = <2>; - #size-cells = <0>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4 0>; - - port@0 { - reg = <0>; - label = "lan5"; - }; - - port@1 { - reg = <1>; - label = "lan4"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - }; - - port@4 { - reg = <4>; - label = "lan1"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - - port@6 { - /* 88E1512 external phy */ - reg = <6>; - label = "lan6"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&rear_button_pins>; diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index 7a2606c3b62e..8480a16919a0 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -210,53 +210,6 @@ compatible = "pwm-fan"; pwms = <&gpio0 24 4000>; }; - - dsa { - status = "disabled"; - - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð0>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0>; /* MDIO address 0, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "internet"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; }; &pciec { diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts index 31ceacd841de..b3ad3f607d31 100644 --- a/arch/arm/boot/dts/kirkwood-dir665.dts +++ b/arch/arm/boot/dts/kirkwood-dir665.dts @@ -190,53 +190,6 @@ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; }; - - dsa { - status = "disabled"; - - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð0port>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0>; /* MDIO address 0, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - }; - }; - }; }; &mdio { diff --git a/arch/arm/boot/dts/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/kirkwood-linksys-viper.dts index a7d659b7145a..2f9660f3b457 100644 --- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts +++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts @@ -66,53 +66,6 @@ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; }; }; - - dsa { - status = "disabled"; - - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð0port>; - dsa,mii-bus = <&mdio>; - - switch@16,0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <16 0>; /* MDIO address 16, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "ethernet1"; - }; - - port@1 { - reg = <1>; - label = "ethernet2"; - }; - - port@2 { - reg = <2>; - label = "ethernet3"; - }; - - port@3 { - reg = <3>; - label = "ethernet4"; - }; - - port@4 { - reg = <4>; - label = "internet"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; }; &pinctrl { diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index 86d532916d56..2e1a75348908 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -107,53 +107,6 @@ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; }; - - dsa { - status = "disabled"; - - compatible = "marvell,dsa"; - #address-cells = <1>; - #size-cells = <0>; - - dsa,ethernet = <ð0port>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0>; /* MDIO address 0, switch 0 in tree */ - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; - }; }; &mdio { diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi index 0f22f0e6f56b..f1f8eee132e8 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi @@ -48,47 +48,6 @@ cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; /* No WP GPIO */ }; - }; - - dsa { - status = "disabled"; - - compatible = "marvell,dsa"; - #address-cells = <2>; - #size-cells = <0>; - - dsa,ethernet = <ð0port>; - dsa,mii-bus = <&mdio>; - - switch@0 { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - }; - }; }; }; From 785fb4342730fb58bbf81ce60a28e70dda4aeebf Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 8 Feb 2019 11:14:05 +0100 Subject: [PATCH 416/506] arm64: dts: meson: g12a: add peripheral clock controller Add the peripheral clock controller to the g12a SoC DT Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 3be649e4efa4..191d31db9853 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -99,6 +99,19 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; + + hhi: system-controller@0 { + compatible = "amlogic,meson-gx-hhi-sysctrl", + "simple-mfd", "syscon"; + reg = <0 0 0 0x400>; + + clkc: clock-controller { + compatible = "amlogic,g12a-clkc"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + }; }; }; From 148423b7454b6f2cee71e2c43aee99ab24acb434 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 18 Dec 2018 16:12:15 -0800 Subject: [PATCH 417/506] dt-bindings: arm: amlogic: add amediatech x96-max bindings Add new vendor for amediatech, and initial board: x96-max Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 1 + Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 8dbc259081e4..7f40cb5f490b 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -109,6 +109,7 @@ Board compatible values (alphabetically, grouped by SoC): - "amlogic,s400" (Meson axg a113d) - "amlogic,u200" (Meson g12a s905d2) + - "amediatech,x96-max" (Meson g12a s905x2) Amlogic Meson Firmware registers Interface ------------------------------------------ diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..4615d4b9d11e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -24,6 +24,7 @@ amarula Amarula Solutions amazon Amazon.com, Inc. amcc Applied Micro Circuits Corporation (APM, formally AMCC) amd Advanced Micro Devices (AMD), Inc. +amediatech Shenzhen Amediatech Technology Co., Ltd amlogic Amlogic, Inc. ampire Ampire Co., Ltd. ams AMS AG From d3aa4ce87348b59d7b240ae356559313a8db2f58 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 18 Dec 2018 16:19:28 -0800 Subject: [PATCH 418/506] arm64: dts: meson: add g12a x96 max board Add the G12a (S905X2) based X96 Max board[1]. There is no branding for the manufacturer anywhere on the product, so it took some digging[2] to find the manufacturer. But since there's nothing about the maker on the product I've left it out of the DT name because 1) nobody will know that name and 2) keeps the DT filename shorter. [1] https://www.cnx-software.com/2018/09/25/x96-max-amlogic-s905x2-tv-box/ [2] https://fccid.io/2AI6D-X96MAX Acked-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/meson-g12a-x96-max.dts | 28 +++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index f12efa27c636..0821fed4c074 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts new file mode 100644 index 000000000000..c62d3d5706ff --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 BayLibre SAS. All rights reserved. + */ + +/dts-v1/; + +#include "meson-g12a.dtsi" + +/ { + compatible = "amediatech,x96-max", "amlogic,u200", "amlogic,g12a"; + model = "Shenzhen Amediatech Technology Co., Ltd X96 Max"; + + aliases { + serial0 = &uart_AO; + }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; +}; + +&uart_AO { + status = "okay"; +}; From 4f63b1c3d6c4604866d3ffd1184b5a9f0fda61dc Mon Sep 17 00:00:00 2001 From: Remi Pommarel Date: Mon, 28 Jan 2019 21:07:27 +0100 Subject: [PATCH 419/506] arm64: dts: armada-3720-espressobin: Configure RGMII and SMI pins In order to be able to communicate with the 88e6341 switch some pins have to be repurposed as RGMII and SMI pins. This fixes ethernet support on system booted via a bootloader that has not already configured those pins (e.g. mainline u-boot, or vendor u-boot compiled without ethernet support). Signed-off-by: Remi Pommarel Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 ++ arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index 18938d133ae3..dcb610933bc7 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -198,6 +198,8 @@ }; ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&smi_pins>; phy-mode = "rgmii-id"; status = "okay"; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index b278b64b73e3..d4542bf10c11 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -271,6 +271,11 @@ function = "mii"; }; + smi_pins: smi-pins { + groups = "smi"; + function = "smi"; + }; + sdio_pins: sdio-pins { groups = "sdio_sb"; function = "sdio"; From 99ce97875973ab83a4f894a56cf7f59afdc3943f Mon Sep 17 00:00:00 2001 From: Remi Pommarel Date: Mon, 28 Jan 2019 21:07:28 +0100 Subject: [PATCH 420/506] arm64: dts: armada-3720-espressobin: Set mv88e6341 cpu port as RGMII-ID The mv88e6341 ethernet switch needs the cpu port control register to be set with TX and RX internal delay in order to work. This fixes ethernet support on system booted via a bootloader that has not already configured this register (e.g. mainline u-boot, or vendor u-boot compiled without ethernet support). Signed-off-by: Remi Pommarel Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index dcb610933bc7..67fa84bf8686 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -158,6 +158,11 @@ reg = <0>; label = "cpu"; ethernet = <ð0>; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; }; port@1 { From 8b0a14d97e282534f12ec254525642be69142cce Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 6 Feb 2019 00:05:12 +0100 Subject: [PATCH 421/506] arm64: dts: marvell: Remove unnecessary #address-cells/#size-cells under flashes By using the new binding for the partitions for the flashes we don't need anymore to use #size-cells and #address-cells at the flash node level. Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-7040-db.dts | 4 ---- arch/arm64/boot/dts/marvell/armada-8040-db.dts | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts index 412efdb46e7c..d20d84ce7ca8 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts @@ -66,8 +66,6 @@ status = "okay"; spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; @@ -169,8 +167,6 @@ status = "okay"; spi-flash@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; compatible = "jedec,spi-nor"; reg = <0x0>; spi-max-frequency = <20000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index 1bac437369a1..9f4f939ab65f 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -81,8 +81,6 @@ status = "okay"; spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; @@ -214,8 +212,6 @@ status = "okay"; spi-flash@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; compatible = "jedec,spi-nor"; reg = <0x0>; spi-max-frequency = <20000000>; From 2ef303f0fe44feee4a3ca8bd62fca86c105927d2 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 8 Jan 2019 17:31:24 +0100 Subject: [PATCH 422/506] arm64: dts: marvell: armada-37xx: declare the COMPHY node Describe the A3700 COMPHY node. It has three PHYs that can be configured as follow: * PCIe or GbE * USB3 or GbE * SATA or USB3 Each of them has its own memory area. Suggested-by: Grzegorz Jaszczyk Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index d4542bf10c11..1a1dbeb2d0ae 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -247,6 +247,35 @@ reg = <0x14000 0x60>; }; + comphy: phy@18300 { + compatible = "marvell,comphy-a3700"; + reg = <0x18300 0x300>, + <0x1F000 0x400>, + <0x5C000 0x400>, + <0xe0178 0x8>; + reg-names = "comphy", + "lane1_pcie_gbe", + "lane0_usb3_gbe", + "lane2_sata_usb3"; + #address-cells = <1>; + #size-cells = <0>; + + comphy0: phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + + comphy1: phy@1 { + reg = <1>; + #phy-cells = <1>; + }; + + comphy2: phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + pinctrl_sb: pinctrl@18800 { compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd"; From c38e13a2f8162a6d92985908c4a760a23c044dfe Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 8 Jan 2019 17:24:38 +0100 Subject: [PATCH 423/506] arm64: dts: marvell: armada-3720-espressobin: declare PCIe PHY The PCIe node is wired to the second PHY of the COMPHY IP. Suggested-by: Grzegorz Jaszczyk Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index 67fa84bf8686..d17fd5600c55 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -46,6 +46,7 @@ /* J9 */ &pcie0 { status = "okay"; + phys = <&comphy1 0>; pinctrl-names = "default"; pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; }; From 8e18c8e58da644018a6217dac5eaa0af8d0f390c Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 4 Dec 2018 20:28:31 +0100 Subject: [PATCH 424/506] arm64: dts: marvell: armada-3720-espressobin: declare SATA PHY property The SATA node is wired to the third PHY of the COMPHY IP. Suggested-by: Grzegorz Jaszczyk Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index d17fd5600c55..6be019e1888e 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -54,6 +54,8 @@ /* J6 */ &sata { status = "okay"; + phys = <&comphy2 0>; + phy-names = "sata-phy"; }; /* J1 */ From bd3d25b0734284dcf603173d54232c538eb6e385 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 29 Jan 2019 10:36:35 +0100 Subject: [PATCH 425/506] arm64: dts: marvell: armada-37xx: link USB hosts with their PHYs Reference the PHY nodes from the USB controller nodes. The USB3 host controller is wired to: * the first PHY of the COMPHY IP * the OTG-capable UTMI PHY The USB2 host controller is wired to: * the host-only UTMI PHY Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 1a1dbeb2d0ae..159c83a90b82 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -351,6 +351,8 @@ marvell,usb-misc-reg = <&usb32_syscon>; interrupts = ; clocks = <&sb_periph_clk 12>; + phys = <&comphy0 0>, <&usb2_utmi_otg_phy>; + phy-names = "usb3-phy", "usb2-utmi-otg-phy"; status = "disabled"; }; @@ -372,6 +374,8 @@ reg = <0x5e000 0x1000>; marvell,usb-misc-reg = <&usb2_syscon>; interrupts = ; + phys = <&usb2_utmi_host_phy>; + phy-names = "usb2-utmi-host-phy"; status = "disabled"; }; From ae88c9e783fa1a4dbfc00b81a770d954ed904730 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Mon, 7 Jan 2019 13:28:48 +0000 Subject: [PATCH 426/506] ARM: dts: imx6sx: Add DISPLAY power domain support This was implemented in the driver but not actually defined and referenced in dts. This makes it always on. From reference manual in section "10.4.1.4.1 Power Distribution": "Display domain - The DISPLAY domain contains GIS, CSI, PXP, LCDIF, PCIe, DCIC, and LDB. It is supplied by internal regulator." The current pd_pcie is actually only for PCIE_PHY, the PCIE ip block is actually inside the DISPLAY domain. Handle this by adding the pcie node in both power domains. Signed-off-by: Leonard Crestez Acked-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 272ff6133ec1..ecf3f3e5c0a0 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -785,6 +785,18 @@ clocks = <&clks IMX6SX_CLK_GPU>; }; + pd_disp: power-domain@2 { + reg = <2>; + #power-domain-cells = <0>; + clocks = <&clks IMX6SX_CLK_PXP_AXI>, + <&clks IMX6SX_CLK_DISPLAY_AXI>, + <&clks IMX6SX_CLK_LCDIF1_PIX>, + <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_LCDIF2_PIX>, + <&clks IMX6SX_CLK_CSI>, + <&clks IMX6SX_CLK_VADC>; + }; + pd_pci: power-domain@3 { reg = <3>; #power-domain-cells = <0>; @@ -1205,6 +1217,7 @@ interrupts = ; clocks = <&clks IMX6SX_CLK_PXP_AXI>; clock-names = "axi"; + power-domains = <&pd_disp>; status = "disabled"; }; @@ -1226,6 +1239,7 @@ <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + power-domains = <&pd_disp>; status = "disabled"; }; @@ -1237,6 +1251,7 @@ <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + power-domains = <&pd_disp>; status = "disabled"; }; @@ -1246,6 +1261,7 @@ clocks = <&clks IMX6SX_CLK_VADC>, <&clks IMX6SX_CLK_CSI>; clock-names = "vadc", "csi"; + power-domains = <&pd_disp>; status = "disabled"; }; }; @@ -1370,7 +1386,8 @@ <&clks IMX6SX_CLK_PCIE_REF_125M>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; - power-domains = <&pd_pci>; + power-domains = <&pd_disp>, <&pd_pci>; + power-domain-names = "pcie", "pcie_phy"; status = "disabled"; }; }; From f243bc821ee372ab499302c5ceacfd8dff8c438f Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 11 Dec 2018 14:51:13 +0100 Subject: [PATCH 427/506] ARM: dts: imx6ull: Fix i.MX6ULL/ULZ ocotp compatible Since imx6ulz.dtsi includes imx6ull.dtsi, we only need to fix the compatible string here to achieve the correct OTP size for both SoCs. Signed-off-by: Stefan Wahren Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index f3668fe69eac..9cd1a48dc2ef 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -30,6 +30,10 @@ >; }; +&ocotp { + compatible = "fsl,imx6ull-ocotp", "syscon"; +}; + / { soc { aips3: aips-bus@2200000 { From 143c3870ffd2d93204f7cb5d2784041bcaa4cbb2 Mon Sep 17 00:00:00 2001 From: BOUGH CHEN Date: Fri, 28 Dec 2018 03:26:16 +0000 Subject: [PATCH 428/506] ARM: dts: imx6ull: change to use new compatible "fsl,imx6ull-usdhc" for usdhc i.MX6ULL has errata ERR010450, there is I/O timing limitation, for SDR mode, SD card clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. This patch change to use the new compatible "fsl,imx6ull-usdhc" to follow this limitation. Signed-off-by: Haibo Chen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index 9cd1a48dc2ef..22e4a307fa59 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -34,6 +34,14 @@ compatible = "fsl,imx6ull-ocotp", "syscon"; }; +&usdhc1 { + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; +}; + +&usdhc2 { + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; +}; + / { soc { aips3: aips-bus@2200000 { From cc077d00fd39cc27f3d7e1927f55c4e3cc64fd69 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 11 Jan 2019 06:22:55 +0000 Subject: [PATCH 429/506] ARM: dts: imx7ulp: add sim node i.MX7ULP SoC revision info is inside the SIM mode's JTAG_ID register, add sim node to support SoC revision check. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7ulp.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index b86daf73bb89..fca6e50f37c8 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -347,4 +347,17 @@ gpio-ranges = <&iomuxc1 0 96 32>; }; }; + + m4aips1: bus@41080000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x41080000 0x80000>; + ranges; + + sim: sim@410a3000 { + compatible = "fsl,imx7ulp-sim", "syscon"; + reg = <0x410a3000 0x1000>; + }; + }; }; From 87489ec3a77f3e01bcf0d46e353ae7112ec8c4f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vok=C3=A1=C4=8D=20Michal?= Date: Tue, 15 Jan 2019 14:22:45 +0000 Subject: [PATCH 430/506] ARM: dts: imx: Add Y Soft IOTA Draco, Hydra and Ursa boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are i.MX6S/DL based SBCs embedded in various Y Soft products. All share the same board design but have slightly different HW configuration. Ursa - i.MX6S SoC, 512MB RAM DDR3, 4GB eMMC, microSD - parallel WVGA 7" LCD with touch panel - 1x Eth (QCA8334 switch) - USB OTG - USB host (micro-B) Draco - i.MX6S SoC, 512MB RAM DDR3, 4GB eMMC, microSD - parallel WVGA 7" LCD with touch panel - 2x Eth (QCA8334 switch) - USB OTG - USB host (micro-B) - RGB LED (I2C LP5562) - 3.5mm audio jack + codec (LM49350) Hydra - i.MX6DL SoC, 2GB RAM DDR3, 4GB eMMC, microSD - I2C OLED display, capacitive matrix keys - 2x Eth (QCA8334 switch) - USB OTG - RGB LED (I2C LP5562) - 3.5mm audio jack + codec (LM49350) - HDMI - miniPCIe slot Cc: Andrew Lunn Signed-off-by: Michal Vokáč Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 595 +++++++++++++++++++++ arch/arm/boot/dts/imx6dl-yapp4-draco.dts | 58 ++ arch/arm/boot/dts/imx6dl-yapp4-hydra.dts | 50 ++ arch/arm/boot/dts/imx6dl-yapp4-ursa.dts | 54 ++ 5 files changed, 760 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-yapp4-common.dtsi create mode 100644 arch/arm/boot/dts/imx6dl-yapp4-draco.dts create mode 100644 arch/arm/boot/dts/imx6dl-yapp4-hydra.dts create mode 100644 arch/arm/boot/dts/imx6dl-yapp4-ursa.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..c0a9b89b7670 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -445,6 +445,9 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-wandboard.dtb \ imx6dl-wandboard-revb1.dtb \ imx6dl-wandboard-revd1.dtb \ + imx6dl-yapp4-draco.dtb \ + imx6dl-yapp4-hydra.dtb \ + imx6dl-yapp4-ursa.dtb \ imx6q-apalis-eval.dtb \ imx6q-apalis-ixora.dtb \ imx6q-apalis-ixora-v1.1.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi new file mode 100644 index 000000000000..b715ab0fa1ff --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -0,0 +1,595 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015-2018 Y Soft Corporation, a.s. + +#include +#include +#include + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 32 64 128 255>; + default-brightness-level = <32>; + num-interpolated-steps = <8>; + power-supply = <&sw2_reg>; + status = "disabled"; + }; + + lcd_display: display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + status = "disabled"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel: panel { + compatible = "dataimage,scf0700c48ggu18"; + power-supply = <&sw2_reg>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "okay"; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + phy-reset-duration = <20>; + phy-supply = <&sw2_reg>; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + switch@0 { + compatible = "qca,qca8334"; + reg = <0>; + + switch_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: port@0 { + reg = <0>; + label = "cpu"; + phy-mode = "rgmii"; + ethernet = <&fec>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@2 { + reg = <2>; + label = "eth2"; + phy-handle = <&phy_port2>; + }; + + port@3 { + reg = <3>; + label = "eth1"; + phy-handle = <&phy_port3>; + }; + }; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + ddc-i2c-bus = <&i2c2>; + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze200"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x8>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vsnvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + leds: led-controller@30 { + compatible = "ti,lp5562"; + reg = <0x30>; + clock-mode = /bits/ 8 <1>; + status = "disabled"; + + chan0 { + chan-name = "R"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + }; + + chan1 { + chan-name = "G"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + }; + + chan2 { + chan-name = "B"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + }; + + chan3 { + chan-name = "W"; + led-cur = /bits/ 8 <0x0>; + max-cur = /bits/ 8 <0x0>; + }; + }; + + eeprom@57 { + compatible = "atmel,24c128"; + reg = <0x57>; + pagesize = <64>; + status = "okay"; + }; + + touchscreen: touchscreen@5c { + compatible = "pixcir,pixcir_tangoc"; + reg = <0x5c>; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + status = "disabled"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; + + oled: oled@3d { + compatible = "solomon,ssd1305fb-i2c"; + reg = <0x3d>; + solomon,height = <64>; + solomon,width = <128>; + solomon,page-offset = <0>; + solomon,prechargep2 = <15>; + reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; + vbat-supply = <&sw2_reg>; + status = "disabled"; + }; + + gpio_oled: gpio@41 { + compatible = "nxp,pca9536"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x41>; + vcc-supply = <&sw2_reg>; + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1b898 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b098 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b098 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b098 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098 + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbus { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098 + >; + }; + + pinctrl_usbotg_vbus: usbotg-vbus { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b018 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b018 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 + >; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; + status = "disabled"; +}; + +&pwm1 { + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_usb_h1_vbus>; + status = "disabled"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usb_otg_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; + status = "okay"; +}; + +&usbphy2 { + fsl,tx-d-cal = <109>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <&sw2_reg>; + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + vmmc-supply = <&sw2_reg>; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-draco.dts b/arch/arm/boot/dts/imx6dl-yapp4-draco.dts new file mode 100644 index 000000000000..a38c407fd837 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-yapp4-draco.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015-2018 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Draco i.MX6Solo board"; + compatible = "ysoft,imx6dl-yapp4-draco", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; + +&backlight { + status = "okay"; +}; + +&lcd_display { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&panel { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchscreen { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts b/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts new file mode 100644 index 000000000000..f97927064750 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015-2018 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Hydra i.MX6DualLite board"; + compatible = "ysoft,imx6dl-yapp4-hydra", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +®_pcie { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts b/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts new file mode 100644 index 000000000000..0d594e4bd559 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015-2018 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Ursa i.MX6Solo board"; + compatible = "ysoft,imx6dl-yapp4-ursa", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; + +&backlight { + status = "okay"; +}; + +&lcd_display { + status = "okay"; +}; + +&panel { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&switch_ports { + /delete-node/ port@2; +}; + +&touchscreen { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; From 69ab17b53e35779122c7e7e198aa2868a993f855 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 16 Jan 2019 16:55:53 -0200 Subject: [PATCH 431/506] ARM: dts: vf610-zii-ssmb-spu3: Pass "no-sdio"/"no-sd" properties esdhc0 is connected to an eMMC, so it is safe to pass the "no-sdio"/"no-sd" properties. esdhc1 is wired to a standard SD socket, so pass the "no-sdio" property. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 757af56e8ee7..0d9fe5ac83a3 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -99,6 +99,8 @@ non-removable; no-1-8-v; keep-power-in-suspend; + no-sdio; + no-sd; status = "okay"; }; @@ -106,6 +108,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; bus-width = <4>; + no-sdio; status = "okay"; }; From d2b91ab1480618885fe0a7f240b7e7710344a066 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Fri, 18 Jan 2019 14:31:13 +0100 Subject: [PATCH 432/506] ARM: dts: imx6*-apalis/-colibri: mark I2C recovery GPIOs as open drain Since commit d2d0ad2aec4a ("i2c: imx: use open drain for recovery GPIO") GPIO lib expects this GPIO to be configured as open drain. Make sure we define this GPIO as open drain in the device tree. This gets rid of the following warning: gpio-81 (scl): enforced open drain please flag it properly in DT/ACPI DSDT/board file Note that currently the i.MX pinctrl driver does not support enabling open drain directly, so this patch has no effect in practice. Open drain is enabled by the fixed pinmux entry. Signed-off-by: Stefan Agner Reviewed-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 4 ++-- arch/arm/boot/dts/imx6ull-colibri.dtsi | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 8380f1b26826..5e6cec92e090 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -369,8 +369,8 @@ pinctrl-names = "default", "recovery"; pinctrl-0 = <&pinctrl_i2c3>; pinctrl-1 = <&pinctrl_i2c3_recovery>; - scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 87e15e7cb32b..8a27c2a05678 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -298,8 +298,8 @@ pinctrl-names = "default", "recovery"; pinctrl-0 = <&pinctrl_i2c3>; pinctrl-1 = <&pinctrl_i2c3_recovery>; - scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 6c63a7384611..9ad1da159768 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -94,16 +94,16 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; &i2c2 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; ad7879@2c { From 82ae9038ddccbda9a9d7dc06a2a5c65e9a34f281 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Mon, 21 Jan 2019 09:57:05 +0000 Subject: [PATCH 433/506] ARM: dts: imx6: Add support for Phytec phyBOARD i.MX6UL Segin The Phytec phyBOARD Segin is i.MX6 based SBC, available with either an i.MX6UL or i.MX6ULL SOM and various add-on boards. The following adds support for the "Full Featured" version of the Segin, which is provided with the i.MX6UL SOM and the PEB-EVAL-01 evaluation module. Its hardware specifications are: * 512MB DDR3 memory * 512MB NAND flash * Dual 10/100 Ethernet * USB Host and USB OTG * RS232 * MicroSD external storage * Audio, RS232, I2C, SPI, CAN headers * Further I/O options via A/V and Expansion headers Signed-off-by: Martyn Welch Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi | 148 ++++++++ .../boot/dts/imx6ul-phytec-peb-eval-01.dtsi | 55 +++ .../dts/imx6ul-phytec-phyboard-segin-full.dts | 89 +++++ .../dts/imx6ul-phytec-phyboard-segin.dtsi | 329 ++++++++++++++++++ 5 files changed, 622 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts create mode 100644 arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c0a9b89b7670..ac1eeb9afdb7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -564,6 +564,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-opos6uldev.dtb \ imx6ul-pico-hobbit.dtb \ imx6ul-pico-pi.dtb \ + imx6ul-phytec-phyboard-segin-full.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi b/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi new file mode 100644 index 000000000000..fc2997449b49 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +#include +#include +#include +#include "imx6ul.dtsi" + +/ { + model = "Phytec phyCORE i.MX6 UltraLite"; + compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + /* + * Set the minimum memory size here and + * let the bootloader set the real size. + */ + memory { + device_type = "memory"; + reg = <0x80000000 0x8000000>; + }; + + gpio_leds_som: leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioleds_som>; + compatible = "gpio-leds"; + + led_green { + label = "phycore:green"; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + eeprom@52 { + compatible = "catalyst,24c32", "atmel,24c32"; + reg = <0x52>; + }; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059 + >; + }; + + pinctrl_gpioleds_som: gpioledssomgrp { + fsl,pins = ; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c1: i2cgrp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + +}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi new file mode 100644 index 000000000000..e2f38f39a6ad --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik + * Author: Christian Hemp + */ + +#include + +/ { + gpio_keys: gpio-keys { + compatible = "gpio-key"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + power { + label = "Power Button"; + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + user_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>; + status = "disabled"; + + led_yellow { + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led_red { + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; +}; + +&iomuxc { + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79 + >; + }; + + pinctrl_user_leds: user_ledsgrp { + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x79 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts b/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts new file mode 100644 index 000000000000..b6a1407a9d44 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/dts-v1/; +#include "imx6ul-phytec-pcl063.dtsi" +#include "imx6ul-phytec-phyboard-segin.dtsi" +#include "imx6ul-phytec-peb-eval-01.dtsi" + +/ { + model = "Phytec phyBOARD-Segin i.MX6 UltraLite Full Featured"; + compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul"; +}; + +&adc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&tlv320 { + status = "okay"; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +®_can1_en { + status = "okay"; +}; + +®_sound_1v8 { + status = "okay"; +}; + +®_sound_3v3 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; + +&sound { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi new file mode 100644 index 000000000000..7bf439a77d2c --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 PHYTEC Messtechnik GmbH + * Author: Christian Hemp + */ + +/ { + model = "Phytec phyBOARD-Segin i.MX6 UltraLite"; + compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + reg_sound_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "i2s-audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "disabled"; + }; + + reg_sound_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "i2s-audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + + reg_can1_en: regulator-can1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&princtrl_flexcan1_en>; + regulator-name = "Can"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_adc1_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "Speaker", "SPOP", + "Speaker", "SPOM", + "LINE1L", "Line In", + "LINE1R", "Line In"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&tlv320>; + clocks = <&clks IMX6UL_CLK_SAI2>; + }; + }; + +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + vref-supply = <®_adc1_vref_3v3>; + /* + * driver can not separate a specific channel so we request 4 channels + * here - we need only the fourth channel + */ + num-channels = <4>; + status = "disabled"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_en>; + status = "disabled"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "disabled"; +}; + +&i2c1 { + tlv320: codec@18 { + compatible = "ti,tlv320aic3007"; + #sound-dai-cells = <0>; + reg = <0x18>; + AVDD-supply = <®_sound_3v3>; + IOVDD-supply = <®_sound_3v3>; + DRVDD-supply = <®_sound_3v3>; + DVDD-supply = <®_sound_1v8>; + status = "disabled"; + }; + + stmpe: touchscreen@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stmpe>; + status = "disabled"; + + touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + touchscreen-inverted-x = <1>; + touchscreen-inverted-y = <1>; + }; + }; + + i2c_rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + compatible = "microcrystal,rv4162"; + reg = <0x68>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + }; +}; + +&mdio { + ethphy1: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <19200000>; + fsl,sai-mclk-direction-output; + status = "disabled"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "disabled"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + status = "disabled"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "disabled"; +}; + +&iomuxc { + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1 { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + princtrl_flexcan1_en: flexcan1engrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; +}; From 063182a4c85673c735508dc01dd07fffbe7defb1 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 21 Jan 2019 16:53:27 +0100 Subject: [PATCH 434/506] ARM: dts: colibri: use valid range configuration for weim A valid WEIM range configuration must specify range entries for all four chip selects. This fixes an error on boot: imx-weim: probe of 21b8000.weim failed with error -22 Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index d5f7a1703aae..9a5d6c94cca4 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -228,10 +228,11 @@ &weim { status = "okay"; - /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */ + /* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */ ranges = <0 0 0x08000000 0x02000000 1 0 0x0a000000 0x02000000 - 2 0 0x0c000000 0x02000000>; + 2 0 0x0c000000 0x02000000 + 3 0 0x0e000000 0x02000000>; /* SRAM on Colibri nEXT_CS0 */ sram@0,0 { From da8782f673a1986bc8691461d3e6ccea988257da Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 22 Jan 2019 09:51:44 +0530 Subject: [PATCH 435/506] ARM: dts: Add devicetree compatibles for LS1021A based boards Add missing devicetree compatibles for the following LS1021A based boards: ls1021a-moxa-uc-8410a.dts ls1021a-qds.dts ls1021a-twr.dts Signed-off-by: Manivannan Sadhasivam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1 + arch/arm/boot/dts/ls1021a-qds.dts | 1 + arch/arm/boot/dts/ls1021a-twr.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts index 6a83f30029ea..ba1ddd93b8f8 100644 --- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts +++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts @@ -18,6 +18,7 @@ / { model = "Moxa UC-8410A"; + compatible = "fsl,ls1021a-moxa-uc-8410a", "fsl,ls1021a"; aliases { enet0_rgmii_phy = &rgmii_phy0; diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index 923a25760516..ca60730dda40 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -51,6 +51,7 @@ / { model = "LS1021A QDS Board"; + compatible = "fsl,ls1021a-qds", "fsl,ls1021a"; aliases { enet0_rgmii_phy = &rgmii_phy1; diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts index 8b48c3c7cd21..97e1fb7ea932 100644 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -51,6 +51,7 @@ / { model = "LS1021A TWR Board"; + compatible = "fsl,ls1021a-twr", "fsl,ls1021a"; aliases { enet2_rgmii_phy = &rgmii_phy1; From a822029a0cc0b838bff043482629f5fb9c2deb32 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 22 Jan 2019 14:21:34 +0100 Subject: [PATCH 436/506] ARM: dts: Add stmpe-adc DT node to Toradex iMX6 modules Add the stmpe-adc DT node as found on Toradex iMX6 modules Signed-off-by: Philippe Schenker Reviewed-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 22 ++++++++++++++-------- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 22 ++++++++++++++-------- 2 files changed, 28 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 5e6cec92e090..7c4ad541c3f5 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -332,11 +332,17 @@ id = <0>; blocks = <0x5>; irq-trigger = <0x1>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; stmpe_touchscreen { compatible = "st,stmpe-ts"; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; /* 8 sample average control */ st,ave-ctrl = <3>; /* 7 length fractional part in z */ @@ -346,17 +352,17 @@ * current limit value */ st,i-drive = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; /* 1 ms panel driver settling time */ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 8a27c2a05678..1beac22266ed 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -262,11 +262,17 @@ id = <0>; blocks = <0x5>; irq-trigger = <0x1>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; stmpe_touchscreen { compatible = "st,stmpe-ts"; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; /* 8 sample average control */ st,ave-ctrl = <3>; /* 7 length fractional part in z */ @@ -276,17 +282,17 @@ * current limit value */ st,i-drive = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; /* 1 ms panel driver settling time */ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; }; }; From 85761f4560dde582e56e93df6667ec65f707a1fe Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 28 Jan 2019 10:08:13 -0200 Subject: [PATCH 437/506] arm64: dts: imx8mq: Add ECSPI support Add support for the three ECSPI ports present on i.MX8MQ. Signed-off-by: Fabio Estevam Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index c2c5f3ee3ce3..4c23e9a6b52a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -25,6 +25,9 @@ serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; }; ckil: clock-ckil { @@ -383,6 +386,42 @@ #size-cells = <1>; ranges = <0x30800000 0x30800000 0x400000>; + ecspi1: spi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, + <&clk IMX8MQ_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: spi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, + <&clk IMX8MQ_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: spi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, + <&clk IMX8MQ_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart1: serial@30860000 { compatible = "fsl,imx8mq-uart", "fsl,imx6q-uart"; From 39f1622b5c941fb1b7e89c70cec9b51f74b20399 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 11 Feb 2019 09:53:35 +0800 Subject: [PATCH 438/506] arm64: dts: imx8mq: Add QuadSPI controller Add a node for the Freescale/NXP QuadSPI controller and extend the AIPS3 memory range to accommodate the QuadSPI-memory region. Signed-off-by: Carlo Caione Reviewed-by: Lucas Stach Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 4c23e9a6b52a..8e98c664d54c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -384,7 +384,8 @@ compatible = "fsl,imx8mq-aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>; + ranges = <0x30800000 0x30800000 0x400000>, + <0x08000000 0x08000000 0x10000000>; ecspi1: spi@30820000 { #address-cells = <1>; @@ -536,6 +537,20 @@ status = "disabled"; }; + qspi0: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, + <0x08000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, + <&clk IMX8MQ_CLK_QSPI_ROOT>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + fec1: ethernet@30be0000 { compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; From f9f818cf256a60268acdf0daddc8e4a1b5177823 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 30 Jan 2019 12:05:10 +0000 Subject: [PATCH 439/506] arm64: dts: imx8mq-evk: Enable the QuadSPI controller Enable the Freescale/NXP QuadSPI controller with a proper pinctrl set on the i.MX8MQ EVK board. Signed-off-by: Carlo Caione Reviewed-by: Lucas Stach Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 26 ++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 00b2904e16eb..d3fcb8872948 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -158,6 +158,20 @@ status = "okay"; }; +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + n25q256a: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + }; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -216,6 +230,18 @@ >; }; + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + + >; + }; + pinctrl_reg_usdhc2: regusdhc2grpgpio { fsl,pins = < MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 From 3ea95c31351946b4a50742fb6907f4c9706ac98f Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 31 Jan 2019 15:01:22 +0000 Subject: [PATCH 440/506] arm64: dts: imx8mq: Add RTC support Add RTC support for i.MX8MQ. Signed-off-by: Abel Vesa Tested-by: Chris Spencer Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 8e98c664d54c..1dc3f05e3199 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -242,6 +242,20 @@ interrupts = ; }; + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x30370000 0x10000>; + + snvs_rtc: snvs-rtc-lp{ + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap =<&snvs>; + offset = <0x34>; + interrupts = , + ; + }; + + }; + clk: clock-controller@30380000 { compatible = "fsl,imx8mq-ccm"; reg = <0x30380000 0x10000>; From b3f6a5f216e5f244dcd9b0d36b1c2434ecc4b6c0 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 2 Feb 2019 14:41:58 +0000 Subject: [PATCH 441/506] arm64: dts: imx8mq: Add ARM PMU node Add the node for the ARM Performance Monitor Units. Signed-off-by: Carlo Caione Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 1dc3f05e3199..8e130ec29091 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -120,6 +120,13 @@ }; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + interrupt-parent = <&gic>; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; From ca04fed4706dfb13cb964be2dc294054ed0efb6b Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 8 Feb 2019 19:53:49 +0100 Subject: [PATCH 442/506] arm64: dts: imx8mq: specify dma-ranges The peripheral bus on the i.MX8MQ is still limited to 32bits, so we need to declare the usable range for device DMA operations, as the DRAM will extend across the 32bit boundary if more than 3GB are installed. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 8e130ec29091..c626ccbbc500 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -147,6 +147,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; bus@30000000 { /* AIPS1 */ compatible = "fsl,imx8mq-aips-bus", "simple-bus"; From 29f0023d01f063feacfc404f0446905aee4f82ee Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 29 Dec 2018 15:35:56 +0100 Subject: [PATCH 443/506] ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the Odroid-C1+ schematics the Ethernet TXD1 signal is routed to GPIOH_5 and the TXD0 signal is routed to GPIOH_6. The public S805 datasheet shows that TXD0 can be routed to DIF_2_P and TXD1 can be routed to DIF_2_N instead. The pin groups eth_txd0_0 (GPIOH_6) and eth_txd0_1 (DIF_2_P) are both configured as Ethernet TXD0 and TXD1 data lines in meson8b.dtsi. At the same time eth_txd1_0 (GPIOH_5) and eth_txd1_1 (DIF_2_N) are configured as TXD0 and TXD1 data lines as well. This results in a bad Ethernet receive performance. Presumably this is due to the eth_txd0 and eth_txd1 signal being routed to the wrong pins. As a result of that data can only be transmitted on eth_txd2 and eth_txd3. However, I have no scope to fully confirm this assumption. The vendor u-boot sources for Odroid-C1 use the following Ethernet pinmux configuration: SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f); SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000); This translates to the following pin groups in the mainline kernel: - register 6 bit 0: eth_rxd1 (DIF_0_P) - register 6 bit 1: eth_rxd0 (DIF_0_N) - register 6 bit 2: eth_rx_dv (DIF_1_P) - register 6 bit 3: eth_rx_clk (DIF_1_N) - register 6 bit 6: eth_tx_en (DIF_3_P) - register 6 bit 8: eth_ref_clk (DIF_3_N) - register 6 bit 9: eth_mdc (DIF_4_P) - register 6 bit 10: eth_mdio_en (DIF_4_N) - register 6 bit 11: eth_tx_clk (GPIOH_9) - register 6 bit 12: eth_txd2 (GPIOH_8) - register 6 bit 13: eth_txd3 (GPIOH_7) - register 7 bit 20: eth_txd0_0 (GPIOH_6) - register 7 bit 21: eth_txd1_0 (GPIOH_5) - register 7 bit 22: eth_rxd3 (DIF_2_P) - register 7 bit 23: eth_rxd2 (DIF_2_N) Drop the eth_txd0_1 and eth_txd1_1 groups from eth_rgmii_pins to fix the Ethernet transmit performance on Odroid-C1. Also add the eth_rxd2 and eth_rxd3 groups so we don't rely on the bootloader to set them up. iperf3 statistics before this change: - transmitting from Odroid-C1: 741 Mbits/sec (0 retries) - receiving on Odroid-C1: 199 Mbits/sec (1713 retries) iperf3 statistics after this change: - transmitting from Odroid-C1: 667 Mbits/sec (0 retries) - receiving on Odroid-C1: 750 Mbits/sec (0 retries) Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description") Signed-off-by: Martin Blumenstingl Cc: Emiliano Ingrassia Cc: Linus Lüssing Tested-by: Emiliano Ingrassia Reviewed-by: Emiliano Ingrassia Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index dd498e681939..9fca77478fec 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -324,9 +324,7 @@ groups = "eth_tx_clk", "eth_tx_en", "eth_txd1_0", - "eth_txd1_1", "eth_txd0_0", - "eth_txd0_1", "eth_rx_clk", "eth_rx_dv", "eth_rxd1", @@ -335,7 +333,9 @@ "eth_mdc", "eth_ref_clk", "eth_txd2", - "eth_txd3"; + "eth_txd3", + "eth_rxd3", + "eth_rxd2"; function = "ethernet"; bias-disable; }; From b6db3936f2833c9f27aa9d868bb7bb6e87401b40 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:21 +0100 Subject: [PATCH 444/506] ARM: dts: meson: switch the clock controller to the HHI register area The clock controller on Meson8/Meson8m2 and Meson8b is part of a register region called "HHI". This register area contains more functionality than just a clock controller: - the clock controller - some reset controller bits - temperature sensor calibration data (on Meson8b and Meson8m2 only) - HDMI controller Allow access to this HHI register area as "system controller". Also migrate the Meson8 and Meson8b clock controllers to this new node. Signed-off-by: Martin Blumenstingl Acked-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 7 +++++++ arch/arm/boot/dts/meson8.dtsi | 15 ++++++++------- arch/arm/boot/dts/meson8b.dtsi | 15 ++++++++------- 3 files changed, 23 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index e4645f612712..536d6314d97e 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -72,6 +72,13 @@ #size-cells = <1>; ranges = <0x0 0xc1100000 0x200000>; + hhi: system-controller@4000 { + compatible = "amlogic,meson-hhi-sysctrl", + "simple-mfd", + "syscon"; + reg = <0x4000 0x400>; + }; + assist: assist@7c00 { compatible = "amlogic,meson-mx-assist", "syscon"; reg = <0x7c00 0x200>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 1ea5a36c5040..66b167537aaa 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -327,13 +327,6 @@ }; &cbus { - clkc: clock-controller@4000 { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "amlogic,meson8-clkc"; - reg = <0x8000 0x4>, <0x4000 0x400>; - }; - reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; reg = <0x4404 0x9c>; @@ -468,6 +461,14 @@ status = "okay"; }; +&hhi { + clkc: clock-controller { + compatible = "amlogic,meson8-clkc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +}; + &hwrng { compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 9fca77478fec..9faf70a6ed9a 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -276,13 +276,6 @@ }; &cbus { - clkc: clock-controller@4000 { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "amlogic,meson8b-clkc"; - reg = <0x8000 0x4>, <0x4000 0x400>; - }; - reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; reg = <0x4404 0x9c>; @@ -437,6 +430,14 @@ status = "okay"; }; +&hhi { + clkc: clock-controller { + compatible = "amlogic,meson8-clkc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +}; + &hwrng { compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; From c0ad99a2deacc7eab5f9bd9dd176bd4cbeea91e2 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:22 +0100 Subject: [PATCH 445/506] ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible The SAR ADC on Meson8m2 is slightly different compared to Meson8. The ADC functionality is identical but the calibration of the internal thermal sensor is different. Use the Meson8m2 specific compatible so the temperature sensor is calibrated correctly on boards using the Meson8m2 SoC. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8m2.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index d1a28c2adac5..bb87b251e16d 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -50,6 +50,10 @@ }; }; +&saradc { + compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; +}; + &wdt { compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; }; From f4c6e8e223c2c77cd3bdde4c9da280fb2338aa5b Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:23 +0100 Subject: [PATCH 446/506] ARM: dts: meson8: add the temperature calibration data for the SAR ADC The SAR ADC can measure the chip temperature of the SoC. This only works if the chip is calibrated and if the calibration data is written to the correct registers. The calibration data is stored in the upper two bytes of eFuse offset 0x1f4. This adds the eFuse cell for the temperature calibration data and passes it to the SAR ADC. We also need to pass the HHI sysctrl node to the SAR ADC because the 4th TSC (temperature sensor calibration coefficient) bit is stored in the HHI region (unlike bits [3:0] which are stored directly inside the SAR ADC's register area). On boards that have the SAR ADC enabled channel 8 can be used to measure the chip temperature. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 66b167537aaa..a9781243453e 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -449,6 +449,11 @@ compatible = "amlogic,meson8-efuse"; clocks = <&clkc CLKID_EFUSE>; clock-names = "core"; + + temperature_calib: calib@1f4 { + /* only the upper two bytes are relevant */ + reg = <0x1f4 0x4>; + }; }; ðmac { @@ -536,6 +541,9 @@ clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; + amlogic,hhi-sysctrl = <&hhi>; + nvmem-cells = <&temperature_calib>; + nvmem-cell-names = "temperature_calib"; }; &sdio { From bbbcf64360bb32c8eab46020b78a0c0e0de4c40c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:24 +0100 Subject: [PATCH 447/506] ARM: dts: meson8b: add the temperature calibration data for the SAR ADC The SAR ADC can measure the chip temperature of the SoC. This only works if the chip is calibrated and if the calibration data is written to the correct registers. The calibration data is stored in the upper two bytes of eFuse offset 0x1f4. This adds the eFuse cell for the temperature calibration data and passes it to the SAR ADC. We also need to pass the HHI sysctrl node to the SAR ADC because the 4th TSC (temperature sensor calibration coefficient) bit is stored in the HHI region (unlike bits [3:0] which are stored directly inside the SAR ADC's register area). On boards that have the SAR ADC enabled channel 8 can be used to measure the chip temperature. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 9faf70a6ed9a..fe84a8c3ce81 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -407,6 +407,11 @@ compatible = "amlogic,meson8b-efuse"; clocks = <&clkc CLKID_EFUSE>; clock-names = "core"; + + temperature_calib: calib@1f4 { + /* only the upper two bytes are relevant */ + reg = <0x1f4 0x4>; + }; }; ðmac { @@ -505,6 +510,9 @@ clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; + amlogic,hhi-sysctrl = <&hhi>; + nvmem-cells = <&temperature_calib>; + nvmem-cell-names = "temperature_calib"; }; &sdio { From 1a4f28ab2556deacd34b925bf419432a59670af6 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:25 +0100 Subject: [PATCH 448/506] ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-ec100.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 0872f6e3abf5..0cebe849a920 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -64,6 +64,11 @@ timeout-ms = <20000>; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + leds { compatible = "gpio-leds"; From a6c94928261a307002c4f8f3c0875c4a655a3a50 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:26 +0100 Subject: [PATCH 449/506] ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperature SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-odroidc1.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index 58669abda259..9251dc102fcc 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -118,6 +118,11 @@ 1800000 1>; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + vcc_1v8: regulator-vcc-1v8 { /* * RICHTEK RT9179 configured for a fixed output voltage of From e7e871b50f80145d37d13e8fbdc73a7dd52c4d88 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:27 +0100 Subject: [PATCH 450/506] ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperature SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts index f5853610b20b..d1d3c828c039 100644 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts @@ -44,6 +44,11 @@ }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&saradc 8>; + }; + vcc_3v3: regulator-vcc3v3 { compatible = "regulator-fixed"; regulator-name = "VCC3V3"; From b7d10841e5d7003bb8bc57c122494b4fb47836c0 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 19 Jan 2019 00:43:37 +0100 Subject: [PATCH 451/506] ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt The INTR32 pin of the IP101GR Ethernet PHY is routed to the GPIOH_3 pad on the SoC. Enable the interrupt function of the PHY's INTR32 pin to switch it from it's default "receive error" mode to "interrupt pin" mode. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-ec100.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 0cebe849a920..74b726fc0d30 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -169,6 +169,10 @@ eth_phy0: ethernet-phy@0 { /* IC Plus IP101A/G (0x02430c54) */ reg = <0>; + icplus,select-interrupt; + interrupt-parent = <&gpio_intc>; + /* GPIOH_3 */ + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; }; }; }; From 3e7db1c1b7a32dfbf1f9fc33d444c83e64dd3513 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 19 Jan 2019 00:43:38 +0100 Subject: [PATCH 452/506] ARM: dts: meson8b: ec100: improve the description of the regulators USB_VBUS is a controlled by a Silergy SY6288CCAC-GP 2A Power Distribution Switch. The name of it's enable GPIO signal is USB_PWR_EN. VCC5V is supplied by the main power input called PWR_5V_STB. The name of it's enable GPIO signal is 3V3_5V_EN. VCC3V3, VCC_DDR3_1V5 and VCCK (the CPU power supply) each use a separate Silergy SY8089AAC-GP 2A step down regulator. They are all supplied by the board's main 5V. VCC3V3 and VCC_DDR3_1V5 are fixed regulators while the voltage of VCCK can be changed by changing it's feedback voltage via PWM_C. VCC1V8 is an ABLIC S-1339D18-M5001-GP fixed voltage regulator which is supplied by VCC3V3. VCC_RTC is a Global Mixed-mode Technology Inc. G918T12U-GP LDO which. It is supplied by either VCC3V3 (when the board is powered) or the RTC coin cell battery. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-ec100.dts | 68 +++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 74b726fc0d30..34cd72911d63 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -88,6 +88,9 @@ }; usb_vbus: regulator-usb-vbus { + /* + * Silergy SY6288CCAC-GP 2A Power Distribution Switch. + */ compatible = "regulator-fixed"; regulator-name = "USB_VBUS"; @@ -95,11 +98,20 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* + * signal name from the schematics: USB_PWR_EN + */ gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; enable-active-high; }; vcc_5v: regulator-vcc5v { + /* + * supplied by the main power input which called PWR_5V_STB + * in the schematics + */ compatible = "regulator-fixed"; regulator-name = "VCC5V"; @@ -107,6 +119,9 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + /* + * signal name from the schematics: 3V3_5V_EN + */ gpio = <&gpio GPIODV_29 GPIO_ACTIVE_LOW>; regulator-boot-on; @@ -114,12 +129,18 @@ }; vcck: regulator-vcck { + /* + * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz + * Synchronous Step Down Regulator. + */ compatible = "pwm-regulator"; regulator-name = "VCCK"; regulator-min-microvolt = <860000>; regulator-max-microvolt = <1140000>; + vin-supply = <&vcc_5v>; + pwms = <&pwm_cd 0 1148 0>; pwm-dutycycle-range = <100 0>; @@ -128,19 +149,66 @@ }; vcc_1v8: regulator-vcc1v8 { + /* + * ABLIC S-1339D18-M5001-GP + */ compatible = "regulator-fixed"; regulator-name = "VCC1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + + vin-supply = <&vcc_3v3>; }; vcc_3v3: regulator-vcc3v3 { + /* + * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz + * Synchronous Step Down Regulator. Also called + * VDDIO_AO3.3V in the schematics. + */ compatible = "regulator-fixed"; regulator-name = "VCC3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + + vin-supply = <&vcc_5v>; + }; + + vcc_ddr3: regulator-vcc-ddr3 { + /* + * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz + * Synchronous Step Down Regulator. Also called + * DDR3_1.5V in the schematics. + */ + compatible = "regulator-fixed"; + + regulator-name = "VCC_DDR3_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + vin-supply = <&vcc_5v>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_rtc: regulator-vcc-rtc { + /* + * Global Mixed-mode Technology Inc. G918T12U-GP + */ + compatible = "regulator-fixed"; + + regulator-name = "VCC_RTC"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + /* + * When the board is powered then the input is VCC3V3, + * otherwise power is taken from the coin cell battery. + */ + vin-supply = <&vcc_3v3>; }; }; From 99f0619b0d0d87f921b05f0b7e43ff2e080a4fcc Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 19 Jan 2019 00:43:39 +0100 Subject: [PATCH 453/506] ARM: dts: meson8b: ec100: add the GPIO line names This adds the GPIO line names from the schematics to get them displayed in the debugfs output of each GPIO controller. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-ec100.dts | 50 +++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 34cd72911d63..889fdc31fb78 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -289,6 +289,56 @@ }; }; +&gpio_ao { + gpio-line-names = "Linux_TX", "Linux_RX", + "SLP_S5_N", "USB2_OC_FLAG#", + "HUB_RST", "USB_PWR_EN", + "I2S_IN", "SLP_S1_N", + "TCK", "TMS", "TDI", "TDO", + "HDMI_CEC", "5640_IRQ", + "MUTE", "S805_TEST#"; +}; + +&gpio { + gpio-line-names = /* Bank GPIOX */ + "WIFI_SD_D0", "WIFI_SD_D1", "WIFI_SD_D2", + "WIFI_SD_D3", "BTPCM_DOUT", "BTPCM_DIN", + "BTPCM_SYNC", "BTPCM_CLK", "WIFI_SD_CLK", + "WIFI_SD_CMD", "WIFI_32K", "WIFI_PWREN", + "UART_B_TX", "UART_B_RX", "UART_B_CTS_N", + "UART_B_RTS_N", "BT_EN", "WIFI_WAKE_HOST", + /* Bank GPIOY */ + "", "", "", "", "", "", "", "", "", "", + "", "", + /* Bank GPIODV */ + "VCCK_PWM_C", "I2C_SDA_A", "I2C_SCL_A", + "I2C_SDA_B", "I2C_SCL_B", "VDDEE_PWM_D", + "VDDEE_PWM 3V3_5V_EN", + /* Bank GPIOH */ + "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", + "RMII_IRQ", "RMII_RST#", "RMII_TXD1", + "RMII_TXD0", "AV_select_1", "AV_select_2", + "MCU_Control_S", + /* Bank CARD */ + "SD_D1_B", "SD_D0_B", "SD_CLK_8726MX", + "SD_CMD_8726MX", "SD_D3_B", "SD_D2_B", + "CARD_EN_DET (CARD_DET)", + /* Bank BOOT */ + "NAND_D0 (EMMC)", "NAND_D1 (EMMC)", + "NAND_D2 (EMMC)", "NAND_D3 (EMMC)", + "NAND_D4 (EMMC)", "NAND_D5 (EMMC)", + "NAND_D6 (EMMC)", "NAND_D7 (EMMC)", + "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)", + "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)", + "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)", + "nWE_S1 NAND_nWE (EMMC)", "", "", "SPI_CS", + /* Bank DIF */ + "RMII_RXD1", "RMII_RXD0", "RMII_CRS_DV", + "RMII_50M_IN", "GPIODIF_4", "GPIODIF_5", + "RMII_TXEN", "CPUETH_25MOUT", "RMII_MDC", + "RMII_MDIO"; +}; + &pwm_cd { status = "okay"; pinctrl-0 = <&pwm_c1_pins>; From bffe0d85e51a657d504cfd28345959e2fd28fc7b Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Mon, 4 Feb 2019 14:33:33 +0100 Subject: [PATCH 454/506] ARM: dts: imx6qdl-phytec-pfla02: add missing interrupt-controller property The DA9063 device need the required "interrupt-controller" property as documented by the bindings [1]. [1] Documentation/devicetree/bindings/mfd/da9063.txt Signed-off-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 1b50b01e9bac..1bfa41e01a0c 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -117,6 +117,7 @@ reg = <0x58>; interrupt-parent = <&gpio2>; interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */ + interrupt-controller; regulators { vddcore_reg: bcore1 { From 8de81c89d0a1aff777057dd78c3f5e4c654494f1 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 4 Feb 2019 16:29:56 +0100 Subject: [PATCH 455/506] ARM: dts: pfla02: add ksz9031 clock skew values The pfla02 SoM has a Micrel KSZ9031RNX ethernet phy connected to the FEC, which needs RX and TX clock skew settings to compensate for differences in line length. The skew values are taken from barebox commit 4c65c20f1071 ("ARM: pfla02: Set new ethernet phy tx timings"), which is based on patches originally provided by Phytec: TX_CLK line is approx. 54mm longer than other TX lines which adds a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we have to add a delay of 0.64ns. We choose 0.78 to have a little gap. This can be done by setting GTX pad skew value to 11100 Also add a delay for the RX delay lines, needed for the Duallite variant. => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F. Cc: Christian Hemp Signed-off-by: Philipp Zabel Signed-off-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 1bfa41e01a0c..433bf09a1954 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -89,10 +89,23 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ðphy>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; phy-supply = <&vdd_eth_io_reg>; status = "disabled"; + + fec_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + txc-skew-ps = <1680>; + rxc-skew-ps = <1860>; + }; + }; }; &gpmi { From 4a2c25961aa331e1a2574e6b323fb692d34f9e27 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Wed, 6 Feb 2019 00:16:41 +0100 Subject: [PATCH 456/506] ARM: dts: vf610: Add ZII SSMB DTU board Add the Zodiac Digital Tapping Unit, a VF610 based network device with 5 Ethernet ports. One of these ports supports 1000Base-T2. Signed-off-by: Andrew Lunn Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts | 311 +++++++++++++++++++++++ 2 files changed, 312 insertions(+) create mode 100644 arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ac1eeb9afdb7..351fadf05c9d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -603,6 +603,7 @@ dtb-$(CONFIG_SOC_VF610) += \ vf610-zii-dev-rev-b.dtb \ vf610-zii-dev-rev-c.dtb \ vf610-zii-scu4-aib.dtb \ + vf610-zii-ssmb-dtu.dtb \ vf610-zii-ssmb-spu3.dtb dtb-$(CONFIG_ARCH_MXS) += \ imx23-evk.dtb \ diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts new file mode 100644 index 000000000000..2b10672fadbd --- /dev/null +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Device tree file for ZII's SSMB DTU board + * + * SSMB - SPU3 Switch Management Board + * DTU - Digital Tapping Unit + * + * Copyright (C) 2015-2019 Zodiac Inflight Innovations + * + * Based on an original 'vf610-twr.dts' which is Copyright 2015, + * Freescale Semiconductor, Inc. + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 SSMB DTU Board"; + compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + max-brightness = <1>; + }; + }; + + reg_vcc_3v3_mcu: regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6190"; + pinctrl-0 = <&pinctrl_gpio_switch0>; + pinctrl-names = "default"; + reg = <0>; + eeprom-length = <65536>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "eth_cu_100_3"; + }; + + port@5 { + reg = <5>; + label = "eth_cu_1000_4"; + }; + + port@6 { + reg = <6>; + label = "eth_cu_1000_5"; + }; + + port@8 { + reg = <8>; + label = "eth_cu_1000_1"; + }; + + port@9 { + reg = <9>; + label = "eth_cu_1000_2"; + phy-handle = <&phy9>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + }; + + mdio1 { + compatible = "marvell,mv88e6xxx-mdio-external"; + #address-cells = <1>; + #size-cells = <0>; + + phy9: phy9@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + pinctrl-0 = <&pinctrl_gpio_phy9>; + pinctrl-names = "default"; + interrupt-parent = <&gpio2>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + reg = <0>; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + gpio6: gpio-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + /* On SSMB */ + temperature-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + /* On DSB */ + temperature-sensor@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "nameplate"; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTD4__DSPI1_CS1 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_phy9: pinctrl-gpio-phy9 { + fsl,pins = < + VF610_PAD_PTB24__GPIO_94 0x219d + >; + }; + + pinctrl_gpio_switch0: pinctrl-gpio-switch0 { + fsl,pins = < + VF610_PAD_PTE2__GPIO_107 0x31c2 + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; +}; From 1e797150e02629c6617efd9bd81914667090ffe7 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 7 Feb 2019 15:18:30 +0000 Subject: [PATCH 457/506] ARM: dts: imx6qdl-sabresd: add regulator control for isl29023 sensor The isl29023 light sensor driver has supported regulator control, assign the power supply for isl29023 to enable the control. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 8930aec6464c..21e03b1b31a9 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -449,6 +449,7 @@ pinctrl-0 = <&pinctrl_i2c3_isl29023_int>; interrupt-parent = <&gpio3>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + vcc-supply = <®_sensors>; }; }; From 72af502f17b8ed851c13f4dbb00aa00c1288f321 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 7 Feb 2019 15:18:34 +0000 Subject: [PATCH 458/506] ARM: dts: imx6qdl-sabresd: add regulators control for mag3110 sensor The mag3110 sensor driver has supported regulators control, assign the power supplies for mag3110 to enable the control. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 21e03b1b31a9..618f186a3370 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -440,6 +440,8 @@ pinctrl-0 = <&pinctrl_i2c3_mag3110_int>; interrupt-parent = <&gpio3>; interrupts = <16 IRQ_TYPE_EDGE_RISING>; + vdd-supply = <®_sensors>; + vddio-supply = <®_sensors>; }; light-sensor@44 { From 14cc68e143b3f8bf712cb93e665ed3e135e22d25 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 7 Feb 2019 15:18:38 +0000 Subject: [PATCH 459/506] ARM: dts: imx6qdl-sabresd: add regulators control for mma8451 sensor The mma8451 sensor driver has supported regulators control, assign the power supplies for mma8451 to enable the control. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 618f186a3370..80b990150756 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -250,6 +250,8 @@ pinctrl-0 = <&pinctrl_i2c1_mma8451_int>; interrupt-parent = <&gpio1>; interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <®_sensors>; + vddio-supply = <®_sensors>; }; ov5642: camera@3c { From ee9ec3ea79c6b3a2c49ac0b406e401a8d0002abb Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 7 Feb 2019 15:18:42 +0000 Subject: [PATCH 460/506] ARM: dts: imx6qdl-sabresd: remove reg_sensors' regulator-always-on Now that all sensors supplied by reg_sensors have supported regulator control, reg_sensors does NOT need to be always ON, remove "regulator-always-on" to save power. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 80b990150756..a0705066ccba 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -64,7 +64,6 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-always-on; }; gpio-keys { From 1c207f911fe9c8e78efc5a4803a0aa8a18102a23 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 10 Feb 2019 14:57:23 -0600 Subject: [PATCH 461/506] ARM: dts: imx: Add support for Logic PD i.MX6QD EVM The EVM consists of a system on module (SOM) and baseboard, and LCD. This patch adds a DTSI file for the SOM and baseboard separately, then a wrapper to combine them and specify processor type and a LCD information. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi | 555 ++++++++++++++++++ arch/arm/boot/dts/imx6-logicpd-som.dtsi | 365 ++++++++++++ arch/arm/boot/dts/imx6q-logicpd.dts | 120 ++++ 3 files changed, 1040 insertions(+) create mode 100644 arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi create mode 100644 arch/arm/boot/dts/imx6-logicpd-som.dtsi create mode 100644 arch/arm/boot/dts/imx6q-logicpd.dts diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi new file mode 100644 index 000000000000..fb01fa6e4224 --- /dev/null +++ b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi @@ -0,0 +1,555 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. + +/ { + keyboard { + compatible = "gpio-keys"; + + btn0 { + gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>; + label = "btn0"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + btn1 { + gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>; + label = "btn1"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + btn2 { + gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>; + label = "btn2"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + btn3 { + gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>; + label = "btn3"; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + }; + + leds { + compatible = "gpio-leds"; + + gen-led0 { + label = "led0"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led0>; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + }; + + gen-led1 { + label = "led1"; + gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>; + }; + + gen-led2 { + label = "led2"; + gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + gen-led3 { + label = "led3"; + gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + reg_usb_otg_vbus: regulator-otg-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_otg>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_3v3: regulator-3v3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_3v3>; + compatible = "regulator-fixed"; + regulator-name = "reg_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_enet: regulator-ethernet { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_enet>; + compatible = "regulator-fixed"; + regulator-name = "ethernet-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + vin-supply = <&sw4_reg>; + }; + + reg_audio: regulator-audio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_audio>; + compatible = "regulator-fixed"; + regulator-name = "3v3_aud"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3>; + }; + + reg_hdmi: regulator-hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_hdmi>; + compatible = "regulator-fixed"; + regulator-name = "hdmi-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3>; + }; + + reg_uart3: regulator-uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_uart3>; + compatible = "regulator-fixed"; + regulator-name = "uart3-supply"; + gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_3v3>; + }; + + reg_1v8: regulator-1v8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_1v8>; + compatible = "regulator-fixed"; + regulator-name = "1v8-supply"; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_3v3>; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_pcie>; + regulator-name = "mpcie_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mipi: regulator-mipi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_mipi>; + regulator-name = "mipi_pwr_en"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + ssi-controller = <&ssi2>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + phy-supply = <®_enet>; + interrupt-parent = <&gpio1>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; + +&i2c3 { + ov5640: camera@10 { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x10>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DOVDD-supply = <®_mipi>; + AVDD-supply = <®_mipi>; + DVDD-supply = <®_mipi>; + reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + + port { + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + + pcf8575: gpio@20 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf8574>; + compatible = "nxp,pcf8575"; + reg = <0x20>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + lines-initial-states = <0x0710>; + wakeup-source; + }; +}; + +&ipu1_csi1_from_mipi_vc1 { + clock-lanes = <0>; + data-lanes = <1 2>; +}; + +&mipi_csi { + status = "okay"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&ssi2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_3v3>; + no-1-8-v; + keep-power-in-suspend; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */ + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_led0: led0grp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b1 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b1 + >; + }; + + pinctrl_pcf8574: pcf8575grp { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_1v8: reg1v8grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; + }; + + pinctrl_reg_3v3: reg3v3grp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 + >; + }; + + pinctrl_reg_audio: reg-audiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_reg_enet: reg-enetgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + >; + }; + + pinctrl_reg_hdmi: reg-hdmigrp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + >; + }; + + pinctrl_reg_mipi: reg-mipigrp { + fsl,pins = ; + }; + + pinctrl_reg_pcie: reg-pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_reg_uart3: reguart3grp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_reg_usb_h1_vbus: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_reg_usb_otg: reg-usb-otggrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069 + >; + }; + + pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + +}; diff --git a/arch/arm/boot/dts/imx6-logicpd-som.dtsi b/arch/arm/boot/dts/imx6-logicpd-som.dtsi new file mode 100644 index 000000000000..7ceae3573248 --- /dev/null +++ b/arch/arm/boot/dts/imx6-logicpd-som.dtsi @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. + +#include +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + reg_wl18xx_vmmc: regulator-wl18xx { + compatible = "regulator-fixed"; + regulator-name = "vwl1837"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vddcore"; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vddsoc"; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "gen_3v3"; + regulator-boot-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-name = "sw3a_vddr"; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-name = "sw3b_vddr"; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "gen_rgmii"; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-name = "gen_5v0"; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "gen_vsns"; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "gen_1v5"; + }; + + vgen2_reg: vgen2 { + regulator-name = "vgen2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-name = "gen_vadj_0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-name = "gen_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-name = "gen_vadj_1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-name = "gen_2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + coin_reg: coin { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; + }; + + temperature-sensor@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + interrupt-parent = <&gpio6>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + temperature-sensor@4a { + compatible = "ti,tmp102"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; + interrupt-parent = <&gpio6>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + pagesize = <32>; + read-only; /* Manufacturing EEPROM programmed at factory */ + reg = <0x51>; + }; + + eeprom@52 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x52>; + }; +}; + +/* Reroute power feeding the CPU to come from the external PMIC */ +®_arm +{ + vin-supply = <&sw1a_reg>; +}; + +®_soc +{ + vin-supply = <&sw1c_reg>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_gpmi_nand: gpmi-nandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < /* Enable ARM Debugger */ + MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_tempsense: tempsensegrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */ + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17049 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10049 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */ + >; + }; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "ti,wl1837-st"; + enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <&sw2_reg>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_wl18xx_vmmc>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + tcxo-clock-frequency = <26000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-logicpd.dts b/arch/arm/boot/dts/imx6q-logicpd.dts new file mode 100644 index 000000000000..45eb0b7f75f8 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-logicpd.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6-logicpd-som.dtsi" +#include "imx6-logicpd-baseboard.dtsi" + +/ { + model = "Logic PD i.MX6QD SOM-M3"; + compatible = "fsl,imx6q"; + + backlight: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 20000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <®_lcd>; + }; + + panel-lvds0 { + compatible = "okaya,rs800480t-7x0gp"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_lcd: regulator-lcd { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_reg>; + compatible = "regulator-fixed"; + regulator-name = "lcd_panel_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_3v3>; + startup-delay-us = <500000>; + }; + + reg_lcd_reset: regulator-lcd-reset { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_reset>; + compatible = "regulator-fixed"; + regulator-name = "nLCD_RESET"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_lcd>; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; + +}; + +&pwm3 { + status = "okay"; +}; + +®_hdmi { + regulator-always-on; /* Without this, the level shifter on HDMI doesn't turn on */ +}; + +&iomuxc { + pinctrl_lcd_reg: lcdreg { + fsl,pins = < + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */ + >; + }; + + pinctrl_lcd_reset: lcdreset { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */ + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* TOUCH_nPINTDAV */ + >; + }; +}; From 1241c72b6db13a1e294f9ea25577a3677733582e Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 21 Dec 2018 18:12:13 +0000 Subject: [PATCH 462/506] ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property Most of the legacy "gpio-key,wakeup" boolean property is already replaced with "wakeup-source". However few occurrences of old property has popped up again, probably from the remnants in downstream trees. Replace the legacy properties with the unified "wakeup-source" property introduced in the commit 700a38b27eef ("Input: gpio_keys - switch to using generic device properties") Cc: Michal Simek Signed-off-by: Sudeep Holla Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-zturn.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/zynq-zturn.dts b/arch/arm/boot/dts/zynq-zturn.dts index b38704657960..5ec616ebca08 100644 --- a/arch/arm/boot/dts/zynq-zturn.dts +++ b/arch/arm/boot/dts/zynq-zturn.dts @@ -54,7 +54,7 @@ label = "K1"; gpios = <&gpio0 0x32 0x1>; linux,code = <0x66>; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; From 361df77976664ae862620bf63b05604323687f6f Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Mon, 11 Feb 2019 12:27:27 +0000 Subject: [PATCH 463/506] ARM: dts: am335x: Add support for Bosch Guardian The Bosch Guardian is a TI am335x based device. It's hardware specifications are as follows: * 256 MB DDR3 memory * 512 MB NAND Flash * USB OTG * RS232 * MicroSD external storage * LCD Display interface Signed-off-by: Martyn Welch [tony@atomide.com: updated to use #include] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/am335x-guardian.dts | 511 ++++++++++++++++++++++++++ 2 files changed, 512 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-guardian.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..1ad9a6307b0a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -719,6 +719,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-cm-t335.dtb \ am335x-evm.dtb \ am335x-evmsk.dtb \ + am335x-guardian.dtb \ am335x-icev2.dtb \ am335x-lxm.dtb \ am335x-moxa-uc-2101.dtb \ diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts new file mode 100644 index 000000000000..c9611ea4b884 --- /dev/null +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -0,0 +1,511 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Robert Bosch Power Tools GmbH + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include +#include + +/ { + model = "Bosch AM335x Guardian"; + compatible = "bosch,am335x-guardian", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + button21 { + label = "guardian-power-button"; + linux,code = ; + gpios = <&gpio2 21 0>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + + led1 { + label = "green:heartbeat"; + gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:mmc0"; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + }; + + panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>; + pinctrl-1 = <&lcd_pins_sleep>; + + display-timings { + 320x240 { + hactive = <320>; + vactive = <240>; + hback-porch = <68>; + hfront-porch = <20>; + hsync-len = <1>; + vback-porch = <18>; + vfront-porch = <4>; + vsync-len = <1>; + clock-frequency = <9000000>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <24>; + bus-width = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + }; + + pwm7: dmtimer-pwm { + compatible = "ti,omap-dmtimer-pwm"; + ti,timers = <&timer7>; + pinctrl-names = "default"; + pinctrl-0 = <&dmtimer7_pins>; + }; + + vmmcsd_fixed: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&cppi41dma { + status = "okay"; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ + status = "okay"; + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + /* + * MTD partition table + * + * All SPL-* partitions are sized to minimal length which can + * be independently programmable. For NAND flash this is equal + * to size of erase-block. + */ + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SPL"; + reg = <0x0 0x40000>; + }; + + partition@1 { + label = "SPL.backup1"; + reg = <0x40000 0x40000>; + }; + + partition@2 { + label = "SPL.backup2"; + reg = <0x80000 0x40000>; + }; + + partition@3 { + label = "SPL.backup3"; + reg = <0xc0000 0x40000>; + }; + + partition@4 { + label = "u-boot"; + reg = <0x100000 0x100000>; + }; + + partition@5 { + label = "u-boot.backup1"; + reg = <0x200000 0x100000>; + }; + + partition@6 { + label = "u-boot-env"; + reg = <0x300000 0x40000>; + }; + + partition@7 { + label = "u-boot-env.backup1"; + reg = <0x340000 0x40000>; + }; + + partition@8 { + label = "UBI"; + reg = <0x380000 0x1fc80000>; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; + + tps: tps@24 { + reg = <0x24>; + }; +}; + +&lcdc { + blue-and-red-wiring = "crossed"; + status = "okay"; +}; + +&mmc1 { + bus-width = <0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vmmcsd_fixed>; + status = "okay"; +}; + +&rtc { + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; + system-power-controller; +}; + +&spi0 { + ti,pindir-d0-out-d1-in; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; +}; + +#include "tps65217.dtsi" + +&tps { + ti,pmic-shutdown-controller; + interrupt-parent = <&intc>; + interrupts = <7>; /* NMI */ + + backlight { + isel = <1>; /* 1 - ISET1, 2 ISET2 */ + fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ + default-brightness = <100>; + }; + + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1351500>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3a"; + regulator-always-on; + }; + }; +}; + +&tscadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin &gpio_pins>; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) + >; + }; + + dmtimer7_pins: pinmux_dmtimer7_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) + >; + }; + + gpio_keys_pins: pinmux_gpio_keys_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) + >; + }; + + gpio_pins: pinmux_gpio_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7) + AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7) + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) + >; + }; + + lcd_disen_pins: pinmux_lcd_disen_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) + >; + }; + + lcd_pins_default: pinmux_lcd_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + >; + }; + + lcd_pins_sleep: pinmux_lcd_pins_sleep { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + >; + }; + + leds_pins: pinmux_leds_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) + AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7) + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) + >; + }; + + spi0_pins: pinmux_spi0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + >; + }; + + nandflash_pins: pinmux_nandflash_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) + AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) + AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) + AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) + AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) + AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) + AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) + >; + }; +}; From 947b7802597106dcbef2ddca23d386f9339ba334 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Mon, 11 Feb 2019 17:20:07 +0100 Subject: [PATCH 464/506] ARM: dts: omap3-gta04: declare backlight in lcd node The lcd display of the gta04 has a backlight but the backlight was not referenced in the lcd node, so screen blanking did not turn off the backlight. Fix that. Signed-off-by: Andreas Kemnade Tested-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 843d8795118d..2a8fcc09094d 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -124,6 +124,7 @@ spi-cpol; spi-cpha; + backlight= <&backlight>; label = "lcd"; port { lcd_in: endpoint { @@ -133,7 +134,7 @@ }; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm11 0 12000000 0>; pwm-names = "backlight"; From 32dfc773a78426c4a637029e77631123622d2446 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Thu, 20 Dec 2018 14:23:13 +0900 Subject: [PATCH 465/506] arm64: dts: uniphier: Add PCIe host controller and PHY nodes Add PCIe host controller and PHY nodes. This supports for LD20, PXs3 and their boards. This node defines PCIe memory, I/O, and config spaces as follows. MEM: 20000000-2ffdffff (255MB) I/O: 2ffe0000-2ffeffff ( 64KB) CFG: 2fff0000-2fffffff ( 64KB) Signed-off-by: Kunihiko Hayashi Signed-off-by: Masahiro Yamada --- .../boot/dts/socionext/uniphier-ld20.dtsi | 47 +++++++++++++++++++ .../boot/dts/socionext/uniphier-pxs3-ref.dts | 4 ++ .../boot/dts/socionext/uniphier-pxs3.dtsi | 47 +++++++++++++++++++ 3 files changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 4a0c46cb11cd..ca9c51081e6b 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -869,6 +869,53 @@ }; }; + pcie: pcie@66000000 { + compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; + status = "disabled"; + reg-names = "dbi", "link", "config"; + reg = <0x66000000 0x1000>, <0x66010000 0x10000>, + <0x2fff0000 0x10000>; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + num-lanes = <1>; + num-viewport = <1>; + bus-range = <0x0 0xff>; + device_type = "pci"; + ranges = + /* downstream I/O */ + <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, + /* non-prefetchable memory */ + <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; + #interrupt-cells = <1>; + interrupt-names = "dma", "msi"; + interrupts = <0 224 4>, <0 225 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ + <0 0 0 2 &pcie_intc 1>, /* INTB */ + <0 0 0 3 &pcie_intc 2>, /* INTC */ + <0 0 0 4 &pcie_intc 3>; /* INTD */ + phy-names = "pcie-phy"; + phys = <&pcie_phy>; + + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <0 226 4>; + }; + }; + + pcie_phy: phy@66038000 { + compatible = "socionext,uniphier-ld20-pcie-phy"; + reg = <0x66038000 0x4000>; + #phy-cells = <0>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + socionext,syscon = <&soc_glue>; + }; + nand: nand@68000000 { compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts index a41f7cac952a..f91d77f6ccd8 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts @@ -112,3 +112,7 @@ &usb1 { status = "okay"; }; + +&pcie { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 4f57c9e9d7a8..080447d7fd67 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -727,6 +727,53 @@ }; }; + pcie: pcie@66000000 { + compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; + status = "disabled"; + reg-names = "dbi", "link", "config"; + reg = <0x66000000 0x1000>, <0x66010000 0x10000>, + <0x2fff0000 0x10000>; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + num-lanes = <1>; + num-viewport = <1>; + bus-range = <0x0 0xff>; + device_type = "pci"; + ranges = + /* downstream I/O */ + <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, + /* non-prefetchable memory */ + <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; + #interrupt-cells = <1>; + interrupt-names = "dma", "msi"; + interrupts = <0 224 4>, <0 225 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ + <0 0 0 2 &pcie_intc 1>, /* INTB */ + <0 0 0 3 &pcie_intc 2>, /* INTC */ + <0 0 0 4 &pcie_intc 3>; /* INTD */ + phy-names = "pcie-phy"; + phys = <&pcie_phy>; + + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <0 226 4>; + }; + }; + + pcie_phy: phy@66038000 { + compatible = "socionext,uniphier-pxs3-pcie-phy"; + reg = <0x66038000 0x4000>; + #phy-cells = <0>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + socionext,syscon = <&soc_glue>; + }; + nand: nand@68000000 { compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; From 519904a42ff8c2ed23651f33c256d009c656a50b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 21 Jan 2019 08:03:36 +0900 Subject: [PATCH 466/506] arm64: dts: uniphier: sort labels in the same order as in dtsi Sort the labels in the same order as in the corresponding dtsi file, in other words, the order of reg address. Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts | 8 ++++---- arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts index d7ae28afef7d..9ca692ed1b2b 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts @@ -145,10 +145,10 @@ }; }; -&nand { - status = "okay"; -}; - &usb { status = "okay"; }; + +&nand { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts index f91d77f6ccd8..1965e4dfe4a4 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts @@ -101,10 +101,6 @@ }; }; -&nand { - status = "okay"; -}; - &usb0 { status = "okay"; }; @@ -116,3 +112,7 @@ &pcie { status = "okay"; }; + +&nand { + status = "okay"; +}; From 42d712a74d0911516c3dcaf64b5ed831fa4cace3 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 11 Jan 2019 11:44:15 +0200 Subject: [PATCH 467/506] arm64: dts: ti: k3-am65: Add MSMC RAM node The AM65 SoC has 2MB MSMC RAM. Add this as a mmio-sram node so drivers can use it via genpool API. Following areas are marked reserved: - Lower 128KB for ATF - 64KB@0xf0000 for SYSFW - Upper 1MB for cache The reserved locations are subject to change at runtime by the bootloader. Cc: Nishanth Menon Cc: Lokesh Vutla Cc: Andrew F. Davis Signed-off-by: Roger Quadros Signed-off-by: Tero Kristo --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 9338315b0ca9..757c839718d6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -6,6 +6,26 @@ */ &cbass_main { + msmc_ram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x0 0x70000000 0x0 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x70000000 0x200000>; + + atf-sram@0 { + reg = <0x0 0x20000>; + }; + + sysfw-sram@f0000 { + reg = <0xf0000 0x10000>; + }; + + l3cache-sram@100000 { + reg = <0x100000 0x100000>; + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; From 7147f341e9827c33d3395c32f68753301d9f4d06 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Tue, 5 Feb 2019 14:45:20 +0200 Subject: [PATCH 468/506] arm64: dts: ti: am654: Add Main System Control Module node Main System control module support is added to the device tree to allow driver to access to their control module registers. Signed-off-by: Jyri Sarha Signed-off-by: Roger Quadros Signed-off-by: Tero Kristo --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 757c839718d6..d94ffce42a2b 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -225,4 +225,12 @@ ti,trm-icp = <0x8>; dma-coherent; }; + + scm_conf: scm_conf@100000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x00100000 0 0x1c000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x00100000 0x1c000>; + }; }; From cc54a99464ccdbb7ff34361f87d4cce714823e88 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 5 Feb 2019 14:45:21 +0200 Subject: [PATCH 469/506] arm64: dts: ti: k3-am6: add USB support Adds support for USB0 and USB1 instances on the AM6 SoC. USB0 is limited to high-speed for now. Signed-off-by: Roger Quadros Signed-off-by: Tero Kristo --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 76 ++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index d94ffce42a2b..752455269fab 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -233,4 +233,80 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; }; + + dwc3_0: dwc3@4000000 { + compatible = "ti,am654-dwc3"; + reg = <0x0 0x4000000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x4000000 0x20000>; + interrupts = ; + dma-coherent; + power-domains = <&k3_pds 151>; + assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ + + usb0: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x10000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + phys = <&usb0_phy>; + phy-names = "usb2-phy"; + snps,dis_u3_susphy_quirk; + }; + }; + + usb0_phy: phy@4100000 { + compatible = "ti,am654-usb2", "ti,omap-usb2"; + reg = <0x0 0x4100000 0x0 0x54>; + syscon-phy-power = <&scm_conf 0x4000>; + clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + }; + + dwc3_1: dwc3@4020000 { + compatible = "ti,am654-dwc3"; + reg = <0x0 0x4020000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x4020000 0x20000>; + interrupts = ; + dma-coherent; + power-domains = <&k3_pds 152>; + assigned-clocks = <&k3_clks 152 2>; + assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + + usb1: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x10000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + phys = <&usb1_phy>; + phy-names = "usb2-phy"; + }; + }; + + usb1_phy: phy@4110000 { + compatible = "ti,am654-usb2", "ti,omap-usb2"; + reg = <0x0 0x4110000 0x0 0x54>; + syscon-phy-power = <&scm_conf 0x4020>; + clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + }; }; From 7e7e7dd51d06952a8807214bbb3365b0d0c12b0a Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 5 Feb 2019 14:45:22 +0200 Subject: [PATCH 470/506] arm64: dts: ti: k3-am654-base-board: enable USB1 Add pinmux for USB1 and enable it as a dual role port. Signed-off-by: Roger Quadros Signed-off-by: Tero Kristo --- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 11e9a2a43dfc..a70e9049ad83 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -86,6 +86,12 @@ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ >; }; + + usb1_pins_default: usb1_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ + >; + }; }; &main_pmx1 { @@ -188,3 +194,25 @@ non-removable; ti,driver-strength-ohm = <50>; }; + +&dwc3_1 { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_default>; + dr_mode = "otg"; +}; + +&dwc3_0 { + status = "disabled"; +}; + +&usb0_phy { + status = "disabled"; +}; From 5bb57a7488c64a391107b2002d4e1f7d6bda00aa Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 8 Jan 2019 10:56:31 +0530 Subject: [PATCH 471/506] dt-bindings: input: ti-tsc-adc: Add new compatible for AM654 SoCs AM654 SoCs has ADC IP which is similar to AM335x, but without the touchscreen part. Add new compatible to handle AM654 SoCs. Also, it seems that existing compatible strings used in the kernel DTs were never documented. So, document them now. Signed-off-by: Vignesh R Reviewed-by: Rob Herring Acked-by: Dmitry Torokhov Signed-off-by: Tero Kristo --- .../devicetree/bindings/input/touchscreen/ti-tsc-adc.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt b/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt index b1163bf97146..aad5e34965eb 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/ti-tsc-adc.txt @@ -2,7 +2,12 @@ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Required properties: +- mfd + compatible: Should be + "ti,am3359-tscadc" for AM335x/AM437x SoCs + "ti,am654-tscadc", "ti,am3359-tscadc" for AM654 SoCs - child "tsc" + compatible: Should be "ti,am3359-tsc". ti,wires: Wires refer to application modes i.e. 4/5/8 wire touchscreen support on the platform. ti,x-plate-resistance: X plate resistance @@ -25,6 +30,9 @@ Required properties: AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7. XP = 0, XN = 1, YP = 2, YN = 3. - child "adc" + compatible: Should be + "ti,am3359-adc" for AM335x/AM437x SoCs + "ti,am654-adc", "ti,am3359-adc" for AM654 SoCs ti,adc-channels: List of analog inputs available for ADC. AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7. From aa6eaaa2ffada4a2fc6309e8e1a130e2284aea79 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 12 Feb 2019 17:52:37 +0530 Subject: [PATCH 472/506] arm64: dts: ti: k3-am65-mcu: Add ADC nodes TI AM654 SoC has two ADC instances in the MCU domain. Add DT nodes for the same. Signed-off-by: Vignesh R Signed-off-by: Tero Kristo --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 30 +++++++++++++++++++ .../arm64/boot/dts/ti/k3-am654-base-board.dts | 12 ++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 593f718e8fb5..6f7d2b316ded 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -57,4 +57,34 @@ #address-cells = <1>; #size-cells = <0>; }; + + tscadc0: tscadc@40200000 { + compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; + reg = <0x0 0x40200000 0x0 0x1000>; + interrupts = ; + clocks = <&k3_clks 0 2>; + assigned-clocks = <&k3_clks 0 2>; + assigned-clock-rates = <60000000>; + clock-names = "adc_tsc_fck"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am654-adc", "ti,am3359-adc"; + }; + }; + + tscadc1: tscadc@40210000 { + compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; + reg = <0x0 0x40210000 0x0 0x1000>; + interrupts = ; + clocks = <&k3_clks 1 2>; + assigned-clocks = <&k3_clks 1 2>; + assigned-clock-rates = <60000000>; + clock-names = "adc_tsc_fck"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am654-adc", "ti,am3359-adc"; + }; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index a70e9049ad83..cf1aa276a1ea 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -216,3 +216,15 @@ &usb0_phy { status = "disabled"; }; + +&tscadc0 { + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; From 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Fri, 15 Feb 2019 00:02:34 +0000 Subject: [PATCH 473/506] arm64: dts: rockchip: Add nanopi4 bluetooth Describe the Bluetooth portion of the Ampak combo module - this is either an AP6356S or an AP6212 depending on the board variant, but there are no relevant compatibility differences between the two. Signed-off-by: Robin Murphy Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-nanopi4.dtsi | 31 +++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index cf6cc4e7d315..d325e117287b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -218,7 +218,7 @@ rk808: pmic@1b { compatible = "rockchip,rk808"; reg = <0x1b>; - clock-output-names = "xin32k", "rk808-clkout2"; + clock-output-names = "xin32k", "rtc_clko_wifi"; #clock-cells = <1>; interrupt-parent = <&gpio1>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; @@ -501,7 +501,20 @@ }; }; - sdio-pwrseq { + sdio { + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + /* external pullup to VCC1V8_PMUPLL */ + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + wifi_reg_on_h: wifi-reg_on-h { rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; @@ -620,6 +633,20 @@ pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; }; &uart2 { From 78dd84ecd9ffafde3d7d7b061bd68caa2a3dfbc3 Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Wed, 13 Feb 2019 22:36:37 +0530 Subject: [PATCH 474/506] arm64: dts: rockchip: rockpro64 dts make regulator more readable rename dc12, vcc_sys, vcc1v8_pmu regulators and make it more redable as per the schematic of rk3399-rockpro64. Signed-off-by: Akash Gajjar Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-rockpro64.dts | 62 +++++++++---------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts index ae87a84327f2..d7361e091dc7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts @@ -25,15 +25,6 @@ #clock-cells = <0>; }; - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -83,6 +74,15 @@ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; }; + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + /* switched by pmic_sleep */ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { compatible = "regulator-fixed"; @@ -103,7 +103,7 @@ regulator-name = "vcc3v3_pcie"; regulator-always-on; regulator-boot-on; - vin-supply = <&dc_12v>; + vin-supply = <&vcc12v_dcin>; }; vcc3v3_sys: vcc3v3-sys { @@ -113,7 +113,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; + vin-supply = <&vcc5v0_sys>; }; /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ @@ -125,7 +125,7 @@ pinctrl-0 = <&vcc5v0_host_en>; regulator-name = "vcc5v0_host"; regulator-always-on; - vin-supply = <&vcc_sys>; + vin-supply = <&vcc5v0_sys>; }; vcc5v0_typec: vcc5v0-typec-regulator { @@ -136,17 +136,17 @@ pinctrl-0 = <&vcc5v0_typec_en>; regulator-name = "vcc5v0_typec"; regulator-always-on; - vin-supply = <&vcc_sys>; + vin-supply = <&vcc5v0_sys>; }; - vcc_sys: vcc-sys { + vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; + regulator-name = "vcc5v0_sys"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; + vin-supply = <&vcc12v_dcin>; }; vdd_log: vdd-log { @@ -157,7 +157,7 @@ regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; + vin-supply = <&vcc5v0_sys>; }; }; @@ -235,18 +235,18 @@ rockchip,system-power-controller; wakeup-source; - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc1v8_pmu>; + vddio-supply = <&vcca_1v8>; regulators { vdd_center: DCDC_REG1 { @@ -316,8 +316,8 @@ }; }; - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; @@ -418,7 +418,7 @@ regulator-ramp-delay = <1000>; regulator-always-on; regulator-boot-on; - vin-supply = <&vcc_sys>; + vin-supply = <&vcc5v0_sys>; regulator-state-mem { regulator-off-in-suspend; @@ -437,7 +437,7 @@ regulator-ramp-delay = <1000>; regulator-always-on; regulator-boot-on; - vin-supply = <&vcc_sys>; + vin-supply = <&vcc5v0_sys>; regulator-state-mem { regulator-off-in-suspend; From c96bb6f9204830f5972021d01b1207fed1b77aa3 Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Wed, 13 Feb 2019 22:36:38 +0530 Subject: [PATCH 475/506] arm64: dts: rockchip: rockpro64 dts remove unused lcd-reset pinmux lcd panel pinmux is unused and the pin actually for something different, so removing it. Signed-off-by: Akash Gajjar Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts index d7361e091dc7..386da589ff36 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts @@ -527,12 +527,6 @@ }; }; - lcd-panel { - lcd_panel_reset: lcd-panel-reset { - rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - pcie { pcie_pwr_en: pcie-pwr-en { rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; From 6db644c79c8d45d73b56bc389aebd85fc3679beb Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Wed, 13 Feb 2019 22:36:40 +0530 Subject: [PATCH 476/506] arm64: dts: rockchip: rockpro64 dts add usb regulator vcc5v0_host and vcc5v0_typec is supplied by vcc5v0_usb and not vcc5v0_sys. add node for vcc5v0_usb fixed regulator. Signed-off-by: Akash Gajjar Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts index 386da589ff36..1f2394e0587d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts @@ -125,7 +125,7 @@ pinctrl-0 = <&vcc5v0_host_en>; regulator-name = "vcc5v0_host"; regulator-always-on; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc5v0_usb>; }; vcc5v0_typec: vcc5v0-typec-regulator { @@ -136,7 +136,7 @@ pinctrl-0 = <&vcc5v0_typec_en>; regulator-name = "vcc5v0_typec"; regulator-always-on; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc5v0_usb>; }; vcc5v0_sys: vcc5v0-sys { @@ -149,6 +149,16 @@ vin-supply = <&vcc12v_dcin>; }; + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; From 4bc4d6013b7f5a957465a22d2c7681f19a0c3e71 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Mon, 11 Feb 2019 02:04:39 +0800 Subject: [PATCH 477/506] arm64: dts: rockchip: fix rk3328-roc-cc gmac2io stability issues This patch is a port of the fix from commit 73e42e186699 ("arm64: dts: rockchip: fix rock64 gmac2io stability issues") As per that patch, enabling thresh dma mode force disables checksuming. This is necessary as tx checksuming does not work with packets larger than 1498. The rk3328-roc-cc board exhibits tx stability issues with large packets similar to rock64's issues. This patch resolves that issue. Signed-off-by: Peter Geis Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts index 99d0d9912950..33c44e857247 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -104,6 +104,7 @@ phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmiim1_pins>; + snps,force_thresh_dma_mode; snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; snps,reset-active-low; snps,reset-delays-us = <0 10000 50000>; From c72235c288c8cc55d33e257e05d3017c2daf1603 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 15 Feb 2019 10:26:48 +0530 Subject: [PATCH 478/506] arm64: dts: rockchip: Add on-board WiFi/BT support for Rock960 boards Add on-board WiFi/BT support for Rock960 boards such as Rock960 based on AP6356S and Ficus based on AP6354 wireless modules. Firmwares for the respective boards are available here: http://people.linaro.org/~manivannan.sadhasivam/rock960_wifi/ http://people.linaro.org/~manivannan.sadhasivam/ficus_wifi/ Signed-off-by: Manivannan Sadhasivam Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-rock960.dtsi | 95 ++++++++++++++++++- 1 file changed, 94 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi index fecb133b0ed2..e40e66e33a5e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi @@ -9,6 +9,15 @@ #include "rk3399-opp.dtsi" / { + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + vcc1v8_s0: vcc1v8-s0 { compatible = "regulator-fixed"; regulator-name = "vcc1v8_s0"; @@ -370,6 +379,20 @@ }; &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_bus1: sdmmc-bus1 { rockchip,pins = @@ -395,6 +418,26 @@ }; }; + sdio0 { + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + <2 20 RK_FUNC_1 &pcfg_pull_up_20ma>, + <2 21 RK_FUNC_1 &pcfg_pull_up_20ma>, + <2 22 RK_FUNC_1 &pcfg_pull_up_20ma>, + <2 23 RK_FUNC_1 &pcfg_pull_up_20ma>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = + <2 24 RK_FUNC_1 &pcfg_pull_up_20ma>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = + <2 25 RK_FUNC_1 &pcfg_pull_none_20ma>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = @@ -411,6 +454,19 @@ <1 14 RK_FUNC_GPIO &pcfg_pull_down>; }; }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm2 { @@ -421,6 +477,32 @@ status = "okay"; }; +&sdio0 { + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + &sdhci { bus-width = <8>; mmc-hs400-1_8v; @@ -447,8 +529,19 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + }; }; &uart2 { From 08585d21de9875a6064b350957faa0460a4c69a6 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Fri, 15 Feb 2019 12:58:39 -0600 Subject: [PATCH 479/506] arm64: dts: sdm845: Fixup dependency on RPMPD includes This patch fixes a dependency issue with the RPMPD dt bindings. This temporarily removes the include file and adds hardcoded values for the OPPs until the other changes full land. This will be addressed in 5.2. Fixes: 5b6f186f0abb ("arm64: dts: sdm845: Add rpmh powercontroller node") Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e4b69c74fe07..5308f1671824 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -2099,43 +2098,43 @@ compatible = "operating-points-v2"; rpmhpd_opp_ret: opp1 { - opp-level = ; + opp-level = <16>; }; rpmhpd_opp_min_svs: opp2 { - opp-level = ; + opp-level = <48>; }; rpmhpd_opp_low_svs: opp3 { - opp-level = ; + opp-level = <64>; }; rpmhpd_opp_svs: opp4 { - opp-level = ; + opp-level = <128>; }; rpmhpd_opp_svs_l1: opp5 { - opp-level = ; + opp-level = <192>; }; rpmhpd_opp_nom: opp6 { - opp-level = ; + opp-level = <256>; }; rpmhpd_opp_nom_l1: opp7 { - opp-level = ; + opp-level = <320>; }; rpmhpd_opp_nom_l2: opp8 { - opp-level = ; + opp-level = <336>; }; rpmhpd_opp_turbo: opp9 { - opp-level = ; + opp-level = <384>; }; rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; + opp-level = <416>; }; }; }; From 51b99b39052854fd7424a3e9d9c47abfde5a1c15 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Feb 2019 20:34:29 +0100 Subject: [PATCH 480/506] ARM: dts: rockchip: remove cap-mmc-highspeed from rk3188-bqedison2qc mmc1 node The mmc1 pins are used for SDIO with a wifi chip. The function mmc_sdio_switch_hs() only checks for MMC_CAP_SD_HIGHSPEED and not for MMC_CAP_MMC_HIGHSPEED, so cap-mmc-highspeed can be removed. Signed-off-by: Johan Jonker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-bqedison2qc.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index cc66abb22170..c8b62bbd6a4a 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -460,7 +460,6 @@ &mmc1 { bus-width = <4>; cap-sd-highspeed; - cap-mmc-highspeed; keep-power-in-suspend; mmc-pwrseq = <&sdio_pwrseq>; non-removable; From ccb01374a835ae4ee8c71f801ca20fc669cba6b8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 23 Jun 2018 10:29:53 +0530 Subject: [PATCH 481/506] arm64: dts: actions: Add interrupt properties to pinctrl node for S900 Add interrupt properties to pinctrl node for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij --- arch/arm64/boot/dts/actions/s900.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index 491ddccc9038..2bb8f298943f 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -253,6 +253,14 @@ gpio-controller; gpio-ranges = <&pinctrl 0 0 146>; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + , + ; }; timer: timer@e0228000 { From 782976299a76cc3e2dd974eed417f115732fc8b7 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 10 Aug 2018 15:21:09 +0530 Subject: [PATCH 482/506] arm64: dts: actions: Add Reset Controller support for S700 SoC Add reset controller property and bindings header for the Actions Semi S700 SoC DTS. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s700.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi index 192c7b39c8c1..43f3c6ea3511 100644 --- a/arch/arm64/boot/dts/actions/s700.dtsi +++ b/arch/arm64/boot/dts/actions/s700.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { compatible = "actions,s700"; @@ -172,6 +173,7 @@ reg = <0x0 0xe0168000 0x0 0x1000>; clocks = <&hosc>, <&losc>; #clock-cells = <1>; + #reset-cells = <1>; }; sps: power-controller@e01b0100 { From 7cac6c0cb32d0798a7a567d93833eef921f9fe6c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 10 Aug 2018 15:21:10 +0530 Subject: [PATCH 483/506] arm64: dts: actions: Add Reset Controller support for S900 SoC Add reset controller property and bindings header for the Actions Semi S900 SoC DTS. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s900.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index 2bb8f298943f..ca2391c07791 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { compatible = "actions,s900"; @@ -184,6 +185,7 @@ reg = <0x0 0xe0160000 0x0 0x1000>; clocks = <&hosc>, <&losc>; #clock-cells = <1>; + #reset-cells = <1>; }; i2c0: i2c@e0170000 { From 7cdf8446ed1de9522885f4ca874d29ef78c80a42 Mon Sep 17 00:00:00 2001 From: Saravanan Sekar Date: Thu, 15 Nov 2018 13:47:48 +0100 Subject: [PATCH 484/506] arm64: dts: actions: Add pinctrl node for Actions Semi S700 Add pinctrl nodes for Actions Semi S700 SoC Signed-off-by: Parthiban Nallathambi Signed-off-by: Saravanan Sekar Acked-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s700.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi index 43f3c6ea3511..e54a6e72507f 100644 --- a/arch/arm64/boot/dts/actions/s700.dtsi +++ b/arch/arm64/boot/dts/actions/s700.dtsi @@ -188,5 +188,21 @@ interrupts = ; interrupt-names = "timer1"; }; + + pinctrl: pinctrl@e01b0000 { + compatible = "actions,s700-pinctrl"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + clocks = <&cmu CLK_GPIO>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 136>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + ; + }; }; }; From 7cf0aacfa81c03aca34660a0132f7cb9aa510cb1 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Tue, 11 Dec 2018 09:04:46 +0100 Subject: [PATCH 485/506] arm64: dts: actions: s700: Add I2C controller nodes Add I2C controller nodes for Actions Semiconductor S700 SoC. Signed-off-by: Parthiban Nallathambi Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s700.dtsi | 40 +++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi index e54a6e72507f..ea12160b06cf 100644 --- a/arch/arm64/boot/dts/actions/s700.dtsi +++ b/arch/arm64/boot/dts/actions/s700.dtsi @@ -176,6 +176,46 @@ #reset-cells = <1>; }; + i2c0: i2c@e0170000 { + compatible = "actions,s700-i2c"; + reg = <0 0xe0170000 0 0x1000>; + clocks = <&cmu CLK_I2C0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e0174000 { + compatible = "actions,s700-i2c"; + reg = <0 0xe0174000 0 0x1000>; + clocks = <&cmu CLK_I2C1>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e0178000 { + compatible = "actions,s700-i2c"; + reg = <0 0xe0178000 0 0x1000>; + clocks = <&cmu CLK_I2C2>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e017c000 { + compatible = "actions,s700-i2c"; + reg = <0 0xe017c000 0 0x1000>; + clocks = <&cmu CLK_I2C3>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sps: power-controller@e01b0100 { compatible = "actions,s700-sps"; reg = <0x0 0xe01b0100 0x0 0x100>; From 9175a8116f452a515cea734c6fedee6788e6bc33 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Tue, 11 Dec 2018 09:04:48 +0100 Subject: [PATCH 486/506] arm64: dts: actions: s700-cubieboard7: Enable I2C0 and I2C1 Add pinctrl definitions for Actions Semiconductor S700 I2C controllers. Pinctrl definitions are only available for I2C0, I2C1 and I2C2. Enable I2C0 (PMIC), I2C1 (gyro, touchscreen) in cubieboard7. Signed-off-by: Parthiban Nallathambi Reviewed-by: Manivannan Sadhasivam Signed-off-by: Manivannan Sadhasivam --- .../boot/dts/actions/s700-cubieboard7.dts | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts index 28f3f4a0f7f0..63e375cd9eb4 100644 --- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts +++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts @@ -30,6 +30,59 @@ }; }; +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_default>; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_default>; +}; + +&i2c2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_default>; +}; + +&pinctrl { + i2c0_default: i2c0_default { + pinmux { + groups = "i2c0_mfp"; + function = "i2c0"; + }; + pinconf { + pins = "i2c0_sclk", "i2c0_sdata"; + bias-pull-up; + }; + }; + + i2c1_default: i2c1_default { + pinmux { + groups = "i2c1_dummy"; + function = "i2c1"; + }; + pinconf { + pins = "i2c1_sclk", "i2c1_sdata"; + bias-pull-up; + }; + }; + + i2c2_default: i2c2_default { + pinmux { + groups = "i2c2_dummy"; + function = "i2c2"; + }; + pinconf { + pins = "i2c2_sclk", "i2c2_sdata"; + bias-pull-up; + }; + }; +}; + &timer { clocks = <&hosc>; }; From 5aed37a5cdef6453eb3bf307574e19e547ca0432 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 15 Feb 2019 12:51:50 +0100 Subject: [PATCH 487/506] ARM: dts: rockchip: add chosen node on veyron devices In order to use earlycon, the stdout-path property needs to be set in the chosen node. All veyron devices use uart2 for debugging, so add it to the core veyron dtsi. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index d8bf939a3aff..0bc2409f6903 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -10,6 +10,10 @@ #include "rk3288.dtsi" / { + chosen { + stdout-path = "serial2:115200n8"; + }; + /* * The default coreboot on veyron devices ignores memory@0 nodes * and would instead create another memory node. From 02260a619efe574d0f6c2a4420b8b76c6802294e Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 15 Feb 2019 12:25:39 -0300 Subject: [PATCH 488/506] arm64: dts: rockchip: Enable tsadc device on rock960 Enable the thermal sensor. This device also provides temperature shutdown protection. The shutdown value is set at 110C, as tested by the vendor. Signed-off-by: Ezequiel Garcia Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi index e40e66e33a5e..2927db4dda9d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi @@ -527,6 +527,13 @@ status = "okay"; }; +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + rockchip,hw-tshut-temp = <110000>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; From 5863dbe071caabe752ce6f9f6782fa03914527ab Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Wed, 13 Feb 2019 20:32:45 +0800 Subject: [PATCH 489/506] arm64: dts: sprd: Remove PMIC INTC irq trigger type The Spreadtrum PMIC INTC controller has no registers to set trigger type, since it is always high level trigger as default. So remove its child devices' irq trigger type setting and change #interrupt-cells to 1. Signed-off-by: Baolin Wang Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/sprd/sc2731.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/sprd/sc2731.dtsi b/arch/arm64/boot/dts/sprd/sc2731.dtsi index 82bd642d770b..f2f2aa50f66b 100644 --- a/arch/arm64/boot/dts/sprd/sc2731.dtsi +++ b/arch/arm64/boot/dts/sprd/sc2731.dtsi @@ -13,7 +13,7 @@ spi-max-frequency = <26000000>; interrupts = ; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; @@ -43,14 +43,14 @@ compatible = "sprd,sc27xx-rtc", "sprd,sc2731-rtc"; reg = <0x280>; interrupt-parent = <&sc2731_pmic>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <2>; }; pmic_eic: gpio@300 { compatible = "sprd,sc27xx-eic"; reg = <0x300>; interrupt-parent = <&sc2731_pmic>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <5>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -69,7 +69,7 @@ compatible = "sprd,sc27xx-adc", "sprd,sc2731-adc"; reg = <0x480>; interrupt-parent = <&sc2731_pmic>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; #io-channel-cells = <1>; hwlocks = <&hwlock 4>; }; From 640e2c51bdf227a540480c0f0e0d68e94113931c Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Wed, 13 Feb 2019 20:32:46 +0800 Subject: [PATCH 490/506] arm64: dts: sprd: Add ADC calibration support This patch adds phandles to the calibration cells provided by the Efuse device, which is used to calibrate the ADC channel scales. Signed-off-by: Baolin Wang Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/sprd/sc2731.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/sprd/sc2731.dtsi b/arch/arm64/boot/dts/sprd/sc2731.dtsi index f2f2aa50f66b..a2edc25936b3 100644 --- a/arch/arm64/boot/dts/sprd/sc2731.dtsi +++ b/arch/arm64/boot/dts/sprd/sc2731.dtsi @@ -63,6 +63,14 @@ #address-cells = <1>; #size-cells = <1>; hwlocks = <&hwlock 12>; + + adc_big_scale: calib@24 { + reg = <0x24 0x2>; + }; + + adc_small_scale: calib@26 { + reg = <0x26 0x2>; + }; }; pmic_adc: adc@480 { @@ -72,6 +80,8 @@ interrupts = <0>; #io-channel-cells = <1>; hwlocks = <&hwlock 4>; + nvmem-cell-names = "big_scale_calib", "small_scale_calib"; + nvmem-cells = <&adc_big_scale>, <&adc_small_scale>; }; vibrator@ec8 { From a47954095395412832ebe7a20023606b6375f153 Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Wed, 13 Feb 2019 20:32:47 +0800 Subject: [PATCH 491/506] arm64: dts: sprd: Add SC2731 charger device Add charger device node and related battery node for SC2731 PMIC. Signed-off-by: Baolin Wang Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/sprd/sc2731.dtsi | 6 ++++++ arch/arm64/boot/dts/sprd/sp9860g-1h10.dts | 16 ++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/sprd/sc2731.dtsi b/arch/arm64/boot/dts/sprd/sc2731.dtsi index a2edc25936b3..dbf6242ef3b5 100644 --- a/arch/arm64/boot/dts/sprd/sc2731.dtsi +++ b/arch/arm64/boot/dts/sprd/sc2731.dtsi @@ -17,6 +17,12 @@ #address-cells = <1>; #size-cells = <0>; + charger@0 { + compatible = "sprd,sc2731-charger"; + reg = <0x0>; + monitored-battery = <&bat>; + }; + led-controller@200 { compatible = "sprd,sc27xx-bltc", "sprd,sc2731-bltc"; reg = <0x200>; diff --git a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts index 985ebb5d157e..6b95fd94cee3 100644 --- a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts +++ b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts @@ -39,6 +39,22 @@ #size-cells = <2>; ranges; }; + + bat: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <1900000>; + charge-term-current-microamp = <120000>; + constant_charge_voltage_max_microvolt = <4350000>; + internal-resistance-micro-ohms = <250000>; + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>, + <4022000 85>, <3983000 80>, <3949000 75>, + <3917000 70>, <3889000 65>, <3864000 60>, + <3835000 55>, <3805000 50>, <3787000 45>, + <3777000 40>, <3773000 35>, <3770000 30>, + <3765000 25>, <3752000 20>, <3724000 15>, + <3680000 10>, <3605000 5>, <3400000 0>; + }; }; &uart0 { From 02643475a8d3cd0b763d278c5fc5e60e190e685c Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Wed, 13 Feb 2019 20:32:48 +0800 Subject: [PATCH 492/506] arm64: dts: sprd: Add SC27XX fuel gauge device Add Spreadtrum SC27XX fuel gauge device node to calculate the battery capacity. Signed-off-by: Baolin Wang Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/sprd/sc2731.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/sprd/sc2731.dtsi b/arch/arm64/boot/dts/sprd/sc2731.dtsi index dbf6242ef3b5..4a79ddf0ef11 100644 --- a/arch/arm64/boot/dts/sprd/sc2731.dtsi +++ b/arch/arm64/boot/dts/sprd/sc2731.dtsi @@ -70,6 +70,11 @@ #size-cells = <1>; hwlocks = <&hwlock 12>; + fgu_calib: calib@6 { + reg = <0x6 0x2>; + bits = <0 9>; + }; + adc_big_scale: calib@24 { reg = <0x24 0x2>; }; @@ -90,6 +95,19 @@ nvmem-cells = <&adc_big_scale>, <&adc_small_scale>; }; + fgu@a00 { + compatible = "sprd,sc2731-fgu"; + reg = <0xa00>; + bat-detect-gpio = <&pmic_eic 9 GPIO_ACTIVE_HIGH>; + io-channels = <&pmic_adc 3>, <&pmic_adc 6>; + io-channel-names = "bat-temp", "charge-vol"; + monitored-battery = <&bat>; + nvmem-cell-names = "fgu_calib"; + nvmem-cells = <&fgu_calib>; + interrupt-parent = <&sc2731_pmic>; + interrupts = <4>; + }; + vibrator@ec8 { compatible = "sprd,sc27xx-vibrator", "sprd,sc2731-vibrator"; reg = <0xec8>; From 0419a75b1808dda225b17ba1509f195f23c0db88 Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Wed, 13 Feb 2019 20:32:49 +0800 Subject: [PATCH 493/506] arm64: dts: sprd: Remove wildcard compatible string Remove wildcard compatible string. Signed-off-by: Baolin Wang Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/sprd/sc2731.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/sprd/sc2731.dtsi b/arch/arm64/boot/dts/sprd/sc2731.dtsi index 4a79ddf0ef11..e15409f55f43 100644 --- a/arch/arm64/boot/dts/sprd/sc2731.dtsi +++ b/arch/arm64/boot/dts/sprd/sc2731.dtsi @@ -24,7 +24,7 @@ }; led-controller@200 { - compatible = "sprd,sc27xx-bltc", "sprd,sc2731-bltc"; + compatible = "sprd,sc2731-bltc"; reg = <0x200>; #address-cells = <1>; #size-cells = <0>; @@ -46,14 +46,14 @@ }; rtc@280 { - compatible = "sprd,sc27xx-rtc", "sprd,sc2731-rtc"; + compatible = "sprd,sc2731-rtc"; reg = <0x280>; interrupt-parent = <&sc2731_pmic>; interrupts = <2>; }; pmic_eic: gpio@300 { - compatible = "sprd,sc27xx-eic"; + compatible = "sprd,sc2731-eic"; reg = <0x300>; interrupt-parent = <&sc2731_pmic>; interrupts = <5>; @@ -64,7 +64,7 @@ }; efuse@380 { - compatible = "sprd,sc27xx-efuse", "sprd,sc2731-efuse"; + compatible = "sprd,sc2731-efuse"; reg = <0x380>; #address-cells = <1>; #size-cells = <1>; @@ -85,7 +85,7 @@ }; pmic_adc: adc@480 { - compatible = "sprd,sc27xx-adc", "sprd,sc2731-adc"; + compatible = "sprd,sc2731-adc"; reg = <0x480>; interrupt-parent = <&sc2731_pmic>; interrupts = <0>; @@ -109,12 +109,12 @@ }; vibrator@ec8 { - compatible = "sprd,sc27xx-vibrator", "sprd,sc2731-vibrator"; + compatible = "sprd,sc2731-vibrator"; reg = <0xec8>; }; regulators { - compatible = "sprd,sc27xx-regulator"; + compatible = "sprd,sc2731-regulator"; vddarm0: BUCK_CPU0 { regulator-name = "vddarm0"; From e653eaed97ac925553b7e0adaf0d65170bfd6ef0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 9 Feb 2019 00:05:57 +0100 Subject: [PATCH 494/506] ARM: dts: exynos: Enable ADC on Odroid HC1 Odroid HC1 uses the exynos5422-odroid-core.dtsi file as a base. All other Exynos5422 Odroids use the "common". The ADC node was defined only in the latter. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++ arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 5 ----- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index bf09eab90f8a..9b0bccb77be5 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -36,6 +36,11 @@ }; }; +&adc { + vdd-supply = <&ldo4_reg>; + status = "okay"; +}; + &bus_wcore { devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, <&nocp_mem1_0>, <&nocp_mem1_1>; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index b299e541cac0..5f195ad7e467 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -362,11 +362,6 @@ }; }; -&adc { - vdd-supply = <&ldo4_reg>; - status = "okay"; -}; - &hdmi { status = "okay"; ddc = <&i2c_2>; From a66352e005488ecb4b534ba1af58a9f671eba9b8 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 15 Feb 2019 11:36:50 +0100 Subject: [PATCH 495/506] ARM: dts: exynos: Add minimal clkout parameters to Exynos3250 PMU Add minimal parameters needed by the Exynos CLKOUT driver to Exynos3250 PMU node. This fixes the following warning on boot: exynos_clkout_init: failed to register clkout clock Fixes: d19bb397e19e ("ARM: dts: exynos: Update PMU node with CLKOUT related data") Cc: Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 608d17454179..5892a9f7622f 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -168,6 +168,9 @@ interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; + clock-names = "clkout8"; + clocks = <&cmu CLK_FIN_PLL>; + #clock-cells = <1>; }; mipi_phy: video-phy { From 8e0861fd7f83760209dff517b4c52acd7c1db4d9 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 15 Feb 2019 12:27:45 +0100 Subject: [PATCH 496/506] ARM: dts: exynos: Add stdout path property to Arndale board Replace bootargs and kernel console parameter with 'stdout-path' property in 'chosen' node to instruct kernel which serial driver should be used for the kernel console and logs. This allows to enable earlycon messages by adding just 'earlycon' parameter to kernel command line. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250-arndale.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index b44f03ef3b27..dc6fa6fe83f1 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -23,7 +23,7 @@ }; chosen { - bootargs = "console=ttySAC2,115200"; + stdout-path = "serial2:115200n8"; }; gpio_keys { From 4dc185ccc72974222948ccf2eb5fc889ea048fbd Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 18 Feb 2019 14:22:57 +0100 Subject: [PATCH 497/506] ARM: dts: exynos: Disable ARM PMU on Odroid XU3-lite ARM Performance Monitoring Units (PMUs) are permanently disabled in the Exynos5422 SoC version used on Odroid XU3-lite boards. Disable them in boards dtb to avoid confusing user and getting following warning on boot: hw-breakpoint: Failed to enable monitor mode on CPU 0 Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index 0db935f2b836..c19b5a51ca44 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -18,6 +18,14 @@ compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; }; +&arm_a7_pmu { + status = "disabled"; +}; + +&arm_a15_pmu { + status = "disabled"; +}; + &pwm { /* * PWM 0 -- fan From 885b005d232c67025e28e4ada1227248ce290f11 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Tue, 12 Feb 2019 19:03:41 +0100 Subject: [PATCH 498/506] ARM: dts: exynos: Add support for secondary DAI to Odroid XU3 This patch extends DAPM routing and adds secondary CPU DAI entry to support the secondary audio PCM interface on Odroid XU3. Signed-off-by: Sylwester Nawrocki Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi index e84544b220b9..51a843bd65ed 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi @@ -24,7 +24,9 @@ "Headphone Jack", "MICBIAS", "IN1", "Headphone Jack", "Speakers", "SPKL", - "Speakers", "SPKR"; + "Speakers", "SPKR", + "I2S Playback", "Mixer DAI TX", + "HiFi Playback", "Mixer DAI TX"; assigned-clocks = <&clock CLK_MOUT_EPLL>, <&clock CLK_MOUT_MAU_EPLL>, @@ -51,7 +53,7 @@ <196608000>; cpu { - sound-dai = <&i2s0 0>; + sound-dai = <&i2s0 0>, <&i2s0 1>; }; codec { sound-dai = <&hdmi>, <&max98090>; From 625c731d1b2af487fc6be10b9a505699c045813a Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Tue, 12 Feb 2019 19:03:42 +0100 Subject: [PATCH 499/506] ARM: dts: exynos: Add support for secondary DAI to Odroid XU4 This patch extends DAPM routing and adds secondary CPU DAI entry to support the secondary audio PCM interface on Odroid XU4. Signed-off-by: Sylwester Nawrocki Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu4.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index 122174ea9e0a..892d389d6d09 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -33,6 +33,8 @@ compatible = "samsung,odroid-xu3-audio"; model = "Odroid-XU4"; + samsung,audio-routing = "I2S Playback", "Mixer DAI TX"; + assigned-clocks = <&clock CLK_MOUT_EPLL>, <&clock CLK_MOUT_MAU_EPLL>, <&clock CLK_MOUT_USER_MAU_EPLL>, @@ -58,7 +60,7 @@ <196608000>; cpu { - sound-dai = <&i2s0 0>; + sound-dai = <&i2s0 0>, <&i2s0 1>; }; codec { From 6a3b25173cd4c6c2cd1ad6f1a3a0a85b488597ed Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 19 Feb 2019 17:12:47 +0100 Subject: [PATCH 500/506] arch: arm: dts: kirkwood-rd88f6281: Remove disabled marvell,dsa reference marvell,dsa properties has been removed from kirkwood-rd88f6281.dtsi while cleanuping the dsa binding, but the dsa reference in kirkwood-rd88f6281-z0.dts has been missed causing the following errors: arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:21.4-16: Warning (reg_format): /dsa/switch@0:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:23.5-15: Warning (reg_format): /dsa/switch@0/port@4:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/kirkwood-rd88f6281-z0.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' arch/arm/boot/dts/kirkwood-rd88f6281-z0.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/kirkwood-rd88f6281-z0.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:20.12-26.5: Warning (avoid_default_addr_size): /dsa/switch@0: Relying on default #address-cells value arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:20.12-26.5: Warning (avoid_default_addr_size): /dsa/switch@0: Relying on default #size-cells value arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:22.11-25.6: Warning (avoid_default_addr_size): /dsa/switch@0/port@4: Relying on default #address-cells value arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts:22.11-25.6: Warning (avoid_default_addr_size): /dsa/switch@0/port@4: Relying on default #size-cells value So remove the dsa reference too in order to fix this issue. Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts index a9fee2c2bcaf..9d88301daf0e 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts +++ b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts @@ -16,15 +16,6 @@ model = "Marvell RD88f6281 Reference design, with Z0 SoC"; compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; - dsa { - switch@0 { - reg = <0 0>; /* MDIO address 0, switch 0 in tree */ - port@4 { - reg = <4>; - label = "wan"; - }; - }; - }; }; ð1 { From e8acd8564b96480be21697ed93fbcc69a355ef9a Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 20 Feb 2019 17:25:14 +0200 Subject: [PATCH 501/506] ARM: dts: dra7: switch to use phy-gmii-sel Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index bb45cb7fc3b6..414f1cd68733 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -77,18 +77,18 @@ }; }; + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,dra7xx-phy-gmii-sel"; + reg = <0x554 0x4>; + #phy-cells = <1>; + }; + scm_conf_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; }; - phy_sel: cpsw-phy-sel@554 { - compatible = "ti,dra7xx-cpsw-phy-sel"; - reg= <0x554 0x4>; - reg-names = "gmii-sel"; - }; - dra7_pmx_core: pinmux@1400 { compatible = "ti,dra7-padconf", "pinctrl-single"; @@ -3099,7 +3099,6 @@ ; ranges = <0 0 0x4000>; syscon = <&scm_conf>; - cpsw-phy-sel = <&phy_sel>; status = "disabled"; davinci_mdio: mdio@1000 { @@ -3114,11 +3113,13 @@ cpsw_emac0: slave@200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1>; }; cpsw_emac1: slave@300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2>; }; }; }; From 837143940d895ddc55d6ab523aad3fd35375b816 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 20 Feb 2019 17:25:15 +0200 Subject: [PATCH 502/506] ARM: dts: dm814x: switch to use phy-gmii-sel Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 601c57afd4fe..413ae19dd5f0 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -343,6 +343,12 @@ #size-cells = <1>; ranges = <0 0 0x800>; + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,dm814-phy-gmii-sel"; + reg = <0x650 0x4>; + #phy-cells = <1>; + }; + scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; @@ -549,17 +555,14 @@ cpsw_emac0: slave@4a100200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1>; + }; cpsw_emac1: slave@4a100300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; - }; - - phy_sel: cpsw-phy-sel@48140650 { - compatible = "ti,am3352-cpsw-phy-sel"; - reg= <0x48140650 0x4>; - reg-names = "gmii-sel"; + phys = <&phy_gmii_sel 2>; }; }; From dab2da84d5db260d8b8edf450ccb67c5660dc5ee Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 20 Feb 2019 17:25:16 +0200 Subject: [PATCH 503/506] ARM: dts: am4372: switch to use phy-gmii-sel Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 17 +++++++++-------- arch/arm/boot/dts/am43x-epos-evm.dts | 5 +---- 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index ca0896f80248..85c6f4ff1824 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -280,12 +280,6 @@ #size-cells = <1>; ranges = <0 0 0x4000>; - phy_sel: cpsw-phy-sel@650 { - compatible = "ti,am43xx-cpsw-phy-sel"; - reg= <0x650 0x4>; - reg-names = "gmii-sel"; - }; - am43xx_pinmux: pinmux@800 { compatible = "ti,am437-padconf", "pinctrl-single"; @@ -300,11 +294,17 @@ }; scm_conf: scm_conf@0 { - compatible = "syscon"; + compatible = "syscon", "simple-bus"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,am43xx-phy-gmii-sel"; + reg = <0x650 0x4>; + #phy-cells = <2>; + }; + scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; @@ -555,7 +555,6 @@ cpts_clock_shift = <29>; ranges = <0 0 0x8000>; syscon = <&scm_conf>; - cpsw-phy-sel = <&phy_sel>; davinci_mdio: mdio@1000 { compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio"; @@ -572,11 +571,13 @@ cpsw_emac0: slave@200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 0>; }; cpsw_emac1: slave@300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 0>; }; }; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 4ea753b3ee43..9dfd80e3b76e 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -584,10 +584,7 @@ &cpsw_emac0 { phy-handle = <ðphy0>; phy-mode = "rmii"; -}; - -&phy_sel { - rmii-clock-ext; + phys = <&phy_gmii_sel 1 1>; }; &i2c0 { From fcfa0e84eaf71537cffd0749f115be7024556a7f Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 20 Feb 2019 17:25:17 +0200 Subject: [PATCH 504/506] ARM: dts: am335x: switch to use phy-gmii-sel Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos-ir2110.dts | 4 ---- arch/arm/boot/dts/am335x-baltos-ir3220.dts | 4 ---- arch/arm/boot/dts/am335x-baltos-ir5221.dts | 4 ---- arch/arm/boot/dts/am335x-chiliboard.dts | 4 ---- arch/arm/boot/dts/am335x-icev2.dts | 4 ---- arch/arm/boot/dts/am335x-igep0033.dtsi | 4 ---- arch/arm/boot/dts/am335x-lxm.dts | 4 ---- arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi | 5 ----- arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts | 5 ----- arch/arm/boot/dts/am335x-phycore-som.dtsi | 4 ---- arch/arm/boot/dts/am33xx-l4.dtsi | 15 ++++++++------- 11 files changed, 8 insertions(+), 49 deletions(-) diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts index 75de1e723303..50dcf1290ac6 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts @@ -72,7 +72,3 @@ dual_emac_res_vlan = <2>; phy-handle = <&phy1>; }; - -&phy_sel { - rmii-clock-ext = <1>; -}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts index 1b215c425c57..f3f1abd26470 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts @@ -114,7 +114,3 @@ dual_emac_res_vlan = <2>; phy-handle = <&phy1>; }; - -&phy_sel { - rmii-clock-ext = <1>; -}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts index 832ead864dc5..42f473f0ed77 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts @@ -133,10 +133,6 @@ phy-handle = <&phy1>; }; -&phy_sel { - rmii-clock-ext = <1>; -}; - &dcan1 { pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins>; diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts index b50d5d2e71ff..bffa5dce54ec 100644 --- a/arch/arm/boot/dts/am335x-chiliboard.dts +++ b/arch/arm/boot/dts/am335x-chiliboard.dts @@ -155,10 +155,6 @@ phy-mode = "rmii"; }; -&phy_sel { - rmii-clock-ext; -}; - /* USB */ &usb { status = "okay"; diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index f2005ecca74f..9ac775c71072 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -484,10 +484,6 @@ dual_emac; }; -&phy_sel { - rmii-clock-ext; -}; - &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index 55b4c94cfafb..cbd22f25de95 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -123,10 +123,6 @@ phy-mode = "rmii"; }; -&phy_sel { - rmii-clock-ext; -}; - &elm { status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts index 481edcfaf121..d0e8e720a4d6 100644 --- a/arch/arm/boot/dts/am335x-lxm.dts +++ b/arch/arm/boot/dts/am335x-lxm.dts @@ -328,10 +328,6 @@ dual_emac_res_vlan = <3>; }; -&phy_sel { - rmii-clock-ext; -}; - &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi index 14f781953475..cb5913a69837 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi @@ -159,11 +159,6 @@ status = "okay"; }; -&phy_sel { - reg= <0x44e10650 0xf5>; - rmii-clock-ext; -}; - &sham { status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts index 5a58efc0c874..e562ce40f290 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts @@ -446,11 +446,6 @@ dual_emac_res_vlan = <2>; }; -&phy_sel { - reg= <0x44e10650 0xf5>; - rmii-clock-ext; -}; - &sham { status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index 428a25e952b0..015adb626b03 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -100,10 +100,6 @@ status = "okay"; }; -&phy_sel { - rmii-clock-ext; -}; - /* I2C Busses */ &am33xx_pinmux { i2c0_pins: pinmux_i2c0 { diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index e957370f8aec..f459ec316a22 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -279,12 +279,6 @@ #pinctrl-cells = <1>; ranges = <0 0 0x2000>; - phy_sel: cpsw-phy-sel@650 { - compatible = "ti,am3352-cpsw-phy-sel"; - reg= <0x650 0x4>; - reg-names = "gmii-sel"; - }; - am33xx_pinmux: pinmux@800 { compatible = "pinctrl-single"; reg = <0x800 0x238>; @@ -300,6 +294,12 @@ #size-cells = <1>; ranges = <0 0 0x800>; + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,am3352-phy-gmii-sel"; + reg = <0x650 0x4>; + #phy-cells = <2>; + }; + scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; @@ -715,7 +715,6 @@ interrupts = <40 41 42 43>; ranges = <0 0 0x8000>; syscon = <&scm_conf>; - cpsw-phy-sel = <&phy_sel>; status = "disabled"; davinci_mdio: mdio@1000 { @@ -731,11 +730,13 @@ cpsw_emac0: slave@200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 1>; }; cpsw_emac1: slave@300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 1>; }; }; }; From bae2bf97939aebd74dfd8f0b76b4902a19e63eef Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 20 Feb 2019 17:25:18 +0200 Subject: [PATCH 505/506] dt-bindings: net: ti: deprecate cpsw-phy-sel bindings The cpsw-phy-sel driver was replaced with new PHY driver phy-gmii-sel, so deprecate cpsw-phy-sel bindings. Reviewed-by: Rob Herring Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/net/cpsw-phy-sel.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt b/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt index 764c0c79b43d..5d76f991c027 100644 --- a/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt +++ b/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt @@ -1,4 +1,4 @@ -TI CPSW Phy mode Selection Device Tree Bindings +TI CPSW Phy mode Selection Device Tree Bindings (DEPRECATED) ----------------------------------------------- Required properties: From a3238924a820c1d7c977b632b769f3b5690cba09 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 25 Feb 2019 19:42:52 +0100 Subject: [PATCH 506/506] ARM: dts: exynos: Fix max voltage for buck8 regulator on Odroid XU3/XU4 The maximum voltage value for buck8 regulator on Odroid XU3/XU4 boards is set too low. Increase it to the 2000mV as specified on the board schematic. So far the board worked fine, because of the bug in the PMIC driver, which used incorrect step value for that regulator. It interpreted the voltage value set by the bootloader as 1225mV and kept it unchanged. The regulator driver has been however fixed recently in the commit 56b5d4ea778c ("regulator: s2mps11: Fix steps for buck7, buck8 and LDO35"), what results in reading the proper buck8 value and forcing it to 1500mV on boot. This is not enough for proper board operation and results in eMMC errors during heavy IO traffic. Increasing maximum voltage value for buck8 restores original driver behavior and fixes eMMC issues. Signed-off-by: Marek Szyprowski Fixes: 86a2d2ac5e5d ("ARM: dts: Add dts file for Odroid XU3 board") Fixes: 56b5d4ea778c ("regulator: s2mps11: Fix steps for buck7, buck8 and LDO35") Cc: Signed-off-by: Krzysztof Kozlowski Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 9b0bccb77be5..25d95de15c9b 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -473,7 +473,7 @@ buck8_reg: BUCK8 { regulator-name = "vdd_1.8v_ldo"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; + regulator-max-microvolt = <2000000>; regulator-always-on; regulator-boot-on; };