drm/gk104/fb/ram: make use of training data provided by vbios
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
Родитель
43b6b2029e
Коммит
6b07c6cfd1
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@ -29,6 +29,8 @@
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#include <subdev/bios/init.h>
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#include <subdev/bios/rammap.h>
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#include <subdev/bios/timing.h>
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#include <subdev/bios/M0205.h>
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#include <subdev/bios/M0209.h>
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#include <subdev/clock.h>
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#include <subdev/clock/pll.h>
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@ -1130,24 +1132,147 @@ nve0_ram_tidy(struct nouveau_fb *pfb)
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ram_exec(fuc, false);
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}
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struct nve0_ram_train {
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u16 mask;
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struct nvbios_M0209S remap;
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struct nvbios_M0209S type00;
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struct nvbios_M0209S type01;
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struct nvbios_M0209S type04;
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struct nvbios_M0209S type06;
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struct nvbios_M0209S type07;
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struct nvbios_M0209S type08;
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struct nvbios_M0209S type09;
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};
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static int
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nve0_ram_train_type(struct nouveau_fb *pfb, int i, u8 ramcfg,
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struct nve0_ram_train *train)
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{
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struct nouveau_bios *bios = nouveau_bios(pfb);
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struct nvbios_M0205E M0205E;
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struct nvbios_M0205S M0205S;
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struct nvbios_M0209E M0209E;
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struct nvbios_M0209S *remap = &train->remap;
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struct nvbios_M0209S *value;
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u8 ver, hdr, cnt, len;
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u32 data;
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/* determine type of data for this index */
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if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E)))
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return -ENOENT;
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switch (M0205E.type) {
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case 0x00: value = &train->type00; break;
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case 0x01: value = &train->type01; break;
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case 0x04: value = &train->type04; break;
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case 0x06: value = &train->type06; break;
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case 0x07: value = &train->type07; break;
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case 0x08: value = &train->type08; break;
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case 0x09: value = &train->type09; break;
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default:
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return 0;
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}
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/* training data index determined by ramcfg strap */
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if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S)))
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return -EINVAL;
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i = M0205S.data;
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/* training data format information */
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if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E)))
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return -EINVAL;
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/* ... and the raw data */
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if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value)))
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return -EINVAL;
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if (M0209E.v02_07 == 2) {
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/* of course! why wouldn't we have a pointer to another entry
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* in the same table, and use the first one as an array of
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* remap indices...
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*/
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if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr,
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remap)))
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(value->data); i++)
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value->data[i] = remap->data[value->data[i]];
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} else
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if (M0209E.v02_07 != 1)
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return -EINVAL;
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train->mask |= 1 << M0205E.type;
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return 0;
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}
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static int
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nve0_ram_train_init_0(struct nouveau_fb *pfb, struct nve0_ram_train *train)
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{
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int i, j;
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if ((train->mask & 0x03d3) != 0x03d3) {
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nv_warn(pfb, "missing link training data\n");
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return -EINVAL;
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}
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for (i = 0; i < 0x30; i++) {
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for (j = 0; j < 8; j += 4) {
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nv_wr32(pfb, 0x10f968 + j, 0x00000000 | (i << 8));
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nv_wr32(pfb, 0x10f920 + j, 0x00000000 |
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train->type08.data[i] << 4 |
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train->type06.data[i]);
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nv_wr32(pfb, 0x10f918 + j, train->type00.data[i]);
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nv_wr32(pfb, 0x10f920 + j, 0x00000100 |
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train->type09.data[i] << 4 |
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train->type07.data[i]);
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nv_wr32(pfb, 0x10f918 + j, train->type01.data[i]);
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}
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}
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for (j = 0; j < 8; j += 4) {
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for (i = 0; i < 0x100; i++) {
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nv_wr32(pfb, 0x10f968 + j, i);
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nv_wr32(pfb, 0x10f900 + j, train->type04.data[i]);
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}
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}
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return 0;
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}
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static int
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nve0_ram_train_init(struct nouveau_fb *pfb)
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{
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u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb));
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struct nve0_ram_train *train;
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int ret = -ENOMEM, i;
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if ((train = kzalloc(sizeof(*train), GFP_KERNEL))) {
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for (i = 0; i < 0x100; i++) {
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ret = nve0_ram_train_type(pfb, i, ramcfg, train);
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if (ret && ret != -ENOENT)
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break;
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}
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}
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switch (pfb->ram->type) {
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case NV_MEM_TYPE_GDDR5:
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ret = nve0_ram_train_init_0(pfb, train);
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break;
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default:
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ret = 0;
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break;
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}
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kfree(train);
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return ret;
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}
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int
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nve0_ram_init(struct nouveau_object *object)
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{
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struct nouveau_fb *pfb = (void *)object->parent;
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struct nve0_ram *ram = (void *)object;
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struct nouveau_bios *bios = nouveau_bios(pfb);
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static const u8 train0[] = {
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0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
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0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
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};
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static const u32 train1[] = {
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0x00000000, 0xffffffff,
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0x55555555, 0xaaaaaaaa,
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0x33333333, 0xcccccccc,
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0xf0f0f0f0, 0x0f0f0f0f,
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0x00ff00ff, 0xff00ff00,
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0x0000ffff, 0xffff0000,
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};
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u8 ver, hdr, cnt, len, snr, ssz;
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u32 data, save;
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int ret, i;
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@ -1190,37 +1315,7 @@ nve0_ram_init(struct nouveau_object *object)
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nv_wr32(pfb, 0x10ecc0, 0xffffffff);
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nv_mask(pfb, 0x10f160, 0x00000010, 0x00000010);
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switch (ram->base.type) {
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case NV_MEM_TYPE_GDDR5:
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for (i = 0; i < 0x30; i++) {
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nv_wr32(pfb, 0x10f968, 0x00000000 | (i << 8));
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nv_wr32(pfb, 0x10f920, 0x00000000 | train0[i % 12]);
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nv_wr32(pfb, 0x10f918, train1[i % 12]);
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nv_wr32(pfb, 0x10f920, 0x00000100 | train0[i % 12]);
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nv_wr32(pfb, 0x10f918, train1[i % 12]);
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nv_wr32(pfb, 0x10f96c, 0x00000000 | (i << 8));
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nv_wr32(pfb, 0x10f924, 0x00000000 | train0[i % 12]);
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nv_wr32(pfb, 0x10f91c, train1[i % 12]);
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nv_wr32(pfb, 0x10f924, 0x00000100 | train0[i % 12]);
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nv_wr32(pfb, 0x10f91c, train1[i % 12]);
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}
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for (i = 0; i < 0x100; i++) {
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nv_wr32(pfb, 0x10f968, i);
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nv_wr32(pfb, 0x10f900, train1[2 + (i & 1)]);
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}
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for (i = 0; i < 0x100; i++) {
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nv_wr32(pfb, 0x10f96c, i);
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nv_wr32(pfb, 0x10f904, train1[2 + (i & 1)]);
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}
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break;
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default:
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break;
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}
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return 0;
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return nve0_ram_train_init(pfb);
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}
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static int
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