PCI: imx6: Move PHY management functions together
Collect imx6_pcie_init_phy(), imx7d_pcie_wait_for_phy_pll_lock(), and imx6_setup_phy_mpll() earlier with other PHY-related code. No functional change intended. Link: https://lore.kernel.org/r/1657783869-19194-3-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
This commit is contained in:
Bjorn Helgaas
Родитель
79f14b6f1c
Коммит
6b1e989e49
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@ -296,6 +296,134 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
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return 0;
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}
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static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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{
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switch (imx6_pcie->drvdata->variant) {
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case IMX8MM:
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/*
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* The PHY initialization had been done in the PHY
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* driver, break here directly.
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*/
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break;
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case IMX8MQ:
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/*
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* TODO: Currently this code assumes external
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* oscillator is being used
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*/
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regmap_update_bits(imx6_pcie->iomuxc_gpr,
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imx6_pcie_grp_offset(imx6_pcie),
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IMX8MQ_GPR_PCIE_REF_USE_PAD,
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IMX8MQ_GPR_PCIE_REF_USE_PAD);
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/*
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* Regarding the datasheet, the PCIE_VPH is suggested
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* to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
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* VREG_BYPASS should be cleared to zero.
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*/
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if (imx6_pcie->vph &&
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regulator_get_voltage(imx6_pcie->vph) > 3000000)
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regmap_update_bits(imx6_pcie->iomuxc_gpr,
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imx6_pcie_grp_offset(imx6_pcie),
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IMX8MQ_GPR_PCIE_VREG_BYPASS,
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0);
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break;
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case IMX7D:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
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break;
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case IMX6SX:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6SX_GPR12_PCIE_RX_EQ_MASK,
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IMX6SX_GPR12_PCIE_RX_EQ_2);
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fallthrough;
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default:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
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/* configure constant input signal to the pcie ctrl and phy */
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_DEEMPH_GEN1,
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imx6_pcie->tx_deemph_gen1 << 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
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imx6_pcie->tx_deemph_gen2_3p5db << 6);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
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imx6_pcie->tx_deemph_gen2_6db << 12);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_SWING_FULL,
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imx6_pcie->tx_swing_full << 18);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_SWING_LOW,
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imx6_pcie->tx_swing_low << 25);
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break;
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}
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imx6_pcie_configure_type(imx6_pcie);
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}
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static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
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{
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u32 val;
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struct device *dev = imx6_pcie->pci->dev;
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if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
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IOMUXC_GPR22, val,
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val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
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PHY_PLL_LOCK_WAIT_USLEEP_MAX,
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PHY_PLL_LOCK_WAIT_TIMEOUT))
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dev_err(dev, "PCIe PLL lock timeout\n");
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}
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static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
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{
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unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
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int mult, div;
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u16 val;
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if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
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return 0;
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switch (phy_rate) {
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case 125000000:
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/*
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* The default settings of the MPLL are for a 125MHz input
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* clock, so no need to reconfigure anything in that case.
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*/
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return 0;
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case 100000000:
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mult = 25;
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div = 0;
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break;
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case 200000000:
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mult = 25;
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div = 1;
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break;
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default:
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dev_err(imx6_pcie->pci->dev,
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"Unsupported PHY reference clock rate %lu\n", phy_rate);
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return -EINVAL;
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}
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pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
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val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
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PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
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val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
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val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
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pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
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pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
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val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
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PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
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val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
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val |= PCIE_PHY_ATEOVRD_EN;
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pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
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return 0;
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}
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static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
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{
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u16 tmp;
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@ -500,19 +628,6 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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return ret;
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}
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static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
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{
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u32 val;
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struct device *dev = imx6_pcie->pci->dev;
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if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
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IOMUXC_GPR22, val,
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val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
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PHY_PLL_LOCK_WAIT_USLEEP_MAX,
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PHY_PLL_LOCK_WAIT_TIMEOUT))
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dev_err(dev, "PCIe PLL lock timeout\n");
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}
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static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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{
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struct dw_pcie *pci = imx6_pcie->pci;
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@ -635,121 +750,6 @@ err_pcie_phy:
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}
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}
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static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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{
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switch (imx6_pcie->drvdata->variant) {
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case IMX8MM:
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/*
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* The PHY initialization had been done in the PHY
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* driver, break here directly.
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*/
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break;
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case IMX8MQ:
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/*
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* TODO: Currently this code assumes external
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* oscillator is being used
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*/
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regmap_update_bits(imx6_pcie->iomuxc_gpr,
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imx6_pcie_grp_offset(imx6_pcie),
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IMX8MQ_GPR_PCIE_REF_USE_PAD,
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IMX8MQ_GPR_PCIE_REF_USE_PAD);
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/*
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* Regarding the datasheet, the PCIE_VPH is suggested
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* to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
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* VREG_BYPASS should be cleared to zero.
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*/
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if (imx6_pcie->vph &&
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regulator_get_voltage(imx6_pcie->vph) > 3000000)
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regmap_update_bits(imx6_pcie->iomuxc_gpr,
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imx6_pcie_grp_offset(imx6_pcie),
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IMX8MQ_GPR_PCIE_VREG_BYPASS,
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0);
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break;
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case IMX7D:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
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break;
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case IMX6SX:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6SX_GPR12_PCIE_RX_EQ_MASK,
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IMX6SX_GPR12_PCIE_RX_EQ_2);
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fallthrough;
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default:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
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/* configure constant input signal to the pcie ctrl and phy */
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_DEEMPH_GEN1,
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imx6_pcie->tx_deemph_gen1 << 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
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imx6_pcie->tx_deemph_gen2_3p5db << 6);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
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imx6_pcie->tx_deemph_gen2_6db << 12);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_SWING_FULL,
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imx6_pcie->tx_swing_full << 18);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_SWING_LOW,
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imx6_pcie->tx_swing_low << 25);
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break;
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}
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imx6_pcie_configure_type(imx6_pcie);
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}
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static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
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{
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unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
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int mult, div;
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u16 val;
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if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
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return 0;
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switch (phy_rate) {
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case 125000000:
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/*
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* The default settings of the MPLL are for a 125MHz input
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* clock, so no need to reconfigure anything in that case.
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*/
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return 0;
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case 100000000:
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mult = 25;
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div = 0;
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break;
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case 200000000:
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mult = 25;
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div = 1;
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break;
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default:
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dev_err(imx6_pcie->pci->dev,
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"Unsupported PHY reference clock rate %lu\n", phy_rate);
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return -EINVAL;
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}
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pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
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val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
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PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
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val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
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val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
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pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
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pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
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val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
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PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
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val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
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val |= PCIE_PHY_ATEOVRD_EN;
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pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
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return 0;
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}
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static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
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{
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struct dw_pcie *pci = imx6_pcie->pci;
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