Merge refs/heads/upstream from master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6.git
This commit is contained in:
Linus Torvalds
Коммит
6b39374a27
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@ -0,0 +1,352 @@
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Chelsio N210 10Gb Ethernet Network Controller
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Driver Release Notes for Linux
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Version 2.1.1
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June 20, 2005
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CONTENTS
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========
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INTRODUCTION
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FEATURES
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PERFORMANCE
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DRIVER MESSAGES
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KNOWN ISSUES
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SUPPORT
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INTRODUCTION
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============
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This document describes the Linux driver for Chelsio 10Gb Ethernet Network
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Controller. This driver supports the Chelsio N210 NIC and is backward
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compatible with the Chelsio N110 model 10Gb NICs.
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FEATURES
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========
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Adaptive Interrupts (adaptive-rx)
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---------------------------------
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This feature provides an adaptive algorithm that adjusts the interrupt
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coalescing parameters, allowing the driver to dynamically adapt the latency
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settings to achieve the highest performance during various types of network
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load.
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The interface used to control this feature is ethtool. Please see the
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ethtool manpage for additional usage information.
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By default, adaptive-rx is disabled.
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To enable adaptive-rx:
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ethtool -C <interface> adaptive-rx on
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To disable adaptive-rx, use ethtool:
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ethtool -C <interface> adaptive-rx off
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After disabling adaptive-rx, the timer latency value will be set to 50us.
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You may set the timer latency after disabling adaptive-rx:
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ethtool -C <interface> rx-usecs <microseconds>
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An example to set the timer latency value to 100us on eth0:
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ethtool -C eth0 rx-usecs 100
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You may also provide a timer latency value while disabling adpative-rx:
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||||
ethtool -C <interface> adaptive-rx off rx-usecs <microseconds>
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|
||||
If adaptive-rx is disabled and a timer latency value is specified, the timer
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will be set to the specified value until changed by the user or until
|
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adaptive-rx is enabled.
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|
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To view the status of the adaptive-rx and timer latency values:
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|
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ethtool -c <interface>
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|
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|
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TCP Segmentation Offloading (TSO) Support
|
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-----------------------------------------
|
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|
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This feature, also known as "large send", enables a system's protocol stack
|
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to offload portions of outbound TCP processing to a network interface card
|
||||
thereby reducing system CPU utilization and enhancing performance.
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|
||||
The interface used to control this feature is ethtool version 1.8 or higher.
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Please see the ethtool manpage for additional usage information.
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|
||||
By default, TSO is enabled.
|
||||
To disable TSO:
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||||
|
||||
ethtool -K <interface> tso off
|
||||
|
||||
To enable TSO:
|
||||
|
||||
ethtool -K <interface> tso on
|
||||
|
||||
To view the status of TSO:
|
||||
|
||||
ethtool -k <interface>
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||||
|
||||
|
||||
PERFORMANCE
|
||||
===========
|
||||
|
||||
The following information is provided as an example of how to change system
|
||||
parameters for "performance tuning" an what value to use. You may or may not
|
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want to change these system parameters, depending on your server/workstation
|
||||
application. Doing so is not warranted in any way by Chelsio Communications,
|
||||
and is done at "YOUR OWN RISK". Chelsio will not be held responsible for loss
|
||||
of data or damage to equipment.
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||||
|
||||
Your distribution may have a different way of doing things, or you may prefer
|
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a different method. These commands are shown only to provide an example of
|
||||
what to do and are by no means definitive.
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|
||||
Making any of the following system changes will only last until you reboot
|
||||
your system. You may want to write a script that runs at boot-up which
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includes the optimal settings for your system.
|
||||
|
||||
Setting PCI Latency Timer:
|
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setpci -d 1425:* 0x0c.l=0x0000F800
|
||||
|
||||
Disabling TCP timestamp:
|
||||
sysctl -w net.ipv4.tcp_timestamps=0
|
||||
|
||||
Disabling SACK:
|
||||
sysctl -w net.ipv4.tcp_sack=0
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|
||||
Setting large number of incoming connection requests:
|
||||
sysctl -w net.ipv4.tcp_max_syn_backlog=3000
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|
||||
Setting maximum receive socket buffer size:
|
||||
sysctl -w net.core.rmem_max=1024000
|
||||
|
||||
Setting maximum send socket buffer size:
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||||
sysctl -w net.core.wmem_max=1024000
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||||
|
||||
Set smp_affinity (on a multiprocessor system) to a single CPU:
|
||||
echo 1 > /proc/irq/<interrupt_number>/smp_affinity
|
||||
|
||||
Setting default receive socket buffer size:
|
||||
sysctl -w net.core.rmem_default=524287
|
||||
|
||||
Setting default send socket buffer size:
|
||||
sysctl -w net.core.wmem_default=524287
|
||||
|
||||
Setting maximum option memory buffers:
|
||||
sysctl -w net.core.optmem_max=524287
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||||
|
||||
Setting maximum backlog (# of unprocessed packets before kernel drops):
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||||
sysctl -w net.core.netdev_max_backlog=300000
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|
||||
Setting TCP read buffers (min/default/max):
|
||||
sysctl -w net.ipv4.tcp_rmem="10000000 10000000 10000000"
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|
||||
Setting TCP write buffers (min/pressure/max):
|
||||
sysctl -w net.ipv4.tcp_wmem="10000000 10000000 10000000"
|
||||
|
||||
Setting TCP buffer space (min/pressure/max):
|
||||
sysctl -w net.ipv4.tcp_mem="10000000 10000000 10000000"
|
||||
|
||||
TCP window size for single connections:
|
||||
The receive buffer (RX_WINDOW) size must be at least as large as the
|
||||
Bandwidth-Delay Product of the communication link between the sender and
|
||||
receiver. Due to the variations of RTT, you may want to increase the buffer
|
||||
size up to 2 times the Bandwidth-Delay Product. Reference page 289 of
|
||||
"TCP/IP Illustrated, Volume 1, The Protocols" by W. Richard Stevens.
|
||||
At 10Gb speeds, use the following formula:
|
||||
RX_WINDOW >= 1.25MBytes * RTT(in milliseconds)
|
||||
Example for RTT with 100us: RX_WINDOW = (1,250,000 * 0.1) = 125,000
|
||||
RX_WINDOW sizes of 256KB - 512KB should be sufficient.
|
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Setting the min, max, and default receive buffer (RX_WINDOW) size:
|
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sysctl -w net.ipv4.tcp_rmem="<min> <default> <max>"
|
||||
|
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TCP window size for multiple connections:
|
||||
The receive buffer (RX_WINDOW) size may be calculated the same as single
|
||||
connections, but should be divided by the number of connections. The
|
||||
smaller window prevents congestion and facilitates better pacing,
|
||||
especially if/when MAC level flow control does not work well or when it is
|
||||
not supported on the machine. Experimentation may be necessary to attain
|
||||
the correct value. This method is provided as a starting point fot the
|
||||
correct receive buffer size.
|
||||
Setting the min, max, and default receive buffer (RX_WINDOW) size is
|
||||
performed in the same manner as single connection.
|
||||
|
||||
|
||||
DRIVER MESSAGES
|
||||
===============
|
||||
|
||||
The following messages are the most common messages logged by syslog. These
|
||||
may be found in /var/log/messages.
|
||||
|
||||
Driver up:
|
||||
Chelsio Network Driver - version 2.1.1
|
||||
|
||||
NIC detected:
|
||||
eth#: Chelsio N210 1x10GBaseX NIC (rev #), PCIX 133MHz/64-bit
|
||||
|
||||
Link up:
|
||||
eth#: link is up at 10 Gbps, full duplex
|
||||
|
||||
Link down:
|
||||
eth#: link is down
|
||||
|
||||
|
||||
KNOWN ISSUES
|
||||
============
|
||||
|
||||
These issues have been identified during testing. The following information
|
||||
is provided as a workaround to the problem. In some cases, this problem is
|
||||
inherent to Linux or to a particular Linux Distribution and/or hardware
|
||||
platform.
|
||||
|
||||
1. Large number of TCP retransmits on a multiprocessor (SMP) system.
|
||||
|
||||
On a system with multiple CPUs, the interrupt (IRQ) for the network
|
||||
controller may be bound to more than one CPU. This will cause TCP
|
||||
retransmits if the packet data were to be split across different CPUs
|
||||
and re-assembled in a different order than expected.
|
||||
|
||||
To eliminate the TCP retransmits, set smp_affinity on the particular
|
||||
interrupt to a single CPU. You can locate the interrupt (IRQ) used on
|
||||
the N110/N210 by using ifconfig:
|
||||
ifconfig <dev_name> | grep Interrupt
|
||||
Set the smp_affinity to a single CPU:
|
||||
echo 1 > /proc/irq/<interrupt_number>/smp_affinity
|
||||
|
||||
It is highly suggested that you do not run the irqbalance daemon on your
|
||||
system, as this will change any smp_affinity setting you have applied.
|
||||
The irqbalance daemon runs on a 10 second interval and binds interrupts
|
||||
to the least loaded CPU determined by the daemon. To disable this daemon:
|
||||
chkconfig --level 2345 irqbalance off
|
||||
|
||||
By default, some Linux distributions enable the kernel feature,
|
||||
irqbalance, which performs the same function as the daemon. To disable
|
||||
this feature, add the following line to your bootloader:
|
||||
noirqbalance
|
||||
|
||||
Example using the Grub bootloader:
|
||||
title Red Hat Enterprise Linux AS (2.4.21-27.ELsmp)
|
||||
root (hd0,0)
|
||||
kernel /vmlinuz-2.4.21-27.ELsmp ro root=/dev/hda3 noirqbalance
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||||
initrd /initrd-2.4.21-27.ELsmp.img
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||||
|
||||
2. After running insmod, the driver is loaded and the incorrect network
|
||||
interface is brought up without running ifup.
|
||||
|
||||
When using 2.4.x kernels, including RHEL kernels, the Linux kernel
|
||||
invokes a script named "hotplug". This script is primarily used to
|
||||
automatically bring up USB devices when they are plugged in, however,
|
||||
the script also attempts to automatically bring up a network interface
|
||||
after loading the kernel module. The hotplug script does this by scanning
|
||||
the ifcfg-eth# config files in /etc/sysconfig/network-scripts, looking
|
||||
for HWADDR=<mac_address>.
|
||||
|
||||
If the hotplug script does not find the HWADDRR within any of the
|
||||
ifcfg-eth# files, it will bring up the device with the next available
|
||||
interface name. If this interface is already configured for a different
|
||||
network card, your new interface will have incorrect IP address and
|
||||
network settings.
|
||||
|
||||
To solve this issue, you can add the HWADDR=<mac_address> key to the
|
||||
interface config file of your network controller.
|
||||
|
||||
To disable this "hotplug" feature, you may add the driver (module name)
|
||||
to the "blacklist" file located in /etc/hotplug. It has been noted that
|
||||
this does not work for network devices because the net.agent script
|
||||
does not use the blacklist file. Simply remove, or rename, the net.agent
|
||||
script located in /etc/hotplug to disable this feature.
|
||||
|
||||
3. Transport Protocol (TP) hangs when running heavy multi-connection traffic
|
||||
on an AMD Opteron system with HyperTransport PCI-X Tunnel chipset.
|
||||
|
||||
If your AMD Opteron system uses the AMD-8131 HyperTransport PCI-X Tunnel
|
||||
chipset, you may experience the "133-Mhz Mode Split Completion Data
|
||||
Corruption" bug identified by AMD while using a 133Mhz PCI-X card on the
|
||||
bus PCI-X bus.
|
||||
|
||||
AMD states, "Under highly specific conditions, the AMD-8131 PCI-X Tunnel
|
||||
can provide stale data via split completion cycles to a PCI-X card that
|
||||
is operating at 133 Mhz", causing data corruption.
|
||||
|
||||
AMD's provides three workarounds for this problem, however, Chelsio
|
||||
recommends the first option for best performance with this bug:
|
||||
|
||||
For 133Mhz secondary bus operation, limit the transaction length and
|
||||
the number of outstanding transactions, via BIOS configuration
|
||||
programming of the PCI-X card, to the following:
|
||||
|
||||
Data Length (bytes): 1k
|
||||
Total allowed outstanding transactions: 2
|
||||
|
||||
Please refer to AMD 8131-HT/PCI-X Errata 26310 Rev 3.08 August 2004,
|
||||
section 56, "133-MHz Mode Split Completion Data Corruption" for more
|
||||
details with this bug and workarounds suggested by AMD.
|
||||
|
||||
It may be possible to work outside AMD's recommended PCI-X settings, try
|
||||
increasing the Data Length to 2k bytes for increased performance. If you
|
||||
have issues with these settings, please revert to the "safe" settings
|
||||
and duplicate the problem before submitting a bug or asking for support.
|
||||
|
||||
NOTE: The default setting on most systems is 8 outstanding transactions
|
||||
and 2k bytes data length.
|
||||
|
||||
4. On multiprocessor systems, it has been noted that an application which
|
||||
is handling 10Gb networking can switch between CPUs causing degraded
|
||||
and/or unstable performance.
|
||||
|
||||
If running on an SMP system and taking performance measurements, it
|
||||
is suggested you either run the latest netperf-2.4.0+ or use a binding
|
||||
tool such as Tim Hockin's procstate utilities (runon)
|
||||
<http://www.hockin.org/~thockin/procstate/>.
|
||||
|
||||
Binding netserver and netperf (or other applications) to particular
|
||||
CPUs will have a significant difference in performance measurements.
|
||||
You may need to experiment which CPU to bind the application to in
|
||||
order to achieve the best performance for your system.
|
||||
|
||||
If you are developing an application designed for 10Gb networking,
|
||||
please keep in mind you may want to look at kernel functions
|
||||
sched_setaffinity & sched_getaffinity to bind your application.
|
||||
|
||||
If you are just running user-space applications such as ftp, telnet,
|
||||
etc., you may want to try the runon tool provided by Tim Hockin's
|
||||
procstate utility. You could also try binding the interface to a
|
||||
particular CPU: runon 0 ifup eth0
|
||||
|
||||
|
||||
SUPPORT
|
||||
=======
|
||||
|
||||
If you have problems with the software or hardware, please contact our
|
||||
customer support team via email at support@chelsio.com or check our website
|
||||
at http://www.chelsio.com
|
||||
|
||||
===============================================================================
|
||||
|
||||
Chelsio Communications
|
||||
370 San Aleso Ave.
|
||||
Suite 100
|
||||
Sunnyvale, CA 94085
|
||||
http://www.chelsio.com
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License, version 2, as
|
||||
published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
|
||||
WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
|
||||
|
||||
Copyright (c) 2003-2005 Chelsio Communications. All rights reserved.
|
||||
|
||||
===============================================================================
|
||||
|
|
@ -2092,6 +2092,12 @@ M: support@simtec.co.uk
|
|||
W: http://www.simtec.co.uk/products/EB2410ITX/
|
||||
S: Supported
|
||||
|
||||
SIS 190 ETHERNET DRIVER
|
||||
P: Francois Romieu
|
||||
M: romieu@fr.zoreil.com
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
|
||||
SIS 5513 IDE CONTROLLER DRIVER
|
||||
P: Lionel Bouton
|
||||
M: Lionel.Bouton@inet6.fr
|
||||
|
|
|
|||
|
|
@ -1923,6 +1923,17 @@ config R8169_VLAN
|
|||
|
||||
If in doubt, say Y.
|
||||
|
||||
config SIS190
|
||||
tristate "SiS190 gigabit ethernet support"
|
||||
depends on PCI
|
||||
select CRC32
|
||||
select MII
|
||||
---help---
|
||||
Say Y here if you have a SiS 190 PCI Gigabit Ethernet adapter.
|
||||
|
||||
To compile this driver as a module, choose M here: the module
|
||||
will be called sis190. This is recommended.
|
||||
|
||||
config SKGE
|
||||
tristate "New SysKonnect GigaEthernet support (EXPERIMENTAL)"
|
||||
depends on PCI && EXPERIMENTAL
|
||||
|
|
@ -2093,6 +2104,25 @@ endmenu
|
|||
menu "Ethernet (10000 Mbit)"
|
||||
depends on !UML
|
||||
|
||||
config CHELSIO_T1
|
||||
tristate "Chelsio 10Gb Ethernet support"
|
||||
depends on PCI
|
||||
help
|
||||
This driver supports Chelsio N110 and N210 models 10Gb Ethernet
|
||||
cards. More information about adapter features and performance
|
||||
tuning is in <file:Documentation/networking/cxgb.txt>.
|
||||
|
||||
For general information about Chelsio and our products, visit
|
||||
our website at <http://www.chelsio.com>.
|
||||
|
||||
For customer support, please visit our customer support page at
|
||||
<http://www.chelsio.com/support.htm>.
|
||||
|
||||
Please send feedback to <linux-bugs@chelsio.com>.
|
||||
|
||||
To compile this driver as a module, choose M here: the module
|
||||
will be called cxgb.
|
||||
|
||||
config IXGB
|
||||
tristate "Intel(R) PRO/10GbE support"
|
||||
depends on PCI
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ endif
|
|||
obj-$(CONFIG_E1000) += e1000/
|
||||
obj-$(CONFIG_IBM_EMAC) += ibm_emac/
|
||||
obj-$(CONFIG_IXGB) += ixgb/
|
||||
obj-$(CONFIG_CHELSIO_T1) += chelsio/
|
||||
obj-$(CONFIG_BONDING) += bonding/
|
||||
obj-$(CONFIG_GIANFAR) += gianfar_driver.o
|
||||
|
||||
|
|
@ -42,6 +43,7 @@ obj-$(CONFIG_EEPRO100) += eepro100.o
|
|||
obj-$(CONFIG_E100) += e100.o
|
||||
obj-$(CONFIG_TLAN) += tlan.o
|
||||
obj-$(CONFIG_EPIC100) += epic100.o
|
||||
obj-$(CONFIG_SIS190) += sis190.o
|
||||
obj-$(CONFIG_SIS900) += sis900.o
|
||||
obj-$(CONFIG_YELLOWFIN) += yellowfin.o
|
||||
obj-$(CONFIG_ACENIC) += acenic.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,11 @@
|
|||
#
|
||||
# Chelsio 10Gb NIC driver for Linux.
|
||||
#
|
||||
|
||||
obj-$(CONFIG_CHELSIO_T1) += cxgb.o
|
||||
|
||||
EXTRA_CFLAGS += -I$(TOPDIR)/drivers/net/chelsio $(DEBUG_FLAGS)
|
||||
|
||||
|
||||
cxgb-objs := cxgb2.o espi.o pm3393.o sge.o subr.o mv88x201x.o
|
||||
|
||||
|
|
@ -0,0 +1,314 @@
|
|||
/*****************************************************************************
|
||||
* *
|
||||
* File: common.h *
|
||||
* $Revision: 1.21 $ *
|
||||
* $Date: 2005/06/22 00:43:25 $ *
|
||||
* Description: *
|
||||
* part of the Chelsio 10Gb Ethernet Driver. *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License, version 2, as *
|
||||
* published by the Free Software Foundation. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License along *
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
|
||||
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* http://www.chelsio.com *
|
||||
* *
|
||||
* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Maintainers: maintainers@chelsio.com *
|
||||
* *
|
||||
* Authors: Dimitrios Michailidis <dm@chelsio.com> *
|
||||
* Tina Yang <tainay@chelsio.com> *
|
||||
* Felix Marti <felix@chelsio.com> *
|
||||
* Scott Bardone <sbardone@chelsio.com> *
|
||||
* Kurt Ottaway <kottaway@chelsio.com> *
|
||||
* Frank DiMambro <frank@chelsio.com> *
|
||||
* *
|
||||
* History: *
|
||||
* *
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _CXGB_COMMON_H_
|
||||
#define _CXGB_COMMON_H_
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/mii.h>
|
||||
#include <linux/crc32.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/pci_ids.h>
|
||||
|
||||
#define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
|
||||
#define DRV_NAME "cxgb"
|
||||
#define DRV_VERSION "2.1.1"
|
||||
#define PFX DRV_NAME ": "
|
||||
|
||||
#define CH_ERR(fmt, ...) printk(KERN_ERR PFX fmt, ## __VA_ARGS__)
|
||||
#define CH_WARN(fmt, ...) printk(KERN_WARNING PFX fmt, ## __VA_ARGS__)
|
||||
#define CH_ALERT(fmt, ...) printk(KERN_ALERT PFX fmt, ## __VA_ARGS__)
|
||||
|
||||
#define CH_DEVICE(devid, ssid, idx) \
|
||||
{ PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
|
||||
|
||||
#define SUPPORTED_PAUSE (1 << 13)
|
||||
#define SUPPORTED_LOOPBACK (1 << 15)
|
||||
|
||||
#define ADVERTISED_PAUSE (1 << 13)
|
||||
#define ADVERTISED_ASYM_PAUSE (1 << 14)
|
||||
|
||||
typedef struct adapter adapter_t;
|
||||
|
||||
void t1_elmer0_ext_intr(adapter_t *adapter);
|
||||
void t1_link_changed(adapter_t *adapter, int port_id, int link_status,
|
||||
int speed, int duplex, int fc);
|
||||
|
||||
struct t1_rx_mode {
|
||||
struct net_device *dev;
|
||||
u32 idx;
|
||||
struct dev_mc_list *list;
|
||||
};
|
||||
|
||||
#define t1_rx_mode_promisc(rm) (rm->dev->flags & IFF_PROMISC)
|
||||
#define t1_rx_mode_allmulti(rm) (rm->dev->flags & IFF_ALLMULTI)
|
||||
#define t1_rx_mode_mc_cnt(rm) (rm->dev->mc_count)
|
||||
|
||||
static inline u8 *t1_get_next_mcaddr(struct t1_rx_mode *rm)
|
||||
{
|
||||
u8 *addr = 0;
|
||||
|
||||
if (rm->idx++ < rm->dev->mc_count) {
|
||||
addr = rm->list->dmi_addr;
|
||||
rm->list = rm->list->next;
|
||||
}
|
||||
return addr;
|
||||
}
|
||||
|
||||
#define MAX_NPORTS 4
|
||||
|
||||
#define SPEED_INVALID 0xffff
|
||||
#define DUPLEX_INVALID 0xff
|
||||
|
||||
enum {
|
||||
CHBT_BOARD_N110,
|
||||
CHBT_BOARD_N210
|
||||
};
|
||||
|
||||
enum {
|
||||
CHBT_TERM_T1,
|
||||
CHBT_TERM_T2
|
||||
};
|
||||
|
||||
enum {
|
||||
CHBT_MAC_PM3393,
|
||||
};
|
||||
|
||||
enum {
|
||||
CHBT_PHY_88X2010,
|
||||
};
|
||||
|
||||
enum {
|
||||
PAUSE_RX = 1 << 0,
|
||||
PAUSE_TX = 1 << 1,
|
||||
PAUSE_AUTONEG = 1 << 2
|
||||
};
|
||||
|
||||
/* Revisions of T1 chip */
|
||||
enum {
|
||||
TERM_T1A = 0,
|
||||
TERM_T1B = 1,
|
||||
TERM_T2 = 3
|
||||
};
|
||||
|
||||
struct sge_params {
|
||||
unsigned int cmdQ_size[2];
|
||||
unsigned int freelQ_size[2];
|
||||
unsigned int large_buf_capacity;
|
||||
unsigned int rx_coalesce_usecs;
|
||||
unsigned int last_rx_coalesce_raw;
|
||||
unsigned int default_rx_coalesce_usecs;
|
||||
unsigned int sample_interval_usecs;
|
||||
unsigned int coalesce_enable;
|
||||
unsigned int polling;
|
||||
};
|
||||
|
||||
struct chelsio_pci_params {
|
||||
unsigned short speed;
|
||||
unsigned char width;
|
||||
unsigned char is_pcix;
|
||||
};
|
||||
|
||||
struct adapter_params {
|
||||
struct sge_params sge;
|
||||
struct chelsio_pci_params pci;
|
||||
|
||||
const struct board_info *brd_info;
|
||||
|
||||
unsigned int nports; /* # of ethernet ports */
|
||||
unsigned int stats_update_period;
|
||||
unsigned short chip_revision;
|
||||
unsigned char chip_version;
|
||||
};
|
||||
|
||||
struct link_config {
|
||||
unsigned int supported; /* link capabilities */
|
||||
unsigned int advertising; /* advertised capabilities */
|
||||
unsigned short requested_speed; /* speed user has requested */
|
||||
unsigned short speed; /* actual link speed */
|
||||
unsigned char requested_duplex; /* duplex user has requested */
|
||||
unsigned char duplex; /* actual link duplex */
|
||||
unsigned char requested_fc; /* flow control user has requested */
|
||||
unsigned char fc; /* actual link flow control */
|
||||
unsigned char autoneg; /* autonegotiating? */
|
||||
};
|
||||
|
||||
struct cmac;
|
||||
struct cphy;
|
||||
|
||||
struct port_info {
|
||||
struct net_device *dev;
|
||||
struct cmac *mac;
|
||||
struct cphy *phy;
|
||||
struct link_config link_config;
|
||||
struct net_device_stats netstats;
|
||||
};
|
||||
|
||||
struct sge;
|
||||
struct peespi;
|
||||
|
||||
struct adapter {
|
||||
u8 *regs;
|
||||
struct pci_dev *pdev;
|
||||
unsigned long registered_device_map;
|
||||
unsigned long open_device_map;
|
||||
unsigned long flags;
|
||||
|
||||
const char *name;
|
||||
int msg_enable;
|
||||
u32 mmio_len;
|
||||
|
||||
struct work_struct ext_intr_handler_task;
|
||||
struct adapter_params params;
|
||||
|
||||
struct vlan_group *vlan_grp;
|
||||
|
||||
/* Terminator modules. */
|
||||
struct sge *sge;
|
||||
struct peespi *espi;
|
||||
|
||||
struct port_info port[MAX_NPORTS];
|
||||
struct work_struct stats_update_task;
|
||||
struct timer_list stats_update_timer;
|
||||
|
||||
struct semaphore mib_mutex;
|
||||
spinlock_t tpi_lock;
|
||||
spinlock_t work_lock;
|
||||
/* guards async operations */
|
||||
spinlock_t async_lock ____cacheline_aligned;
|
||||
u32 slow_intr_mask;
|
||||
};
|
||||
|
||||
enum { /* adapter flags */
|
||||
FULL_INIT_DONE = 1 << 0,
|
||||
TSO_CAPABLE = 1 << 2,
|
||||
TCP_CSUM_CAPABLE = 1 << 3,
|
||||
UDP_CSUM_CAPABLE = 1 << 4,
|
||||
VLAN_ACCEL_CAPABLE = 1 << 5,
|
||||
RX_CSUM_ENABLED = 1 << 6,
|
||||
};
|
||||
|
||||
struct mdio_ops;
|
||||
struct gmac;
|
||||
struct gphy;
|
||||
|
||||
struct board_info {
|
||||
unsigned char board;
|
||||
unsigned char port_number;
|
||||
unsigned long caps;
|
||||
unsigned char chip_term;
|
||||
unsigned char chip_mac;
|
||||
unsigned char chip_phy;
|
||||
unsigned int clock_core;
|
||||
unsigned int clock_mc3;
|
||||
unsigned int clock_mc4;
|
||||
unsigned int espi_nports;
|
||||
unsigned int clock_cspi;
|
||||
unsigned int clock_elmer0;
|
||||
unsigned char mdio_mdien;
|
||||
unsigned char mdio_mdiinv;
|
||||
unsigned char mdio_mdc;
|
||||
unsigned char mdio_phybaseaddr;
|
||||
struct gmac *gmac;
|
||||
struct gphy *gphy;
|
||||
struct mdio_ops *mdio_ops;
|
||||
const char *desc;
|
||||
};
|
||||
|
||||
extern struct pci_device_id t1_pci_tbl[];
|
||||
|
||||
static inline int adapter_matches_type(const adapter_t *adapter,
|
||||
int version, int revision)
|
||||
{
|
||||
return adapter->params.chip_version == version &&
|
||||
adapter->params.chip_revision == revision;
|
||||
}
|
||||
|
||||
#define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
|
||||
#define is_T2(adap) adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
|
||||
|
||||
/* Returns true if an adapter supports VLAN acceleration and TSO */
|
||||
static inline int vlan_tso_capable(const adapter_t *adapter)
|
||||
{
|
||||
return !t1_is_T1B(adapter);
|
||||
}
|
||||
|
||||
#define for_each_port(adapter, iter) \
|
||||
for (iter = 0; iter < (adapter)->params.nports; ++iter)
|
||||
|
||||
#define board_info(adapter) ((adapter)->params.brd_info)
|
||||
#define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
|
||||
|
||||
static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
|
||||
{
|
||||
return board_info(adap)->clock_core / 1000000;
|
||||
}
|
||||
|
||||
extern int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
|
||||
extern int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
|
||||
|
||||
extern void t1_interrupts_enable(adapter_t *adapter);
|
||||
extern void t1_interrupts_disable(adapter_t *adapter);
|
||||
extern void t1_interrupts_clear(adapter_t *adapter);
|
||||
extern int elmer0_ext_intr_handler(adapter_t *adapter);
|
||||
extern int t1_slow_intr_handler(adapter_t *adapter);
|
||||
|
||||
extern int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
|
||||
extern const struct board_info *t1_get_board_info(unsigned int board_id);
|
||||
extern const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
|
||||
unsigned short ssid);
|
||||
extern int t1_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
|
||||
extern int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
|
||||
struct adapter_params *p);
|
||||
extern int t1_init_hw_modules(adapter_t *adapter);
|
||||
extern int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
|
||||
extern void t1_free_sw_modules(adapter_t *adapter);
|
||||
extern void t1_fatal_err(adapter_t *adapter);
|
||||
|
||||
extern void t1_tp_set_udp_checksum_offload(adapter_t *adapter, int enable);
|
||||
extern void t1_tp_set_tcp_checksum_offload(adapter_t *adapter, int enable);
|
||||
extern void t1_tp_set_ip_checksum_offload(adapter_t *adapter, int enable);
|
||||
|
||||
#endif /* _CXGB_COMMON_H_ */
|
||||
|
|
@ -0,0 +1,148 @@
|
|||
/*****************************************************************************
|
||||
* *
|
||||
* File: cphy.h *
|
||||
* $Revision: 1.7 $ *
|
||||
* $Date: 2005/06/21 18:29:47 $ *
|
||||
* Description: *
|
||||
* part of the Chelsio 10Gb Ethernet Driver. *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License, version 2, as *
|
||||
* published by the Free Software Foundation. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License along *
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
|
||||
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* http://www.chelsio.com *
|
||||
* *
|
||||
* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Maintainers: maintainers@chelsio.com *
|
||||
* *
|
||||
* Authors: Dimitrios Michailidis <dm@chelsio.com> *
|
||||
* Tina Yang <tainay@chelsio.com> *
|
||||
* Felix Marti <felix@chelsio.com> *
|
||||
* Scott Bardone <sbardone@chelsio.com> *
|
||||
* Kurt Ottaway <kottaway@chelsio.com> *
|
||||
* Frank DiMambro <frank@chelsio.com> *
|
||||
* *
|
||||
* History: *
|
||||
* *
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _CXGB_CPHY_H_
|
||||
#define _CXGB_CPHY_H_
|
||||
|
||||
#include "common.h"
|
||||
|
||||
struct mdio_ops {
|
||||
void (*init)(adapter_t *adapter, const struct board_info *bi);
|
||||
int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int *val);
|
||||
int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int val);
|
||||
};
|
||||
|
||||
/* PHY interrupt types */
|
||||
enum {
|
||||
cphy_cause_link_change = 0x1,
|
||||
cphy_cause_error = 0x2
|
||||
};
|
||||
|
||||
struct cphy;
|
||||
|
||||
/* PHY operations */
|
||||
struct cphy_ops {
|
||||
void (*destroy)(struct cphy *);
|
||||
int (*reset)(struct cphy *, int wait);
|
||||
|
||||
int (*interrupt_enable)(struct cphy *);
|
||||
int (*interrupt_disable)(struct cphy *);
|
||||
int (*interrupt_clear)(struct cphy *);
|
||||
int (*interrupt_handler)(struct cphy *);
|
||||
|
||||
int (*autoneg_enable)(struct cphy *);
|
||||
int (*autoneg_disable)(struct cphy *);
|
||||
int (*autoneg_restart)(struct cphy *);
|
||||
|
||||
int (*advertise)(struct cphy *phy, unsigned int advertise_map);
|
||||
int (*set_loopback)(struct cphy *, int on);
|
||||
int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
|
||||
int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
|
||||
int *duplex, int *fc);
|
||||
};
|
||||
|
||||
/* A PHY instance */
|
||||
struct cphy {
|
||||
int addr; /* PHY address */
|
||||
adapter_t *adapter; /* associated adapter */
|
||||
struct cphy_ops *ops; /* PHY operations */
|
||||
int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int *val);
|
||||
int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int val);
|
||||
struct cphy_instance *instance;
|
||||
};
|
||||
|
||||
/* Convenience MDIO read/write wrappers */
|
||||
static inline int mdio_read(struct cphy *cphy, int mmd, int reg,
|
||||
unsigned int *valp)
|
||||
{
|
||||
return cphy->mdio_read(cphy->adapter, cphy->addr, mmd, reg, valp);
|
||||
}
|
||||
|
||||
static inline int mdio_write(struct cphy *cphy, int mmd, int reg,
|
||||
unsigned int val)
|
||||
{
|
||||
return cphy->mdio_write(cphy->adapter, cphy->addr, mmd, reg, val);
|
||||
}
|
||||
|
||||
static inline int simple_mdio_read(struct cphy *cphy, int reg,
|
||||
unsigned int *valp)
|
||||
{
|
||||
return mdio_read(cphy, 0, reg, valp);
|
||||
}
|
||||
|
||||
static inline int simple_mdio_write(struct cphy *cphy, int reg,
|
||||
unsigned int val)
|
||||
{
|
||||
return mdio_write(cphy, 0, reg, val);
|
||||
}
|
||||
|
||||
/* Convenience initializer */
|
||||
static inline void cphy_init(struct cphy *phy, adapter_t *adapter,
|
||||
int phy_addr, struct cphy_ops *phy_ops,
|
||||
struct mdio_ops *mdio_ops)
|
||||
{
|
||||
phy->adapter = adapter;
|
||||
phy->addr = phy_addr;
|
||||
phy->ops = phy_ops;
|
||||
if (mdio_ops) {
|
||||
phy->mdio_read = mdio_ops->read;
|
||||
phy->mdio_write = mdio_ops->write;
|
||||
}
|
||||
}
|
||||
|
||||
/* Operations of the PHY-instance factory */
|
||||
struct gphy {
|
||||
/* Construct a PHY instance with the given PHY address */
|
||||
struct cphy *(*create)(adapter_t *adapter, int phy_addr,
|
||||
struct mdio_ops *mdio_ops);
|
||||
|
||||
/*
|
||||
* Reset the PHY chip. This resets the whole PHY chip, not individual
|
||||
* ports.
|
||||
*/
|
||||
int (*reset)(adapter_t *adapter);
|
||||
};
|
||||
|
||||
extern struct gphy t1_mv88x201x_ops;
|
||||
extern struct gphy t1_dummy_phy_ops;
|
||||
|
||||
#endif /* _CXGB_CPHY_H_ */
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/*****************************************************************************
|
||||
* *
|
||||
* File: cpl5_cmd.h *
|
||||
* $Revision: 1.6 $ *
|
||||
* $Date: 2005/06/21 18:29:47 $ *
|
||||
* Description: *
|
||||
* part of the Chelsio 10Gb Ethernet Driver. *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License, version 2, as *
|
||||
* published by the Free Software Foundation. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License along *
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
|
||||
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* http://www.chelsio.com *
|
||||
* *
|
||||
* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Maintainers: maintainers@chelsio.com *
|
||||
* *
|
||||
* Authors: Dimitrios Michailidis <dm@chelsio.com> *
|
||||
* Tina Yang <tainay@chelsio.com> *
|
||||
* Felix Marti <felix@chelsio.com> *
|
||||
* Scott Bardone <sbardone@chelsio.com> *
|
||||
* Kurt Ottaway <kottaway@chelsio.com> *
|
||||
* Frank DiMambro <frank@chelsio.com> *
|
||||
* *
|
||||
* History: *
|
||||
* *
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _CXGB_CPL5_CMD_H_
|
||||
#define _CXGB_CPL5_CMD_H_
|
||||
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
|
||||
#error "Adjust your <asm/byteorder.h> defines"
|
||||
#endif
|
||||
|
||||
enum CPL_opcode {
|
||||
CPL_RX_PKT = 0xAD,
|
||||
CPL_TX_PKT = 0xB2,
|
||||
CPL_TX_PKT_LSO = 0xB6,
|
||||
};
|
||||
|
||||
enum { /* TX_PKT_LSO ethernet types */
|
||||
CPL_ETH_II,
|
||||
CPL_ETH_II_VLAN,
|
||||
CPL_ETH_802_3,
|
||||
CPL_ETH_802_3_VLAN
|
||||
};
|
||||
|
||||
struct cpl_rx_data {
|
||||
u32 rsvd0;
|
||||
u32 len;
|
||||
u32 seq;
|
||||
u16 urg;
|
||||
u8 rsvd1;
|
||||
u8 status;
|
||||
};
|
||||
|
||||
/*
|
||||
* We want this header's alignment to be no more stringent than 2-byte aligned.
|
||||
* All fields are u8 or u16 except for the length. However that field is not
|
||||
* used so we break it into 2 16-bit parts to easily meet our alignment needs.
|
||||
*/
|
||||
struct cpl_tx_pkt {
|
||||
u8 opcode;
|
||||
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||||
u8 iff:4;
|
||||
u8 ip_csum_dis:1;
|
||||
u8 l4_csum_dis:1;
|
||||
u8 vlan_valid:1;
|
||||
u8 rsvd:1;
|
||||
#else
|
||||
u8 rsvd:1;
|
||||
u8 vlan_valid:1;
|
||||
u8 l4_csum_dis:1;
|
||||
u8 ip_csum_dis:1;
|
||||
u8 iff:4;
|
||||
#endif
|
||||
u16 vlan;
|
||||
u16 len_hi;
|
||||
u16 len_lo;
|
||||
};
|
||||
|
||||
struct cpl_tx_pkt_lso {
|
||||
u8 opcode;
|
||||
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||||
u8 iff:4;
|
||||
u8 ip_csum_dis:1;
|
||||
u8 l4_csum_dis:1;
|
||||
u8 vlan_valid:1;
|
||||
u8 rsvd:1;
|
||||
#else
|
||||
u8 rsvd:1;
|
||||
u8 vlan_valid:1;
|
||||
u8 l4_csum_dis:1;
|
||||
u8 ip_csum_dis:1;
|
||||
u8 iff:4;
|
||||
#endif
|
||||
u16 vlan;
|
||||
u32 len;
|
||||
|
||||
u32 rsvd2;
|
||||
u8 rsvd3;
|
||||
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||||
u8 tcp_hdr_words:4;
|
||||
u8 ip_hdr_words:4;
|
||||
#else
|
||||
u8 ip_hdr_words:4;
|
||||
u8 tcp_hdr_words:4;
|
||||
#endif
|
||||
u16 eth_type_mss;
|
||||
};
|
||||
|
||||
struct cpl_rx_pkt {
|
||||
u8 opcode;
|
||||
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||||
u8 iff:4;
|
||||
u8 csum_valid:1;
|
||||
u8 bad_pkt:1;
|
||||
u8 vlan_valid:1;
|
||||
u8 rsvd:1;
|
||||
#else
|
||||
u8 rsvd:1;
|
||||
u8 vlan_valid:1;
|
||||
u8 bad_pkt:1;
|
||||
u8 csum_valid:1;
|
||||
u8 iff:4;
|
||||
#endif
|
||||
u16 csum;
|
||||
u16 vlan;
|
||||
u16 len;
|
||||
};
|
||||
|
||||
#endif /* _CXGB_CPL5_CMD_H_ */
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,151 @@
|
|||
/*****************************************************************************
|
||||
* *
|
||||
* File: elmer0.h *
|
||||
* $Revision: 1.6 $ *
|
||||
* $Date: 2005/06/21 22:49:43 $ *
|
||||
* Description: *
|
||||
* part of the Chelsio 10Gb Ethernet Driver. *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License, version 2, as *
|
||||
* published by the Free Software Foundation. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License along *
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
|
||||
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* http://www.chelsio.com *
|
||||
* *
|
||||
* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Maintainers: maintainers@chelsio.com *
|
||||
* *
|
||||
* Authors: Dimitrios Michailidis <dm@chelsio.com> *
|
||||
* Tina Yang <tainay@chelsio.com> *
|
||||
* Felix Marti <felix@chelsio.com> *
|
||||
* Scott Bardone <sbardone@chelsio.com> *
|
||||
* Kurt Ottaway <kottaway@chelsio.com> *
|
||||
* Frank DiMambro <frank@chelsio.com> *
|
||||
* *
|
||||
* History: *
|
||||
* *
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _CXGB_ELMER0_H_
|
||||
#define _CXGB_ELMER0_H_
|
||||
|
||||
/* ELMER0 registers */
|
||||
#define A_ELMER0_VERSION 0x100000
|
||||
#define A_ELMER0_PHY_CFG 0x100004
|
||||
#define A_ELMER0_INT_ENABLE 0x100008
|
||||
#define A_ELMER0_INT_CAUSE 0x10000c
|
||||
#define A_ELMER0_GPI_CFG 0x100010
|
||||
#define A_ELMER0_GPI_STAT 0x100014
|
||||
#define A_ELMER0_GPO 0x100018
|
||||
#define A_ELMER0_PORT0_MI1_CFG 0x400000
|
||||
|
||||
#define S_MI1_MDI_ENABLE 0
|
||||
#define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE)
|
||||
#define F_MI1_MDI_ENABLE V_MI1_MDI_ENABLE(1U)
|
||||
|
||||
#define S_MI1_MDI_INVERT 1
|
||||
#define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT)
|
||||
#define F_MI1_MDI_INVERT V_MI1_MDI_INVERT(1U)
|
||||
|
||||
#define S_MI1_PREAMBLE_ENABLE 2
|
||||
#define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE)
|
||||
#define F_MI1_PREAMBLE_ENABLE V_MI1_PREAMBLE_ENABLE(1U)
|
||||
|
||||
#define S_MI1_SOF 3
|
||||
#define M_MI1_SOF 0x3
|
||||
#define V_MI1_SOF(x) ((x) << S_MI1_SOF)
|
||||
#define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF)
|
||||
|
||||
#define S_MI1_CLK_DIV 5
|
||||
#define M_MI1_CLK_DIV 0xff
|
||||
#define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV)
|
||||
#define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV)
|
||||
|
||||
#define A_ELMER0_PORT0_MI1_ADDR 0x400004
|
||||
|
||||
#define S_MI1_REG_ADDR 0
|
||||
#define M_MI1_REG_ADDR 0x1f
|
||||
#define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR)
|
||||
#define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR)
|
||||
|
||||
#define S_MI1_PHY_ADDR 5
|
||||
#define M_MI1_PHY_ADDR 0x1f
|
||||
#define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR)
|
||||
#define G_MI1_PHY_ADDR(x) (((x) >> S_MI1_PHY_ADDR) & M_MI1_PHY_ADDR)
|
||||
|
||||
#define A_ELMER0_PORT0_MI1_DATA 0x400008
|
||||
|
||||
#define S_MI1_DATA 0
|
||||
#define M_MI1_DATA 0xffff
|
||||
#define V_MI1_DATA(x) ((x) << S_MI1_DATA)
|
||||
#define G_MI1_DATA(x) (((x) >> S_MI1_DATA) & M_MI1_DATA)
|
||||
|
||||
#define A_ELMER0_PORT0_MI1_OP 0x40000c
|
||||
|
||||
#define S_MI1_OP 0
|
||||
#define M_MI1_OP 0x3
|
||||
#define V_MI1_OP(x) ((x) << S_MI1_OP)
|
||||
#define G_MI1_OP(x) (((x) >> S_MI1_OP) & M_MI1_OP)
|
||||
|
||||
#define S_MI1_ADDR_AUTOINC 2
|
||||
#define V_MI1_ADDR_AUTOINC(x) ((x) << S_MI1_ADDR_AUTOINC)
|
||||
#define F_MI1_ADDR_AUTOINC V_MI1_ADDR_AUTOINC(1U)
|
||||
|
||||
#define S_MI1_OP_BUSY 31
|
||||
#define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY)
|
||||
#define F_MI1_OP_BUSY V_MI1_OP_BUSY(1U)
|
||||
|
||||
#define A_ELMER0_PORT1_MI1_CFG 0x500000
|
||||
#define A_ELMER0_PORT1_MI1_ADDR 0x500004
|
||||
#define A_ELMER0_PORT1_MI1_DATA 0x500008
|
||||
#define A_ELMER0_PORT1_MI1_OP 0x50000c
|
||||
#define A_ELMER0_PORT2_MI1_CFG 0x600000
|
||||
#define A_ELMER0_PORT2_MI1_ADDR 0x600004
|
||||
#define A_ELMER0_PORT2_MI1_DATA 0x600008
|
||||
#define A_ELMER0_PORT2_MI1_OP 0x60000c
|
||||
#define A_ELMER0_PORT3_MI1_CFG 0x700000
|
||||
#define A_ELMER0_PORT3_MI1_ADDR 0x700004
|
||||
#define A_ELMER0_PORT3_MI1_DATA 0x700008
|
||||
#define A_ELMER0_PORT3_MI1_OP 0x70000c
|
||||
|
||||
/* Simple bit definition for GPI and GP0 registers. */
|
||||
#define ELMER0_GP_BIT0 0x0001
|
||||
#define ELMER0_GP_BIT1 0x0002
|
||||
#define ELMER0_GP_BIT2 0x0004
|
||||
#define ELMER0_GP_BIT3 0x0008
|
||||
#define ELMER0_GP_BIT4 0x0010
|
||||
#define ELMER0_GP_BIT5 0x0020
|
||||
#define ELMER0_GP_BIT6 0x0040
|
||||
#define ELMER0_GP_BIT7 0x0080
|
||||
#define ELMER0_GP_BIT8 0x0100
|
||||
#define ELMER0_GP_BIT9 0x0200
|
||||
#define ELMER0_GP_BIT10 0x0400
|
||||
#define ELMER0_GP_BIT11 0x0800
|
||||
#define ELMER0_GP_BIT12 0x1000
|
||||
#define ELMER0_GP_BIT13 0x2000
|
||||
#define ELMER0_GP_BIT14 0x4000
|
||||
#define ELMER0_GP_BIT15 0x8000
|
||||
#define ELMER0_GP_BIT16 0x10000
|
||||
#define ELMER0_GP_BIT17 0x20000
|
||||
#define ELMER0_GP_BIT18 0x40000
|
||||
#define ELMER0_GP_BIT19 0x80000
|
||||
|
||||
#define MI1_OP_DIRECT_WRITE 1
|
||||
#define MI1_OP_DIRECT_READ 2
|
||||
|
||||
#define MI1_OP_INDIRECT_ADDRESS 0
|
||||
#define MI1_OP_INDIRECT_WRITE 1
|
||||
#define MI1_OP_INDIRECT_READ_INC 2
|
||||
#define MI1_OP_INDIRECT_READ 3
|
||||
|
||||
#endif /* _CXGB_ELMER0_H_ */
|
||||
|
|
@ -0,0 +1,346 @@
|
|||
/*****************************************************************************
|
||||
* *
|
||||
* File: espi.c *
|
||||
* $Revision: 1.14 $ *
|
||||
* $Date: 2005/05/14 00:59:32 $ *
|
||||
* Description: *
|
||||
* Ethernet SPI functionality. *
|
||||
* part of the Chelsio 10Gb Ethernet Driver. *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License, version 2, as *
|
||||
* published by the Free Software Foundation. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License along *
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
|
||||
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* http://www.chelsio.com *
|
||||
* *
|
||||
* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Maintainers: maintainers@chelsio.com *
|
||||
* *
|
||||
* Authors: Dimitrios Michailidis <dm@chelsio.com> *
|
||||
* Tina Yang <tainay@chelsio.com> *
|
||||
* Felix Marti <felix@chelsio.com> *
|
||||
* Scott Bardone <sbardone@chelsio.com> *
|
||||
* Kurt Ottaway <kottaway@chelsio.com> *
|
||||
* Frank DiMambro <frank@chelsio.com> *
|
||||
* *
|
||||
* History: *
|
||||
* *
|
||||
****************************************************************************/
|
||||
|
||||
#include "common.h"
|
||||
#include "regs.h"
|
||||
#include "espi.h"
|
||||
|
||||
struct peespi {
|
||||
adapter_t *adapter;
|
||||
struct espi_intr_counts intr_cnt;
|
||||
u32 misc_ctrl;
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
#define ESPI_INTR_MASK (F_DIP4ERR | F_RXDROP | F_TXDROP | F_RXOVERFLOW | \
|
||||
F_RAMPARITYERR | F_DIP2PARITYERR)
|
||||
#define MON_MASK (V_MONITORED_PORT_NUM(3) | F_MONITORED_DIRECTION \
|
||||
| F_MONITORED_INTERFACE)
|
||||
|
||||
#define TRICN_CNFG 14
|
||||
#define TRICN_CMD_READ 0x11
|
||||
#define TRICN_CMD_WRITE 0x21
|
||||
#define TRICN_CMD_ATTEMPTS 10
|
||||
|
||||
static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr,
|
||||
int ch_addr, int reg_offset, u32 wr_data)
|
||||
{
|
||||
int busy, attempts = TRICN_CMD_ATTEMPTS;
|
||||
|
||||
writel(V_WRITE_DATA(wr_data) |
|
||||
V_REGISTER_OFFSET(reg_offset) |
|
||||
V_CHANNEL_ADDR(ch_addr) | V_MODULE_ADDR(module_addr) |
|
||||
V_BUNDLE_ADDR(bundle_addr) |
|
||||
V_SPI4_COMMAND(TRICN_CMD_WRITE),
|
||||
adapter->regs + A_ESPI_CMD_ADDR);
|
||||
writel(0, adapter->regs + A_ESPI_GOSTAT);
|
||||
|
||||
do {
|
||||
busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY;
|
||||
} while (busy && --attempts);
|
||||
|
||||
if (busy)
|
||||
CH_ERR("%s: TRICN write timed out\n", adapter->name);
|
||||
|
||||
return busy;
|
||||
}
|
||||
|
||||
/* 1. Deassert rx_reset_core. */
|
||||
/* 2. Program TRICN_CNFG registers. */
|
||||
/* 3. Deassert rx_reset_link */
|
||||
static int tricn_init(adapter_t *adapter)
|
||||
{
|
||||
int i = 0;
|
||||
int sme = 1;
|
||||
int stat = 0;
|
||||
int timeout = 0;
|
||||
int is_ready = 0;
|
||||
int dynamic_deskew = 0;
|
||||
|
||||
if (dynamic_deskew)
|
||||
sme = 0;
|
||||
|
||||
|
||||
/* 1 */
|
||||
timeout=1000;
|
||||
do {
|
||||
stat = readl(adapter->regs + A_ESPI_RX_RESET);
|
||||
is_ready = (stat & 0x4);
|
||||
timeout--;
|
||||
udelay(5);
|
||||
} while (!is_ready || (timeout==0));
|
||||
writel(0x2, adapter->regs + A_ESPI_RX_RESET);
|
||||
if (timeout==0)
|
||||
{
|
||||
CH_ERR("ESPI : ERROR : Timeout tricn_init() \n");
|
||||
t1_fatal_err(adapter);
|
||||
}
|
||||
|
||||
/* 2 */
|
||||
if (sme) {
|
||||
tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81);
|
||||
tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81);
|
||||
tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81);
|
||||
}
|
||||
for (i=1; i<= 8; i++) tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1);
|
||||
for (i=1; i<= 2; i++) tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1);
|
||||
for (i=1; i<= 3; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);
|
||||
for (i=4; i<= 4; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xf1);
|
||||
for (i=5; i<= 5; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);
|
||||
for (i=6; i<= 6; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xf1);
|
||||
for (i=7; i<= 7; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0x80);
|
||||
for (i=8; i<= 8; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xf1);
|
||||
|
||||
/* 3 */
|
||||
writel(0x3, adapter->regs + A_ESPI_RX_RESET);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void t1_espi_intr_enable(struct peespi *espi)
|
||||
{
|
||||
u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
|
||||
|
||||
/*
|
||||
* Cannot enable ESPI interrupts on T1B because HW asserts the
|
||||
* interrupt incorrectly, namely the driver gets ESPI interrupts
|
||||
* but no data is actually dropped (can verify this reading the ESPI
|
||||
* drop registers). Also, once the ESPI interrupt is asserted it
|
||||
* cannot be cleared (HW bug).
|
||||
*/
|
||||
enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK;
|
||||
writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE);
|
||||
writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
|
||||
}
|
||||
|
||||
void t1_espi_intr_clear(struct peespi *espi)
|
||||
{
|
||||
writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS);
|
||||
writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE);
|
||||
}
|
||||
|
||||
void t1_espi_intr_disable(struct peespi *espi)
|
||||
{
|
||||
u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
|
||||
|
||||
writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE);
|
||||
writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
|
||||
}
|
||||
|
||||
int t1_espi_intr_handler(struct peespi *espi)
|
||||
{
|
||||
u32 cnt;
|
||||
u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
|
||||
|
||||
if (status & F_DIP4ERR)
|
||||
espi->intr_cnt.DIP4_err++;
|
||||
if (status & F_RXDROP)
|
||||
espi->intr_cnt.rx_drops++;
|
||||
if (status & F_TXDROP)
|
||||
espi->intr_cnt.tx_drops++;
|
||||
if (status & F_RXOVERFLOW)
|
||||
espi->intr_cnt.rx_ovflw++;
|
||||
if (status & F_RAMPARITYERR)
|
||||
espi->intr_cnt.parity_err++;
|
||||
if (status & F_DIP2PARITYERR) {
|
||||
espi->intr_cnt.DIP2_parity_err++;
|
||||
|
||||
/*
|
||||
* Must read the error count to clear the interrupt
|
||||
* that it causes.
|
||||
*/
|
||||
cnt = readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
|
||||
}
|
||||
|
||||
/*
|
||||
* For T1B we need to write 1 to clear ESPI interrupts. For T2+ we
|
||||
* write the status as is.
|
||||
*/
|
||||
if (status && t1_is_T1B(espi->adapter))
|
||||
status = 1;
|
||||
writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi)
|
||||
{
|
||||
return &espi->intr_cnt;
|
||||
}
|
||||
|
||||
static void espi_setup_for_pm3393(adapter_t *adapter)
|
||||
{
|
||||
u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
|
||||
|
||||
writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
|
||||
writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1);
|
||||
writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
|
||||
writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3);
|
||||
writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
|
||||
writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
|
||||
writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH);
|
||||
writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
|
||||
writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG);
|
||||
}
|
||||
|
||||
/* T2 Init part -- */
|
||||
/* 1. Set T_ESPI_MISCCTRL_ADDR */
|
||||
/* 2. Init ESPI registers. */
|
||||
/* 3. Init TriCN Hard Macro */
|
||||
int t1_espi_init(struct peespi *espi, int mac_type, int nports)
|
||||
{
|
||||
u32 cnt;
|
||||
|
||||
u32 status_enable_extra = 0;
|
||||
adapter_t *adapter = espi->adapter;
|
||||
u32 status, burstval = 0x800100;
|
||||
|
||||
/* Disable ESPI training. MACs that can handle it enable it below. */
|
||||
writel(0, adapter->regs + A_ESPI_TRAIN);
|
||||
|
||||
if (is_T2(adapter)) {
|
||||
writel(V_OUT_OF_SYNC_COUNT(4) |
|
||||
V_DIP2_PARITY_ERR_THRES(3) |
|
||||
V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL);
|
||||
if (nports == 4) {
|
||||
/* T204: maxburst1 = 0x40, maxburst2 = 0x20 */
|
||||
burstval = 0x200040;
|
||||
}
|
||||
}
|
||||
writel(burstval, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
|
||||
|
||||
switch (mac_type) {
|
||||
case CHBT_MAC_PM3393:
|
||||
espi_setup_for_pm3393(adapter);
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Make sure any pending interrupts from the SPI are
|
||||
* Cleared before enabling the interrupt.
|
||||
*/
|
||||
writel(ESPI_INTR_MASK, espi->adapter->regs + A_ESPI_INTR_ENABLE);
|
||||
status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
|
||||
if (status & F_DIP2PARITYERR) {
|
||||
cnt = readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
|
||||
}
|
||||
|
||||
/*
|
||||
* For T1B we need to write 1 to clear ESPI interrupts. For T2+ we
|
||||
* write the status as is.
|
||||
*/
|
||||
if (status && t1_is_T1B(espi->adapter))
|
||||
status = 1;
|
||||
writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS);
|
||||
|
||||
writel(status_enable_extra | F_RXSTATUSENABLE,
|
||||
adapter->regs + A_ESPI_FIFO_STATUS_ENABLE);
|
||||
|
||||
if (is_T2(adapter)) {
|
||||
tricn_init(adapter);
|
||||
/*
|
||||
* Always position the control at the 1st port egress IN
|
||||
* (sop,eop) counter to reduce PIOs for T/N210 workaround.
|
||||
*/
|
||||
espi->misc_ctrl = (readl(adapter->regs + A_ESPI_MISC_CONTROL)
|
||||
& ~MON_MASK) | (F_MONITORED_DIRECTION
|
||||
| F_MONITORED_INTERFACE);
|
||||
writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
|
||||
spin_lock_init(&espi->lock);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void t1_espi_destroy(struct peespi *espi)
|
||||
{
|
||||
kfree(espi);
|
||||
}
|
||||
|
||||
struct peespi *t1_espi_create(adapter_t *adapter)
|
||||
{
|
||||
struct peespi *espi = kmalloc(sizeof(*espi), GFP_KERNEL);
|
||||
|
||||
memset(espi, 0, sizeof(*espi));
|
||||
|
||||
if (espi)
|
||||
espi->adapter = adapter;
|
||||
return espi;
|
||||
}
|
||||
|
||||
void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
|
||||
{
|
||||
struct peespi *espi = adapter->espi;
|
||||
|
||||
if (!is_T2(adapter))
|
||||
return;
|
||||
spin_lock(&espi->lock);
|
||||
espi->misc_ctrl = (val & ~MON_MASK) |
|
||||
(espi->misc_ctrl & MON_MASK);
|
||||
writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
|
||||
spin_unlock(&espi->lock);
|
||||
}
|
||||
|
||||
u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait)
|
||||
{
|
||||
u32 sel;
|
||||
|
||||
struct peespi *espi = adapter->espi;
|
||||
|
||||
if (!is_T2(adapter))
|
||||
return 0;
|
||||
sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2);
|
||||
if (!wait) {
|
||||
if (!spin_trylock(&espi->lock))
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
spin_lock(&espi->lock);
|
||||
if ((sel != (espi->misc_ctrl & MON_MASK))) {
|
||||
writel(((espi->misc_ctrl & ~MON_MASK) | sel),
|
||||
adapter->regs + A_ESPI_MISC_CONTROL);
|
||||
sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
|
||||
writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
|
||||
}
|
||||
else
|
||||
sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
|
||||
spin_unlock(&espi->lock);
|
||||
return sel;
|
||||
}
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*****************************************************************************
|
||||
* *
|
||||
* File: espi.h *
|
||||
* $Revision: 1.7 $ *
|
||||
* $Date: 2005/06/21 18:29:47 $ *
|
||||
* Description: *
|
||||
* part of the Chelsio 10Gb Ethernet Driver. *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License, version 2, as *
|
||||
* published by the Free Software Foundation. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License along *
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
|
||||
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* http://www.chelsio.com *
|
||||
* *
|
||||
* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Maintainers: maintainers@chelsio.com *
|
||||
* *
|
||||
* Authors: Dimitrios Michailidis <dm@chelsio.com> *
|
||||
* Tina Yang <tainay@chelsio.com> *
|
||||
* Felix Marti <felix@chelsio.com> *
|
||||
* Scott Bardone <sbardone@chelsio.com> *
|
||||
* Kurt Ottaway <kottaway@chelsio.com> *
|
||||
* Frank DiMambro <frank@chelsio.com> *
|
||||
* *
|
||||
* History: *
|
||||
* *
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _CXGB_ESPI_H_
|
||||
#define _CXGB_ESPI_H_
|
||||
|
||||
#include "common.h"
|
||||
|
||||
struct espi_intr_counts {
|
||||
unsigned int DIP4_err;
|
||||
unsigned int rx_drops;
|
||||
unsigned int tx_drops;
|
||||
unsigned int rx_ovflw;
|
||||
unsigned int parity_err;
|
||||
unsigned int DIP2_parity_err;
|
||||
};
|
||||
|
||||
struct peespi;
|
||||
|
||||
struct peespi *t1_espi_create(adapter_t *adapter);
|
||||
void t1_espi_destroy(struct peespi *espi);
|
||||
int t1_espi_init(struct peespi *espi, int mac_type, int nports);
|
||||
|
||||
void t1_espi_intr_enable(struct peespi *);
|
||||
void t1_espi_intr_clear(struct peespi *);
|
||||
void t1_espi_intr_disable(struct peespi *);
|
||||
int t1_espi_intr_handler(struct peespi *);
|
||||
const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi);
|
||||
|
||||
void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val);
|
||||
u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait);
|
||||
|
||||
#endif /* _CXGB_ESPI_H_ */
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
/*****************************************************************************
|
||||
* *
|
||||
* File: gmac.h *
|
||||
* $Revision: 1.6 $ *
|
||||
* $Date: 2005/06/21 18:29:47 $ *
|
||||
* Description: *
|
||||
* Generic MAC functionality. *
|
||||
* part of the Chelsio 10Gb Ethernet Driver. *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License, version 2, as *
|
||||
* published by the Free Software Foundation. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License along *
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
|
||||
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* http://www.chelsio.com *
|
||||
* *
|
||||
* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Maintainers: maintainers@chelsio.com *
|
||||
* *
|
||||
* Authors: Dimitrios Michailidis <dm@chelsio.com> *
|
||||
* Tina Yang <tainay@chelsio.com> *
|
||||
* Felix Marti <felix@chelsio.com> *
|
||||
* Scott Bardone <sbardone@chelsio.com> *
|
||||
* Kurt Ottaway <kottaway@chelsio.com> *
|
||||
* Frank DiMambro <frank@chelsio.com> *
|
||||
* *
|
||||
* History: *
|
||||
* *
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _CXGB_GMAC_H_
|
||||
#define _CXGB_GMAC_H_
|
||||
|
||||
#include "common.h"
|
||||
|
||||
enum { MAC_STATS_UPDATE_FAST, MAC_STATS_UPDATE_FULL };
|
||||
enum { MAC_DIRECTION_RX = 1, MAC_DIRECTION_TX = 2 };
|
||||
|
||||
struct cmac_statistics {
|
||||
/* Transmit */
|
||||
u64 TxOctetsOK;
|
||||
u64 TxOctetsBad;
|
||||
u64 TxUnicastFramesOK;
|
||||
u64 TxMulticastFramesOK;
|
||||
u64 TxBroadcastFramesOK;
|
||||
u64 TxPauseFrames;
|
||||
u64 TxFramesWithDeferredXmissions;
|
||||
u64 TxLateCollisions;
|
||||
u64 TxTotalCollisions;
|
||||
u64 TxFramesAbortedDueToXSCollisions;
|
||||
u64 TxUnderrun;
|
||||
u64 TxLengthErrors;
|
||||
u64 TxInternalMACXmitError;
|
||||
u64 TxFramesWithExcessiveDeferral;
|
||||
u64 TxFCSErrors;
|
||||
|
||||
/* Receive */
|
||||
u64 RxOctetsOK;
|
||||
u64 RxOctetsBad;
|
||||
u64 RxUnicastFramesOK;
|
||||
u64 RxMulticastFramesOK;
|
||||
u64 RxBroadcastFramesOK;
|
||||
u64 RxPauseFrames;
|
||||
u64 RxFCSErrors;
|
||||
u64 RxAlignErrors;
|
||||
u64 RxSymbolErrors;
|
||||
u64 RxDataErrors;
|
||||
u64 RxSequenceErrors;
|
||||
u64 RxRuntErrors;
|
||||
u64 RxJabberErrors;
|
||||
u64 RxInternalMACRcvError;
|
||||
u64 RxInRangeLengthErrors;
|
||||
u64 RxOutOfRangeLengthField;
|
||||
u64 RxFrameTooLongErrors;
|
||||
};
|
||||
|
||||
struct cmac_ops {
|
||||
void (*destroy)(struct cmac *);
|
||||
int (*reset)(struct cmac *);
|
||||
int (*interrupt_enable)(struct cmac *);
|
||||
int (*interrupt_disable)(struct cmac *);
|
||||
int (*interrupt_clear)(struct cmac *);
|
||||
int (*interrupt_handler)(struct cmac *);
|
||||
|
||||
int (*enable)(struct cmac *, int);
|
||||
int (*disable)(struct cmac *, int);
|
||||
|
||||
int (*loopback_enable)(struct cmac *);
|
||||
int (*loopback_disable)(struct cmac *);
|
||||
|
||||
int (*set_mtu)(struct cmac *, int mtu);
|
||||
int (*set_rx_mode)(struct cmac *, struct t1_rx_mode *rm);
|
||||
|
||||
int (*set_speed_duplex_fc)(struct cmac *, int speed, int duplex, int fc);
|
||||
int (*get_speed_duplex_fc)(struct cmac *, int *speed, int *duplex,
|
||||
int *fc);
|
||||
|
||||
const struct cmac_statistics *(*statistics_update)(struct cmac *, int);
|
||||
|
||||
int (*macaddress_get)(struct cmac *, u8 mac_addr[6]);
|
||||
int (*macaddress_set)(struct cmac *, u8 mac_addr[6]);
|
||||
};
|
||||
|
||||
typedef struct _cmac_instance cmac_instance;
|
||||
|
||||
struct cmac {
|
||||
struct cmac_statistics stats;
|
||||
adapter_t *adapter;
|
||||
struct cmac_ops *ops;
|
||||
cmac_instance *instance;
|
||||
};
|
||||
|
||||
struct gmac {
|
||||
unsigned int stats_update_period;
|
||||
struct cmac *(*create)(adapter_t *adapter, int index);
|
||||
int (*reset)(adapter_t *);
|
||||
};
|
||||
|
||||
extern struct gmac t1_pm3393_ops;
|
||||
extern struct gmac t1_chelsio_mac_ops;
|
||||
extern struct gmac t1_vsc7321_ops;
|
||||
extern struct gmac t1_ixf1010_ops;
|
||||
extern struct gmac t1_dummy_mac_ops;
|
||||
|
||||
#endif /* _CXGB_GMAC_H_ */
|
||||
|
|
@ -0,0 +1,252 @@
|
|||
/*****************************************************************************
|
||||
* *
|
||||
* File: mv88x201x.c *
|
||||
* $Revision: 1.12 $ *
|
||||
* $Date: 2005/04/15 19:27:14 $ *
|
||||
* Description: *
|
||||
* Marvell PHY (mv88x201x) functionality. *
|
||||
* part of the Chelsio 10Gb Ethernet Driver. *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License, version 2, as *
|
||||
* published by the Free Software Foundation. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License along *
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
|
||||
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* http://www.chelsio.com *
|
||||
* *
|
||||
* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Maintainers: maintainers@chelsio.com *
|
||||
* *
|
||||
* Authors: Dimitrios Michailidis <dm@chelsio.com> *
|
||||
* Tina Yang <tainay@chelsio.com> *
|
||||
* Felix Marti <felix@chelsio.com> *
|
||||
* Scott Bardone <sbardone@chelsio.com> *
|
||||
* Kurt Ottaway <kottaway@chelsio.com> *
|
||||
* Frank DiMambro <frank@chelsio.com> *
|
||||
* *
|
||||
* History: *
|
||||
* *
|
||||
****************************************************************************/
|
||||
|
||||
#include "cphy.h"
|
||||
#include "elmer0.h"
|
||||
|
||||
/*
|
||||
* The 88x2010 Rev C. requires some link status registers * to be read
|
||||
* twice in order to get the right values. Future * revisions will fix
|
||||
* this problem and then this macro * can disappear.
|
||||
*/
|
||||
#define MV88x2010_LINK_STATUS_BUGS 1
|
||||
|
||||
static int led_init(struct cphy *cphy)
|
||||
{
|
||||
/* Setup the LED registers so we can turn on/off.
|
||||
* Writing these bits maps control to another
|
||||
* register. mmd(0x1) addr(0x7)
|
||||
*/
|
||||
mdio_write(cphy, 0x3, 0x8304, 0xdddd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int led_link(struct cphy *cphy, u32 do_enable)
|
||||
{
|
||||
u32 led = 0;
|
||||
#define LINK_ENABLE_BIT 0x1
|
||||
|
||||
mdio_read(cphy, 0x1, 0x7, &led);
|
||||
|
||||
if (do_enable & LINK_ENABLE_BIT) {
|
||||
led |= LINK_ENABLE_BIT;
|
||||
mdio_write(cphy, 0x1, 0x7, led);
|
||||
} else {
|
||||
led &= ~LINK_ENABLE_BIT;
|
||||
mdio_write(cphy, 0x1, 0x7, led);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Port Reset */
|
||||
static int mv88x201x_reset(struct cphy *cphy, int wait)
|
||||
{
|
||||
/* This can be done through registers. It is not required since
|
||||
* a full chip reset is used.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mv88x201x_interrupt_enable(struct cphy *cphy)
|
||||
{
|
||||
u32 elmer;
|
||||
|
||||
/* Enable PHY LASI interrupts. */
|
||||
mdio_write(cphy, 0x1, 0x9002, 0x1);
|
||||
|
||||
/* Enable Marvell interrupts through Elmer0. */
|
||||
t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
|
||||
elmer |= ELMER0_GP_BIT6;
|
||||
t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mv88x201x_interrupt_disable(struct cphy *cphy)
|
||||
{
|
||||
u32 elmer;
|
||||
|
||||
/* Disable PHY LASI interrupts. */
|
||||
mdio_write(cphy, 0x1, 0x9002, 0x0);
|
||||
|
||||
/* Disable Marvell interrupts through Elmer0. */
|
||||
t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
|
||||
elmer &= ~ELMER0_GP_BIT6;
|
||||
t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mv88x201x_interrupt_clear(struct cphy *cphy)
|
||||
{
|
||||
u32 elmer;
|
||||
u32 val;
|
||||
|
||||
#ifdef MV88x2010_LINK_STATUS_BUGS
|
||||
/* Required to read twice before clear takes affect. */
|
||||
mdio_read(cphy, 0x1, 0x9003, &val);
|
||||
mdio_read(cphy, 0x1, 0x9004, &val);
|
||||
mdio_read(cphy, 0x1, 0x9005, &val);
|
||||
|
||||
/* Read this register after the others above it else
|
||||
* the register doesn't clear correctly.
|
||||
*/
|
||||
mdio_read(cphy, 0x1, 0x1, &val);
|
||||
#endif
|
||||
|
||||
/* Clear link status. */
|
||||
mdio_read(cphy, 0x1, 0x1, &val);
|
||||
/* Clear PHY LASI interrupts. */
|
||||
mdio_read(cphy, 0x1, 0x9005, &val);
|
||||
|
||||
#ifdef MV88x2010_LINK_STATUS_BUGS
|
||||
/* Do it again. */
|
||||
mdio_read(cphy, 0x1, 0x9003, &val);
|
||||
mdio_read(cphy, 0x1, 0x9004, &val);
|
||||
#endif
|
||||
|
||||
/* Clear Marvell interrupts through Elmer0. */
|
||||
t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
|
||||
elmer |= ELMER0_GP_BIT6;
|
||||
t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mv88x201x_interrupt_handler(struct cphy *cphy)
|
||||
{
|
||||
/* Clear interrupts */
|
||||
mv88x201x_interrupt_clear(cphy);
|
||||
|
||||
/* We have only enabled link change interrupts and so
|
||||
* cphy_cause must be a link change interrupt.
|
||||
*/
|
||||
return cphy_cause_link_change;
|
||||
}
|
||||
|
||||
static int mv88x201x_set_loopback(struct cphy *cphy, int on)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mv88x201x_get_link_status(struct cphy *cphy, int *link_ok,
|
||||
int *speed, int *duplex, int *fc)
|
||||
{
|
||||
u32 val = 0;
|
||||
#define LINK_STATUS_BIT 0x4
|
||||
|
||||
if (link_ok) {
|
||||
/* Read link status. */
|
||||
mdio_read(cphy, 0x1, 0x1, &val);
|
||||
val &= LINK_STATUS_BIT;
|
||||
*link_ok = (val == LINK_STATUS_BIT);
|
||||
/* Turn on/off Link LED */
|
||||
led_link(cphy, *link_ok);
|
||||
}
|
||||
if (speed)
|
||||
*speed = SPEED_10000;
|
||||
if (duplex)
|
||||
*duplex = DUPLEX_FULL;
|
||||
if (fc)
|
||||
*fc = PAUSE_RX | PAUSE_TX;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mv88x201x_destroy(struct cphy *cphy)
|
||||
{
|
||||
kfree(cphy);
|
||||
}
|
||||
|
||||
static struct cphy_ops mv88x201x_ops = {
|
||||
.destroy = mv88x201x_destroy,
|
||||
.reset = mv88x201x_reset,
|
||||
.interrupt_enable = mv88x201x_interrupt_enable,
|
||||
.interrupt_disable = mv88x201x_interrupt_disable,
|
||||
.interrupt_clear = mv88x201x_interrupt_clear,
|
||||
.interrupt_handler = mv88x201x_interrupt_handler,
|
||||
.get_link_status = mv88x201x_get_link_status,
|
||||
.set_loopback = mv88x201x_set_loopback,
|
||||
};
|
||||
|
||||
static struct cphy *mv88x201x_phy_create(adapter_t *adapter, int phy_addr,
|
||||
struct mdio_ops *mdio_ops)
|
||||
{
|
||||
u32 val;
|
||||
struct cphy *cphy = kmalloc(sizeof(*cphy), GFP_KERNEL);
|
||||
|
||||
if (!cphy)
|
||||
return NULL;
|
||||
memset(cphy, 0, sizeof(*cphy));
|
||||
cphy_init(cphy, adapter, phy_addr, &mv88x201x_ops, mdio_ops);
|
||||
|
||||
/* Commands the PHY to enable XFP's clock. */
|
||||
mdio_read(cphy, 0x3, 0x8300, &val);
|
||||
mdio_write(cphy, 0x3, 0x8300, val | 1);
|
||||
|
||||
/* Clear link status. Required because of a bug in the PHY. */
|
||||
mdio_read(cphy, 0x1, 0x8, &val);
|
||||
mdio_read(cphy, 0x3, 0x8, &val);
|
||||
|
||||
/* Allows for Link,Ack LED turn on/off */
|
||||
led_init(cphy);
|
||||
return cphy;
|
||||
}
|
||||
|
||||
/* Chip Reset */
|
||||
static int mv88x201x_phy_reset(adapter_t *adapter)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
t1_tpi_read(adapter, A_ELMER0_GPO, &val);
|
||||
val &= ~4;
|
||||
t1_tpi_write(adapter, A_ELMER0_GPO, val);
|
||||
msleep(100);
|
||||
|
||||
t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);
|
||||
msleep(1000);
|
||||
|
||||
/* Now lets enable the Laser. Delay 100us */
|
||||
t1_tpi_read(adapter, A_ELMER0_GPO, &val);
|
||||
val |= 0x8000;
|
||||
t1_tpi_write(adapter, A_ELMER0_GPO, val);
|
||||
udelay(100);
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct gphy t1_mv88x201x_ops = {
|
||||
mv88x201x_phy_create,
|
||||
mv88x201x_phy_reset
|
||||
};
|
||||
|
|
@ -0,0 +1,826 @@
|
|||
/*****************************************************************************
|
||||
* *
|
||||
* File: pm3393.c *
|
||||
* $Revision: 1.16 $ *
|
||||
* $Date: 2005/05/14 00:59:32 $ *
|
||||
* Description: *
|
||||
* PMC/SIERRA (pm3393) MAC-PHY functionality. *
|
||||
* part of the Chelsio 10Gb Ethernet Driver. *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License, version 2, as *
|
||||
* published by the Free Software Foundation. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License along *
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
|
||||
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* http://www.chelsio.com *
|
||||
* *
|
||||
* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Maintainers: maintainers@chelsio.com *
|
||||
* *
|
||||
* Authors: Dimitrios Michailidis <dm@chelsio.com> *
|
||||
* Tina Yang <tainay@chelsio.com> *
|
||||
* Felix Marti <felix@chelsio.com> *
|
||||
* Scott Bardone <sbardone@chelsio.com> *
|
||||
* Kurt Ottaway <kottaway@chelsio.com> *
|
||||
* Frank DiMambro <frank@chelsio.com> *
|
||||
* *
|
||||
* History: *
|
||||
* *
|
||||
****************************************************************************/
|
||||
|
||||
#include "common.h"
|
||||
#include "regs.h"
|
||||
#include "gmac.h"
|
||||
#include "elmer0.h"
|
||||
#include "suni1x10gexp_regs.h"
|
||||
|
||||
/* 802.3ae 10Gb/s MDIO Manageable Device(MMD)
|
||||
*/
|
||||
enum {
|
||||
MMD_RESERVED,
|
||||
MMD_PMAPMD,
|
||||
MMD_WIS,
|
||||
MMD_PCS,
|
||||
MMD_PHY_XGXS, /* XGMII Extender Sublayer */
|
||||
MMD_DTE_XGXS,
|
||||
};
|
||||
|
||||
enum {
|
||||
PHY_XGXS_CTRL_1,
|
||||
PHY_XGXS_STATUS_1
|
||||
};
|
||||
|
||||
#define OFFSET(REG_ADDR) (REG_ADDR << 2)
|
||||
|
||||
/* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
|
||||
#define MAX_FRAME_SIZE 9600
|
||||
|
||||
#define IPG 12
|
||||
#define TXXG_CONF1_VAL ((IPG << SUNI1x10GEXP_BITOFF_TXXG_IPGT) | \
|
||||
SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN | SUNI1x10GEXP_BITMSK_TXXG_CRCEN | \
|
||||
SUNI1x10GEXP_BITMSK_TXXG_PADEN)
|
||||
#define RXXG_CONF1_VAL (SUNI1x10GEXP_BITMSK_RXXG_PUREP | 0x14 | \
|
||||
SUNI1x10GEXP_BITMSK_RXXG_FLCHK | SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP)
|
||||
|
||||
/* Update statistics every 15 minutes */
|
||||
#define STATS_TICK_SECS (15 * 60)
|
||||
|
||||
enum { /* RMON registers */
|
||||
RxOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW,
|
||||
RxUnicastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW,
|
||||
RxMulticastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW,
|
||||
RxBroadcastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW,
|
||||
RxPAUSEMACCtrlFramesReceived = SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW,
|
||||
RxFrameCheckSequenceErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW,
|
||||
RxFramesLostDueToInternalMACErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW,
|
||||
RxSymbolErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW,
|
||||
RxInRangeLengthErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW,
|
||||
RxFramesTooLongErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW,
|
||||
RxJabbers = SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW,
|
||||
RxFragments = SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW,
|
||||
RxUndersizedFrames = SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW,
|
||||
|
||||
TxOctetsTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW,
|
||||
TxFramesLostDueToInternalMACTransmissionError = SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW,
|
||||
TxTransmitSystemError = SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW,
|
||||
TxUnicastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW,
|
||||
TxMulticastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW,
|
||||
TxBroadcastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW,
|
||||
TxPAUSEMACCtrlFramesTransmitted = SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW
|
||||
};
|
||||
|
||||
struct _cmac_instance {
|
||||
u8 enabled;
|
||||
u8 fc;
|
||||
u8 mac_addr[6];
|
||||
};
|
||||
|
||||
static int pmread(struct cmac *cmac, u32 reg, u32 * data32)
|
||||
{
|
||||
t1_tpi_read(cmac->adapter, OFFSET(reg), data32);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pmwrite(struct cmac *cmac, u32 reg, u32 data32)
|
||||
{
|
||||
t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Port reset. */
|
||||
static int pm3393_reset(struct cmac *cmac)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable interrupts for the PM3393
|
||||
|
||||
1. Enable PM3393 BLOCK interrupts.
|
||||
2. Enable PM3393 Master Interrupt bit(INTE)
|
||||
3. Enable ELMER's PM3393 bit.
|
||||
4. Enable Terminator external interrupt.
|
||||
*/
|
||||
static int pm3393_interrupt_enable(struct cmac *cmac)
|
||||
{
|
||||
u32 pl_intr;
|
||||
|
||||
/* PM3393 - Enabling all hardware block interrupts.
|
||||
*/
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff);
|
||||
|
||||
/* Don't interrupt on statistics overflow, we are polling */
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
|
||||
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff);
|
||||
|
||||
/* PM3393 - Global interrupt enable
|
||||
*/
|
||||
/* TBD XXX Disable for now until we figure out why error interrupts keep asserting. */
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE,
|
||||
0 /*SUNI1x10GEXP_BITMSK_TOP_INTE */ );
|
||||
|
||||
/* TERMINATOR - PL_INTERUPTS_EXT */
|
||||
pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE);
|
||||
pl_intr |= F_PL_INTR_EXT;
|
||||
writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pm3393_interrupt_disable(struct cmac *cmac)
|
||||
{
|
||||
u32 elmer;
|
||||
|
||||
/* PM3393 - Enabling HW interrupt blocks. */
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);
|
||||
|
||||
/* PM3393 - Global interrupt enable */
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);
|
||||
|
||||
/* ELMER - External chip interrupts. */
|
||||
t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);
|
||||
elmer &= ~ELMER0_GP_BIT1;
|
||||
t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);
|
||||
|
||||
/* TERMINATOR - PL_INTERUPTS_EXT */
|
||||
/* DO NOT DISABLE TERMINATOR's EXTERNAL INTERRUPTS. ANOTHER CHIP
|
||||
* COULD WANT THEM ENABLED. We disable PM3393 at the ELMER level.
|
||||
*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pm3393_interrupt_clear(struct cmac *cmac)
|
||||
{
|
||||
u32 elmer;
|
||||
u32 pl_intr;
|
||||
u32 val32;
|
||||
|
||||
/* PM3393 - Clearing HW interrupt blocks. Note, this assumes
|
||||
* bit WCIMODE=0 for a clear-on-read.
|
||||
*/
|
||||
pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);
|
||||
pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);
|
||||
pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);
|
||||
pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);
|
||||
pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);
|
||||
pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);
|
||||
pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);
|
||||
pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);
|
||||
pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);
|
||||
pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);
|
||||
pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);
|
||||
pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,
|
||||
&val32);
|
||||
pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);
|
||||
pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);
|
||||
|
||||
/* PM3393 - Global interrupt status
|
||||
*/
|
||||
pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);
|
||||
|
||||
/* ELMER - External chip interrupts.
|
||||
*/
|
||||
t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);
|
||||
elmer |= ELMER0_GP_BIT1;
|
||||
t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);
|
||||
|
||||
/* TERMINATOR - PL_INTERUPTS_EXT
|
||||
*/
|
||||
pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE);
|
||||
pl_intr |= F_PL_INTR_EXT;
|
||||
writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Interrupt handler */
|
||||
static int pm3393_interrupt_handler(struct cmac *cmac)
|
||||
{
|
||||
u32 master_intr_status;
|
||||
/*
|
||||
1. Read master interrupt register.
|
||||
2. Read BLOCK's interrupt status registers.
|
||||
3. Handle BLOCK interrupts.
|
||||
*/
|
||||
/* Read the master interrupt status register. */
|
||||
pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,
|
||||
&master_intr_status);
|
||||
|
||||
/* TBD XXX Lets just clear everything for now */
|
||||
pm3393_interrupt_clear(cmac);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pm3393_enable(struct cmac *cmac, int which)
|
||||
{
|
||||
if (which & MAC_DIRECTION_RX)
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1,
|
||||
(RXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_RXXG_RXEN));
|
||||
|
||||
if (which & MAC_DIRECTION_TX) {
|
||||
u32 val = TXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_TXXG_TXEN0;
|
||||
|
||||
if (cmac->instance->fc & PAUSE_RX)
|
||||
val |= SUNI1x10GEXP_BITMSK_TXXG_FCRX;
|
||||
if (cmac->instance->fc & PAUSE_TX)
|
||||
val |= SUNI1x10GEXP_BITMSK_TXXG_FCTX;
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val);
|
||||
}
|
||||
|
||||
cmac->instance->enabled |= which;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pm3393_enable_port(struct cmac *cmac, int which)
|
||||
{
|
||||
/* Clear port statistics */
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
|
||||
SUNI1x10GEXP_BITMSK_MSTAT_CLEAR);
|
||||
udelay(2);
|
||||
memset(&cmac->stats, 0, sizeof(struct cmac_statistics));
|
||||
|
||||
pm3393_enable(cmac, which);
|
||||
|
||||
/*
|
||||
* XXX This should be done by the PHY and preferrably not at all.
|
||||
* The PHY doesn't give us link status indication on its own so have
|
||||
* the link management code query it instead.
|
||||
*/
|
||||
{
|
||||
extern void link_changed(adapter_t *adapter, int port_id);
|
||||
|
||||
link_changed(cmac->adapter, 0);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pm3393_disable(struct cmac *cmac, int which)
|
||||
{
|
||||
if (which & MAC_DIRECTION_RX)
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL);
|
||||
if (which & MAC_DIRECTION_TX)
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL);
|
||||
|
||||
/*
|
||||
* The disable is graceful. Give the PM3393 time. Can't wait very
|
||||
* long here, we may be holding locks.
|
||||
*/
|
||||
udelay(20);
|
||||
|
||||
cmac->instance->enabled &= ~which;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pm3393_loopback_enable(struct cmac *cmac)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pm3393_loopback_disable(struct cmac *cmac)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pm3393_set_mtu(struct cmac *cmac, int mtu)
|
||||
{
|
||||
int enabled = cmac->instance->enabled;
|
||||
|
||||
/* MAX_FRAME_SIZE includes header + FCS, mtu doesn't */
|
||||
mtu += 14 + 4;
|
||||
if (mtu > MAX_FRAME_SIZE)
|
||||
return -EINVAL;
|
||||
|
||||
/* Disable Rx/Tx MAC before configuring it. */
|
||||
if (enabled)
|
||||
pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
|
||||
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu);
|
||||
|
||||
if (enabled)
|
||||
pm3393_enable(cmac, enabled);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 calc_crc(u8 *b, int len)
|
||||
{
|
||||
int i;
|
||||
u32 crc = (u32)~0;
|
||||
|
||||
/* calculate crc one bit at a time */
|
||||
while (len--) {
|
||||
crc ^= *b++;
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (crc & 0x1)
|
||||
crc = (crc >> 1) ^ 0xedb88320;
|
||||
else
|
||||
crc = (crc >> 1);
|
||||
}
|
||||
}
|
||||
|
||||
/* reverse bits */
|
||||
crc = ((crc >> 4) & 0x0f0f0f0f) | ((crc << 4) & 0xf0f0f0f0);
|
||||
crc = ((crc >> 2) & 0x33333333) | ((crc << 2) & 0xcccccccc);
|
||||
crc = ((crc >> 1) & 0x55555555) | ((crc << 1) & 0xaaaaaaaa);
|
||||
/* swap bytes */
|
||||
crc = (crc >> 16) | (crc << 16);
|
||||
crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
|
||||
|
||||
return crc;
|
||||
}
|
||||
|
||||
static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
|
||||
{
|
||||
int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;
|
||||
u32 rx_mode;
|
||||
|
||||
/* Disable MAC RX before reconfiguring it */
|
||||
if (enabled)
|
||||
pm3393_disable(cmac, MAC_DIRECTION_RX);
|
||||
|
||||
pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, &rx_mode);
|
||||
rx_mode &= ~(SUNI1x10GEXP_BITMSK_RXXG_PMODE |
|
||||
SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2,
|
||||
(u16)rx_mode);
|
||||
|
||||
if (t1_rx_mode_promisc(rm)) {
|
||||
/* Promiscuous mode. */
|
||||
rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_PMODE;
|
||||
}
|
||||
if (t1_rx_mode_allmulti(rm)) {
|
||||
/* Accept all multicast. */
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff);
|
||||
rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN;
|
||||
} else if (t1_rx_mode_mc_cnt(rm)) {
|
||||
/* Accept one or more multicast(s). */
|
||||
u8 *addr;
|
||||
int bit;
|
||||
u16 mc_filter[4] = { 0, };
|
||||
|
||||
while ((addr = t1_get_next_mcaddr(rm))) {
|
||||
bit = (calc_crc(addr, ETH_ALEN) >> 23) & 0x3f; /* bit[23:28] */
|
||||
mc_filter[bit >> 4] |= 1 << (bit & 0xf);
|
||||
}
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]);
|
||||
rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN;
|
||||
}
|
||||
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode);
|
||||
|
||||
if (enabled)
|
||||
pm3393_enable(cmac, MAC_DIRECTION_RX);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pm3393_get_speed_duplex_fc(struct cmac *cmac, int *speed,
|
||||
int *duplex, int *fc)
|
||||
{
|
||||
if (speed)
|
||||
*speed = SPEED_10000;
|
||||
if (duplex)
|
||||
*duplex = DUPLEX_FULL;
|
||||
if (fc)
|
||||
*fc = cmac->instance->fc;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,
|
||||
int fc)
|
||||
{
|
||||
if (speed >= 0 && speed != SPEED_10000)
|
||||
return -1;
|
||||
if (duplex >= 0 && duplex != DUPLEX_FULL)
|
||||
return -1;
|
||||
if (fc & ~(PAUSE_TX | PAUSE_RX))
|
||||
return -1;
|
||||
|
||||
if (fc != cmac->instance->fc) {
|
||||
cmac->instance->fc = (u8) fc;
|
||||
if (cmac->instance->enabled & MAC_DIRECTION_TX)
|
||||
pm3393_enable(cmac, MAC_DIRECTION_TX);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define RMON_UPDATE(mac, name, stat_name) \
|
||||
{ \
|
||||
t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \
|
||||
t1_tpi_read((mac)->adapter, OFFSET(((name)+1)), &val1); \
|
||||
t1_tpi_read((mac)->adapter, OFFSET(((name)+2)), &val2); \
|
||||
(mac)->stats.stat_name = ((u64)val0 & 0xffff) | \
|
||||
(((u64)val1 & 0xffff) << 16) | \
|
||||
(((u64)val2 & 0xff) << 32) | \
|
||||
((mac)->stats.stat_name & \
|
||||
(~(u64)0 << 40)); \
|
||||
if (ro & \
|
||||
((name - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW) >> 2)) \
|
||||
(mac)->stats.stat_name += ((u64)1 << 40); \
|
||||
}
|
||||
|
||||
static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
|
||||
int flag)
|
||||
{
|
||||
u64 ro;
|
||||
u32 val0, val1, val2, val3;
|
||||
|
||||
/* Snap the counters */
|
||||
pmwrite(mac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
|
||||
SUNI1x10GEXP_BITMSK_MSTAT_SNAP);
|
||||
|
||||
/* Counter rollover, clear on read */
|
||||
pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0, &val0);
|
||||
pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1, &val1);
|
||||
pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2, &val2);
|
||||
pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3, &val3);
|
||||
ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) |
|
||||
(((u64)val2 & 0xffff) << 32) | (((u64)val3 & 0xffff) << 48);
|
||||
|
||||
/* Rx stats */
|
||||
RMON_UPDATE(mac, RxOctetsReceivedOK, RxOctetsOK);
|
||||
RMON_UPDATE(mac, RxUnicastFramesReceivedOK, RxUnicastFramesOK);
|
||||
RMON_UPDATE(mac, RxMulticastFramesReceivedOK, RxMulticastFramesOK);
|
||||
RMON_UPDATE(mac, RxBroadcastFramesReceivedOK, RxBroadcastFramesOK);
|
||||
RMON_UPDATE(mac, RxPAUSEMACCtrlFramesReceived, RxPauseFrames);
|
||||
RMON_UPDATE(mac, RxFrameCheckSequenceErrors, RxFCSErrors);
|
||||
RMON_UPDATE(mac, RxFramesLostDueToInternalMACErrors,
|
||||
RxInternalMACRcvError);
|
||||
RMON_UPDATE(mac, RxSymbolErrors, RxSymbolErrors);
|
||||
RMON_UPDATE(mac, RxInRangeLengthErrors, RxInRangeLengthErrors);
|
||||
RMON_UPDATE(mac, RxFramesTooLongErrors , RxFrameTooLongErrors);
|
||||
RMON_UPDATE(mac, RxJabbers, RxJabberErrors);
|
||||
RMON_UPDATE(mac, RxFragments, RxRuntErrors);
|
||||
RMON_UPDATE(mac, RxUndersizedFrames, RxRuntErrors);
|
||||
|
||||
/* Tx stats */
|
||||
RMON_UPDATE(mac, TxOctetsTransmittedOK, TxOctetsOK);
|
||||
RMON_UPDATE(mac, TxFramesLostDueToInternalMACTransmissionError,
|
||||
TxInternalMACXmitError);
|
||||
RMON_UPDATE(mac, TxTransmitSystemError, TxFCSErrors);
|
||||
RMON_UPDATE(mac, TxUnicastFramesTransmittedOK, TxUnicastFramesOK);
|
||||
RMON_UPDATE(mac, TxMulticastFramesTransmittedOK, TxMulticastFramesOK);
|
||||
RMON_UPDATE(mac, TxBroadcastFramesTransmittedOK, TxBroadcastFramesOK);
|
||||
RMON_UPDATE(mac, TxPAUSEMACCtrlFramesTransmitted, TxPauseFrames);
|
||||
|
||||
return &mac->stats;
|
||||
}
|
||||
|
||||
static int pm3393_macaddress_get(struct cmac *cmac, u8 mac_addr[6])
|
||||
{
|
||||
memcpy(mac_addr, cmac->instance->mac_addr, 6);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pm3393_macaddress_set(struct cmac *cmac, u8 ma[6])
|
||||
{
|
||||
u32 val, lo, mid, hi, enabled = cmac->instance->enabled;
|
||||
|
||||
/*
|
||||
* MAC addr: 00:07:43:00:13:09
|
||||
*
|
||||
* ma[5] = 0x09
|
||||
* ma[4] = 0x13
|
||||
* ma[3] = 0x00
|
||||
* ma[2] = 0x43
|
||||
* ma[1] = 0x07
|
||||
* ma[0] = 0x00
|
||||
*
|
||||
* The PM3393 requires byte swapping and reverse order entry
|
||||
* when programming MAC addresses:
|
||||
*
|
||||
* low_bits[15:0] = ma[1]:ma[0]
|
||||
* mid_bits[31:16] = ma[3]:ma[2]
|
||||
* high_bits[47:32] = ma[5]:ma[4]
|
||||
*/
|
||||
|
||||
/* Store local copy */
|
||||
memcpy(cmac->instance->mac_addr, ma, 6);
|
||||
|
||||
lo = ((u32) ma[1] << 8) | (u32) ma[0];
|
||||
mid = ((u32) ma[3] << 8) | (u32) ma[2];
|
||||
hi = ((u32) ma[5] << 8) | (u32) ma[4];
|
||||
|
||||
/* Disable Rx/Tx MAC before configuring it. */
|
||||
if (enabled)
|
||||
pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
|
||||
|
||||
/* Set RXXG Station Address */
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi);
|
||||
|
||||
/* Set TXXG Station Address */
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi);
|
||||
|
||||
/* Setup Exact Match Filter 1 with our MAC address
|
||||
*
|
||||
* Must disable exact match filter before configuring it.
|
||||
*/
|
||||
pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val);
|
||||
val &= 0xff0f;
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
|
||||
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid);
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi);
|
||||
|
||||
val |= 0x0090;
|
||||
pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
|
||||
|
||||
if (enabled)
|
||||
pm3393_enable(cmac, enabled);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pm3393_destroy(struct cmac *cmac)
|
||||
{
|
||||
kfree(cmac);
|
||||
}
|
||||
|
||||
static struct cmac_ops pm3393_ops = {
|
||||
.destroy = pm3393_destroy,
|
||||
.reset = pm3393_reset,
|
||||
.interrupt_enable = pm3393_interrupt_enable,
|
||||
.interrupt_disable = pm3393_interrupt_disable,
|
||||
.interrupt_clear = pm3393_interrupt_clear,
|
||||
.interrupt_handler = pm3393_interrupt_handler,
|
||||
.enable = pm3393_enable_port,
|
||||
.disable = pm3393_disable,
|
||||
.loopback_enable = pm3393_loopback_enable,
|
||||
.loopback_disable = pm3393_loopback_disable,
|
||||
.set_mtu = pm3393_set_mtu,
|
||||
.set_rx_mode = pm3393_set_rx_mode,
|
||||
.get_speed_duplex_fc = pm3393_get_speed_duplex_fc,
|
||||
.set_speed_duplex_fc = pm3393_set_speed_duplex_fc,
|
||||
.statistics_update = pm3393_update_statistics,
|
||||
.macaddress_get = pm3393_macaddress_get,
|
||||
.macaddress_set = pm3393_macaddress_set
|
||||
};
|
||||
|
||||
static struct cmac *pm3393_mac_create(adapter_t *adapter, int index)
|
||||
{
|
||||
struct cmac *cmac;
|
||||
|
||||
cmac = kmalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL);
|
||||
if (!cmac)
|
||||
return NULL;
|
||||
memset(cmac, 0, sizeof(*cmac));
|
||||
|
||||
cmac->ops = &pm3393_ops;
|
||||
cmac->instance = (cmac_instance *) (cmac + 1);
|
||||
cmac->adapter = adapter;
|
||||
cmac->instance->fc = PAUSE_TX | PAUSE_RX;
|
||||
|
||||
t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000);
|
||||
t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000);
|
||||
t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800);
|
||||
t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001); /* PL4IO Enable */
|
||||
t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x2324), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x2325), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x2326), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x2327), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x2328), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x2329), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x232a), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x232b), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x232c), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x232d), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x232e), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x232f), 0x00008800);
|
||||
t1_tpi_write(adapter, OFFSET(0x230d), 0x00009c00);
|
||||
t1_tpi_write(adapter, OFFSET(0x2304), 0x00000202); /* PL4IO Calendar Repetitions */
|
||||
|
||||
t1_tpi_write(adapter, OFFSET(0x3200), 0x00008080); /* EFLX Enable */
|
||||
t1_tpi_write(adapter, OFFSET(0x3210), 0x00000000); /* EFLX Channel Deprovision */
|
||||
t1_tpi_write(adapter, OFFSET(0x3203), 0x00000000); /* EFLX Low Limit */
|
||||
t1_tpi_write(adapter, OFFSET(0x3204), 0x00000040); /* EFLX High Limit */
|
||||
t1_tpi_write(adapter, OFFSET(0x3205), 0x000002cc); /* EFLX Almost Full */
|
||||
t1_tpi_write(adapter, OFFSET(0x3206), 0x00000199); /* EFLX Almost Empty */
|
||||
t1_tpi_write(adapter, OFFSET(0x3207), 0x00000240); /* EFLX Cut Through Threshold */
|
||||
t1_tpi_write(adapter, OFFSET(0x3202), 0x00000000); /* EFLX Indirect Register Update */
|
||||
t1_tpi_write(adapter, OFFSET(0x3210), 0x00000001); /* EFLX Channel Provision */
|
||||
t1_tpi_write(adapter, OFFSET(0x3208), 0x0000ffff); /* EFLX Undocumented */
|
||||
t1_tpi_write(adapter, OFFSET(0x320a), 0x0000ffff); /* EFLX Undocumented */
|
||||
t1_tpi_write(adapter, OFFSET(0x320c), 0x0000ffff); /* EFLX enable overflow interrupt The other bit are undocumented */
|
||||
t1_tpi_write(adapter, OFFSET(0x320e), 0x0000ffff); /* EFLX Undocumented */
|
||||
|
||||
t1_tpi_write(adapter, OFFSET(0x2200), 0x0000c000); /* IFLX Configuration - enable */
|
||||
t1_tpi_write(adapter, OFFSET(0x2201), 0x00000000); /* IFLX Channel Deprovision */
|
||||
t1_tpi_write(adapter, OFFSET(0x220e), 0x00000000); /* IFLX Low Limit */
|
||||
t1_tpi_write(adapter, OFFSET(0x220f), 0x00000100); /* IFLX High Limit */
|
||||
t1_tpi_write(adapter, OFFSET(0x2210), 0x00000c00); /* IFLX Almost Full Limit */
|
||||
t1_tpi_write(adapter, OFFSET(0x2211), 0x00000599); /* IFLX Almost Empty Limit */
|
||||
t1_tpi_write(adapter, OFFSET(0x220d), 0x00000000); /* IFLX Indirect Register Update */
|
||||
t1_tpi_write(adapter, OFFSET(0x2201), 0x00000001); /* IFLX Channel Provision */
|
||||
t1_tpi_write(adapter, OFFSET(0x2203), 0x0000ffff); /* IFLX Undocumented */
|
||||
t1_tpi_write(adapter, OFFSET(0x2205), 0x0000ffff); /* IFLX Undocumented */
|
||||
t1_tpi_write(adapter, OFFSET(0x2209), 0x0000ffff); /* IFLX Enable overflow interrupt. The other bit are undocumented */
|
||||
|
||||
t1_tpi_write(adapter, OFFSET(0x2241), 0xfffffffe); /* PL4MOS Undocumented */
|
||||
t1_tpi_write(adapter, OFFSET(0x2242), 0x0000ffff); /* PL4MOS Undocumented */
|
||||
t1_tpi_write(adapter, OFFSET(0x2243), 0x00000008); /* PL4MOS Starving Burst Size */
|
||||
t1_tpi_write(adapter, OFFSET(0x2244), 0x00000008); /* PL4MOS Hungry Burst Size */
|
||||
t1_tpi_write(adapter, OFFSET(0x2245), 0x00000008); /* PL4MOS Transfer Size */
|
||||
t1_tpi_write(adapter, OFFSET(0x2240), 0x00000005); /* PL4MOS Disable */
|
||||
|
||||
t1_tpi_write(adapter, OFFSET(0x2280), 0x00002103); /* PL4ODP Training Repeat and SOP rule */
|
||||
t1_tpi_write(adapter, OFFSET(0x2284), 0x00000000); /* PL4ODP MAX_T setting */
|
||||
|
||||
t1_tpi_write(adapter, OFFSET(0x3280), 0x00000087); /* PL4IDU Enable data forward, port state machine. Set ALLOW_NON_ZERO_OLB */
|
||||
t1_tpi_write(adapter, OFFSET(0x3282), 0x0000001f); /* PL4IDU Enable Dip4 check error interrupts */
|
||||
|
||||
t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32); /* # TXXG Config */
|
||||
/* For T1 use timer based Mac flow control. */
|
||||
t1_tpi_write(adapter, OFFSET(0x304d), 0x8000);
|
||||
t1_tpi_write(adapter, OFFSET(0x2040), 0x059c); /* # RXXG Config */
|
||||
t1_tpi_write(adapter, OFFSET(0x2049), 0x0001); /* # RXXG Cut Through */
|
||||
t1_tpi_write(adapter, OFFSET(0x2070), 0x0000); /* # Disable promiscuous mode */
|
||||
|
||||
/* Setup Exact Match Filter 0 to allow broadcast packets.
|
||||
*/
|
||||
t1_tpi_write(adapter, OFFSET(0x206e), 0x0000); /* # Disable Match Enable bit */
|
||||
t1_tpi_write(adapter, OFFSET(0x204a), 0xffff); /* # low addr */
|
||||
t1_tpi_write(adapter, OFFSET(0x204b), 0xffff); /* # mid addr */
|
||||
t1_tpi_write(adapter, OFFSET(0x204c), 0xffff); /* # high addr */
|
||||
t1_tpi_write(adapter, OFFSET(0x206e), 0x0009); /* # Enable Match Enable bit */
|
||||
|
||||
t1_tpi_write(adapter, OFFSET(0x0003), 0x0000); /* # NO SOP/ PAD_EN setup */
|
||||
t1_tpi_write(adapter, OFFSET(0x0100), 0x0ff0); /* # RXEQB disabled */
|
||||
t1_tpi_write(adapter, OFFSET(0x0101), 0x0f0f); /* # No Preemphasis */
|
||||
|
||||
return cmac;
|
||||
}
|
||||
|
||||
static int pm3393_mac_reset(adapter_t * adapter)
|
||||
{
|
||||
u32 val;
|
||||
u32 x;
|
||||
u32 is_pl4_reset_finished;
|
||||
u32 is_pl4_outof_lock;
|
||||
u32 is_xaui_mabc_pll_locked;
|
||||
u32 successful_reset;
|
||||
int i;
|
||||
|
||||
/* The following steps are required to properly reset
|
||||
* the PM3393. This information is provided in the
|
||||
* PM3393 datasheet (Issue 2: November 2002)
|
||||
* section 13.1 -- Device Reset.
|
||||
*
|
||||
* The PM3393 has three types of components that are
|
||||
* individually reset:
|
||||
*
|
||||
* DRESETB - Digital circuitry
|
||||
* PL4_ARESETB - PL4 analog circuitry
|
||||
* XAUI_ARESETB - XAUI bus analog circuitry
|
||||
*
|
||||
* Steps to reset PM3393 using RSTB pin:
|
||||
*
|
||||
* 1. Assert RSTB pin low ( write 0 )
|
||||
* 2. Wait at least 1ms to initiate a complete initialization of device.
|
||||
* 3. Wait until all external clocks and REFSEL are stable.
|
||||
* 4. Wait minimum of 1ms. (after external clocks and REFEL are stable)
|
||||
* 5. De-assert RSTB ( write 1 )
|
||||
* 6. Wait until internal timers to expires after ~14ms.
|
||||
* - Allows analog clock synthesizer(PL4CSU) to stabilize to
|
||||
* selected reference frequency before allowing the digital
|
||||
* portion of the device to operate.
|
||||
* 7. Wait at least 200us for XAUI interface to stabilize.
|
||||
* 8. Verify the PM3393 came out of reset successfully.
|
||||
* Set successful reset flag if everything worked else try again
|
||||
* a few more times.
|
||||
*/
|
||||
|
||||
successful_reset = 0;
|
||||
for (i = 0; i < 3 && !successful_reset; i++) {
|
||||
/* 1 */
|
||||
t1_tpi_read(adapter, A_ELMER0_GPO, &val);
|
||||
val &= ~1;
|
||||
t1_tpi_write(adapter, A_ELMER0_GPO, val);
|
||||
|
||||
/* 2 */
|
||||
msleep(1);
|
||||
|
||||
/* 3 */
|
||||
msleep(1);
|
||||
|
||||
/* 4 */
|
||||
msleep(2 /*1 extra ms for safety */ );
|
||||
|
||||
/* 5 */
|
||||
val |= 1;
|
||||
t1_tpi_write(adapter, A_ELMER0_GPO, val);
|
||||
|
||||
/* 6 */
|
||||
msleep(15 /*1 extra ms for safety */ );
|
||||
|
||||
/* 7 */
|
||||
msleep(1);
|
||||
|
||||
/* 8 */
|
||||
|
||||
/* Has PL4 analog block come out of reset correctly? */
|
||||
t1_tpi_read(adapter, OFFSET(SUNI1x10GEXP_REG_DEVICE_STATUS), &val);
|
||||
is_pl4_reset_finished = (val & SUNI1x10GEXP_BITMSK_TOP_EXPIRED);
|
||||
|
||||
/* TBD XXX SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL gets locked later in the init sequence
|
||||
* figure out why? */
|
||||
|
||||
/* Have all PL4 block clocks locked? */
|
||||
x = (SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL
|
||||
/*| SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL */ |
|
||||
SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL |
|
||||
SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL |
|
||||
SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL);
|
||||
is_pl4_outof_lock = (val & x);
|
||||
|
||||
/* ??? If this fails, might be able to software reset the XAUI part
|
||||
* and try to recover... thus saving us from doing another HW reset */
|
||||
/* Has the XAUI MABC PLL circuitry stablized? */
|
||||
is_xaui_mabc_pll_locked =
|
||||
(val & SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED);
|
||||
|
||||
successful_reset = (is_pl4_reset_finished && !is_pl4_outof_lock
|
||||
&& is_xaui_mabc_pll_locked);
|
||||
}
|
||||
return successful_reset ? 0 : 1;
|
||||
}
|
||||
|
||||
struct gmac t1_pm3393_ops = {
|
||||
STATS_TICK_SECS,
|
||||
pm3393_mac_create,
|
||||
pm3393_mac_reset
|
||||
};
|
||||
|
|
@ -0,0 +1,468 @@
|
|||
/*****************************************************************************
|
||||
* *
|
||||
* File: regs.h *
|
||||
* $Revision: 1.8 $ *
|
||||
* $Date: 2005/06/21 18:29:48 $ *
|
||||
* Description: *
|
||||
* part of the Chelsio 10Gb Ethernet Driver. *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License, version 2, as *
|
||||
* published by the Free Software Foundation. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License along *
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
|
||||
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* http://www.chelsio.com *
|
||||
* *
|
||||
* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Maintainers: maintainers@chelsio.com *
|
||||
* *
|
||||
* Authors: Dimitrios Michailidis <dm@chelsio.com> *
|
||||
* Tina Yang <tainay@chelsio.com> *
|
||||
* Felix Marti <felix@chelsio.com> *
|
||||
* Scott Bardone <sbardone@chelsio.com> *
|
||||
* Kurt Ottaway <kottaway@chelsio.com> *
|
||||
* Frank DiMambro <frank@chelsio.com> *
|
||||
* *
|
||||
* History: *
|
||||
* *
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _CXGB_REGS_H_
|
||||
#define _CXGB_REGS_H_
|
||||
|
||||
/* SGE registers */
|
||||
#define A_SG_CONTROL 0x0
|
||||
|
||||
#define S_CMDQ0_ENABLE 0
|
||||
#define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE)
|
||||
#define F_CMDQ0_ENABLE V_CMDQ0_ENABLE(1U)
|
||||
|
||||
#define S_CMDQ1_ENABLE 1
|
||||
#define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE)
|
||||
#define F_CMDQ1_ENABLE V_CMDQ1_ENABLE(1U)
|
||||
|
||||
#define S_FL0_ENABLE 2
|
||||
#define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE)
|
||||
#define F_FL0_ENABLE V_FL0_ENABLE(1U)
|
||||
|
||||
#define S_FL1_ENABLE 3
|
||||
#define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE)
|
||||
#define F_FL1_ENABLE V_FL1_ENABLE(1U)
|
||||
|
||||
#define S_CPL_ENABLE 4
|
||||
#define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE)
|
||||
#define F_CPL_ENABLE V_CPL_ENABLE(1U)
|
||||
|
||||
#define S_RESPONSE_QUEUE_ENABLE 5
|
||||
#define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE)
|
||||
#define F_RESPONSE_QUEUE_ENABLE V_RESPONSE_QUEUE_ENABLE(1U)
|
||||
|
||||
#define S_CMDQ_PRIORITY 6
|
||||
#define M_CMDQ_PRIORITY 0x3
|
||||
#define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)
|
||||
#define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)
|
||||
|
||||
#define S_DISABLE_CMDQ1_GTS 9
|
||||
#define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)
|
||||
#define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U)
|
||||
|
||||
#define S_DISABLE_FL0_GTS 10
|
||||
#define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS)
|
||||
#define F_DISABLE_FL0_GTS V_DISABLE_FL0_GTS(1U)
|
||||
|
||||
#define S_DISABLE_FL1_GTS 11
|
||||
#define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS)
|
||||
#define F_DISABLE_FL1_GTS V_DISABLE_FL1_GTS(1U)
|
||||
|
||||
#define S_ENABLE_BIG_ENDIAN 12
|
||||
#define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)
|
||||
#define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U)
|
||||
|
||||
#define S_ISCSI_COALESCE 14
|
||||
#define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)
|
||||
#define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U)
|
||||
|
||||
#define S_RX_PKT_OFFSET 15
|
||||
#define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)
|
||||
|
||||
#define S_VLAN_XTRACT 18
|
||||
#define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)
|
||||
#define F_VLAN_XTRACT V_VLAN_XTRACT(1U)
|
||||
|
||||
#define A_SG_DOORBELL 0x4
|
||||
#define A_SG_CMD0BASELWR 0x8
|
||||
#define A_SG_CMD0BASEUPR 0xc
|
||||
#define A_SG_CMD1BASELWR 0x10
|
||||
#define A_SG_CMD1BASEUPR 0x14
|
||||
#define A_SG_FL0BASELWR 0x18
|
||||
#define A_SG_FL0BASEUPR 0x1c
|
||||
#define A_SG_FL1BASELWR 0x20
|
||||
#define A_SG_FL1BASEUPR 0x24
|
||||
#define A_SG_CMD0SIZE 0x28
|
||||
#define A_SG_FL0SIZE 0x2c
|
||||
#define A_SG_RSPSIZE 0x30
|
||||
#define A_SG_RSPBASELWR 0x34
|
||||
#define A_SG_RSPBASEUPR 0x38
|
||||
#define A_SG_FLTHRESHOLD 0x3c
|
||||
#define A_SG_RSPQUEUECREDIT 0x40
|
||||
#define A_SG_SLEEPING 0x48
|
||||
#define A_SG_INTRTIMER 0x4c
|
||||
#define A_SG_CMD1SIZE 0xb0
|
||||
#define A_SG_FL1SIZE 0xb4
|
||||
#define A_SG_INT_ENABLE 0xb8
|
||||
|
||||
#define S_RESPQ_EXHAUSTED 0
|
||||
#define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED)
|
||||
#define F_RESPQ_EXHAUSTED V_RESPQ_EXHAUSTED(1U)
|
||||
|
||||
#define S_RESPQ_OVERFLOW 1
|
||||
#define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW)
|
||||
#define F_RESPQ_OVERFLOW V_RESPQ_OVERFLOW(1U)
|
||||
|
||||
#define S_FL_EXHAUSTED 2
|
||||
#define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED)
|
||||
#define F_FL_EXHAUSTED V_FL_EXHAUSTED(1U)
|
||||
|
||||
#define S_PACKET_TOO_BIG 3
|
||||
#define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG)
|
||||
#define F_PACKET_TOO_BIG V_PACKET_TOO_BIG(1U)
|
||||
|
||||
#define S_PACKET_MISMATCH 4
|
||||
#define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH)
|
||||
#define F_PACKET_MISMATCH V_PACKET_MISMATCH(1U)
|
||||
|
||||
#define A_SG_INT_CAUSE 0xbc
|
||||
#define A_SG_RESPACCUTIMER 0xc0
|
||||
|
||||
/* MC3 registers */
|
||||
|
||||
#define S_READY 1
|
||||
#define V_READY(x) ((x) << S_READY)
|
||||
#define F_READY V_READY(1U)
|
||||
|
||||
/* MC4 registers */
|
||||
|
||||
#define A_MC4_CFG 0x180
|
||||
#define S_MC4_SLOW 25
|
||||
#define V_MC4_SLOW(x) ((x) << S_MC4_SLOW)
|
||||
#define F_MC4_SLOW V_MC4_SLOW(1U)
|
||||
|
||||
/* TPI registers */
|
||||
|
||||
#define A_TPI_ADDR 0x280
|
||||
#define A_TPI_WR_DATA 0x284
|
||||
#define A_TPI_RD_DATA 0x288
|
||||
#define A_TPI_CSR 0x28c
|
||||
|
||||
#define S_TPIWR 0
|
||||
#define V_TPIWR(x) ((x) << S_TPIWR)
|
||||
#define F_TPIWR V_TPIWR(1U)
|
||||
|
||||
#define S_TPIRDY 1
|
||||
#define V_TPIRDY(x) ((x) << S_TPIRDY)
|
||||
#define F_TPIRDY V_TPIRDY(1U)
|
||||
|
||||
#define A_TPI_PAR 0x29c
|
||||
|
||||
#define S_TPIPAR 0
|
||||
#define M_TPIPAR 0x7f
|
||||
#define V_TPIPAR(x) ((x) << S_TPIPAR)
|
||||
#define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR)
|
||||
|
||||
/* TP registers */
|
||||
|
||||
#define A_TP_IN_CONFIG 0x300
|
||||
|
||||
#define S_TP_IN_CSPI_CPL 3
|
||||
#define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL)
|
||||
#define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U)
|
||||
|
||||
#define S_TP_IN_CSPI_CHECK_IP_CSUM 5
|
||||
#define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM)
|
||||
#define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U)
|
||||
|
||||
#define S_TP_IN_CSPI_CHECK_TCP_CSUM 6
|
||||
#define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM)
|
||||
#define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U)
|
||||
|
||||
#define S_TP_IN_ESPI_ETHERNET 8
|
||||
#define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET)
|
||||
#define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U)
|
||||
|
||||
#define S_TP_IN_ESPI_CHECK_IP_CSUM 12
|
||||
#define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM)
|
||||
#define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U)
|
||||
|
||||
#define S_TP_IN_ESPI_CHECK_TCP_CSUM 13
|
||||
#define V_TP_IN_ESPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_TCP_CSUM)
|
||||
#define F_TP_IN_ESPI_CHECK_TCP_CSUM V_TP_IN_ESPI_CHECK_TCP_CSUM(1U)
|
||||
|
||||
#define S_OFFLOAD_DISABLE 14
|
||||
#define V_OFFLOAD_DISABLE(x) ((x) << S_OFFLOAD_DISABLE)
|
||||
#define F_OFFLOAD_DISABLE V_OFFLOAD_DISABLE(1U)
|
||||
|
||||
#define A_TP_OUT_CONFIG 0x304
|
||||
|
||||
#define S_TP_OUT_CSPI_CPL 2
|
||||
#define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL)
|
||||
#define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U)
|
||||
|
||||
#define S_TP_OUT_ESPI_ETHERNET 6
|
||||
#define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET)
|
||||
#define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U)
|
||||
|
||||
#define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10
|
||||
#define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM)
|
||||
#define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U)
|
||||
|
||||
#define S_TP_OUT_ESPI_GENERATE_TCP_CSUM 11
|
||||
#define V_TP_OUT_ESPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_TCP_CSUM)
|
||||
#define F_TP_OUT_ESPI_GENERATE_TCP_CSUM V_TP_OUT_ESPI_GENERATE_TCP_CSUM(1U)
|
||||
|
||||
#define A_TP_GLOBAL_CONFIG 0x308
|
||||
|
||||
#define S_IP_TTL 0
|
||||
#define M_IP_TTL 0xff
|
||||
#define V_IP_TTL(x) ((x) << S_IP_TTL)
|
||||
|
||||
#define S_TCP_CSUM 11
|
||||
#define V_TCP_CSUM(x) ((x) << S_TCP_CSUM)
|
||||
#define F_TCP_CSUM V_TCP_CSUM(1U)
|
||||
|
||||
#define S_UDP_CSUM 12
|
||||
#define V_UDP_CSUM(x) ((x) << S_UDP_CSUM)
|
||||
#define F_UDP_CSUM V_UDP_CSUM(1U)
|
||||
|
||||
#define S_IP_CSUM 13
|
||||
#define V_IP_CSUM(x) ((x) << S_IP_CSUM)
|
||||
#define F_IP_CSUM V_IP_CSUM(1U)
|
||||
|
||||
#define S_PATH_MTU 15
|
||||
#define V_PATH_MTU(x) ((x) << S_PATH_MTU)
|
||||
#define F_PATH_MTU V_PATH_MTU(1U)
|
||||
|
||||
#define S_5TUPLE_LOOKUP 17
|
||||
#define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP)
|
||||
|
||||
#define S_SYN_COOKIE_PARAMETER 26
|
||||
#define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER)
|
||||
|
||||
#define A_TP_PC_CONFIG 0x348
|
||||
#define S_DIS_TX_FILL_WIN_PUSH 12
|
||||
#define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH)
|
||||
#define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U)
|
||||
|
||||
#define S_TP_PC_REV 30
|
||||
#define M_TP_PC_REV 0x3
|
||||
#define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV)
|
||||
#define A_TP_RESET 0x44c
|
||||
#define S_TP_RESET 0
|
||||
#define V_TP_RESET(x) ((x) << S_TP_RESET)
|
||||
#define F_TP_RESET V_TP_RESET(1U)
|
||||
|
||||
#define A_TP_INT_ENABLE 0x470
|
||||
#define A_TP_INT_CAUSE 0x474
|
||||
#define A_TP_TX_DROP_CONFIG 0x4b8
|
||||
|
||||
#define S_ENABLE_TX_DROP 31
|
||||
#define V_ENABLE_TX_DROP(x) ((x) << S_ENABLE_TX_DROP)
|
||||
#define F_ENABLE_TX_DROP V_ENABLE_TX_DROP(1U)
|
||||
|
||||
#define S_ENABLE_TX_ERROR 30
|
||||
#define V_ENABLE_TX_ERROR(x) ((x) << S_ENABLE_TX_ERROR)
|
||||
#define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U)
|
||||
|
||||
#define S_DROP_TICKS_CNT 4
|
||||
#define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT)
|
||||
|
||||
#define S_NUM_PKTS_DROPPED 0
|
||||
#define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED)
|
||||
|
||||
/* CSPI registers */
|
||||
|
||||
#define S_DIP4ERR 0
|
||||
#define V_DIP4ERR(x) ((x) << S_DIP4ERR)
|
||||
#define F_DIP4ERR V_DIP4ERR(1U)
|
||||
|
||||
#define S_RXDROP 1
|
||||
#define V_RXDROP(x) ((x) << S_RXDROP)
|
||||
#define F_RXDROP V_RXDROP(1U)
|
||||
|
||||
#define S_TXDROP 2
|
||||
#define V_TXDROP(x) ((x) << S_TXDROP)
|
||||
#define F_TXDROP V_TXDROP(1U)
|
||||
|
||||
#define S_RXOVERFLOW 3
|
||||
#define V_RXOVERFLOW(x) ((x) << S_RXOVERFLOW)
|
||||
#define F_RXOVERFLOW V_RXOVERFLOW(1U)
|
||||
|
||||
#define S_RAMPARITYERR 4
|
||||
#define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR)
|
||||
#define F_RAMPARITYERR V_RAMPARITYERR(1U)
|
||||
|
||||
/* ESPI registers */
|
||||
|
||||
#define A_ESPI_SCH_TOKEN0 0x880
|
||||
#define A_ESPI_SCH_TOKEN1 0x884
|
||||
#define A_ESPI_SCH_TOKEN2 0x888
|
||||
#define A_ESPI_SCH_TOKEN3 0x88c
|
||||
#define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890
|
||||
#define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894
|
||||
#define A_ESPI_CALENDAR_LENGTH 0x898
|
||||
#define A_PORT_CONFIG 0x89c
|
||||
|
||||
#define S_RX_NPORTS 0
|
||||
#define V_RX_NPORTS(x) ((x) << S_RX_NPORTS)
|
||||
|
||||
#define S_TX_NPORTS 8
|
||||
#define V_TX_NPORTS(x) ((x) << S_TX_NPORTS)
|
||||
|
||||
#define A_ESPI_FIFO_STATUS_ENABLE 0x8a0
|
||||
|
||||
#define S_RXSTATUSENABLE 0
|
||||
#define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE)
|
||||
#define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U)
|
||||
|
||||
#define S_INTEL1010MODE 4
|
||||
#define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE)
|
||||
#define F_INTEL1010MODE V_INTEL1010MODE(1U)
|
||||
|
||||
#define A_ESPI_MAXBURST1_MAXBURST2 0x8a8
|
||||
#define A_ESPI_TRAIN 0x8ac
|
||||
#define A_ESPI_INTR_STATUS 0x8c8
|
||||
|
||||
#define S_DIP2PARITYERR 5
|
||||
#define V_DIP2PARITYERR(x) ((x) << S_DIP2PARITYERR)
|
||||
#define F_DIP2PARITYERR V_DIP2PARITYERR(1U)
|
||||
|
||||
#define A_ESPI_INTR_ENABLE 0x8cc
|
||||
#define A_RX_DROP_THRESHOLD 0x8d0
|
||||
#define A_ESPI_RX_RESET 0x8ec
|
||||
#define A_ESPI_MISC_CONTROL 0x8f0
|
||||
|
||||
#define S_OUT_OF_SYNC_COUNT 0
|
||||
#define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT)
|
||||
|
||||
#define S_DIP2_PARITY_ERR_THRES 5
|
||||
#define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES)
|
||||
|
||||
#define S_DIP4_THRES 9
|
||||
#define V_DIP4_THRES(x) ((x) << S_DIP4_THRES)
|
||||
|
||||
#define S_MONITORED_PORT_NUM 25
|
||||
#define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM)
|
||||
|
||||
#define S_MONITORED_DIRECTION 27
|
||||
#define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION)
|
||||
#define F_MONITORED_DIRECTION V_MONITORED_DIRECTION(1U)
|
||||
|
||||
#define S_MONITORED_INTERFACE 28
|
||||
#define V_MONITORED_INTERFACE(x) ((x) << S_MONITORED_INTERFACE)
|
||||
#define F_MONITORED_INTERFACE V_MONITORED_INTERFACE(1U)
|
||||
|
||||
#define A_ESPI_DIP2_ERR_COUNT 0x8f4
|
||||
#define A_ESPI_CMD_ADDR 0x8f8
|
||||
|
||||
#define S_WRITE_DATA 0
|
||||
#define V_WRITE_DATA(x) ((x) << S_WRITE_DATA)
|
||||
|
||||
#define S_REGISTER_OFFSET 8
|
||||
#define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET)
|
||||
|
||||
#define S_CHANNEL_ADDR 12
|
||||
#define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR)
|
||||
|
||||
#define S_MODULE_ADDR 16
|
||||
#define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR)
|
||||
|
||||
#define S_BUNDLE_ADDR 20
|
||||
#define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR)
|
||||
|
||||
#define S_SPI4_COMMAND 24
|
||||
#define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND)
|
||||
|
||||
#define A_ESPI_GOSTAT 0x8fc
|
||||
#define S_ESPI_CMD_BUSY 8
|
||||
#define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY)
|
||||
#define F_ESPI_CMD_BUSY V_ESPI_CMD_BUSY(1U)
|
||||
|
||||
/* PL registers */
|
||||
|
||||
#define A_PL_ENABLE 0xa00
|
||||
|
||||
#define S_PL_INTR_SGE_ERR 0
|
||||
#define V_PL_INTR_SGE_ERR(x) ((x) << S_PL_INTR_SGE_ERR)
|
||||
#define F_PL_INTR_SGE_ERR V_PL_INTR_SGE_ERR(1U)
|
||||
|
||||
#define S_PL_INTR_SGE_DATA 1
|
||||
#define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA)
|
||||
#define F_PL_INTR_SGE_DATA V_PL_INTR_SGE_DATA(1U)
|
||||
|
||||
#define S_PL_INTR_TP 6
|
||||
#define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP)
|
||||
#define F_PL_INTR_TP V_PL_INTR_TP(1U)
|
||||
|
||||
#define S_PL_INTR_ESPI 8
|
||||
#define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI)
|
||||
#define F_PL_INTR_ESPI V_PL_INTR_ESPI(1U)
|
||||
|
||||
#define S_PL_INTR_PCIX 10
|
||||
#define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX)
|
||||
#define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U)
|
||||
|
||||
#define S_PL_INTR_EXT 11
|
||||
#define V_PL_INTR_EXT(x) ((x) << S_PL_INTR_EXT)
|
||||
#define F_PL_INTR_EXT V_PL_INTR_EXT(1U)
|
||||
|
||||
#define A_PL_CAUSE 0xa04
|
||||
|
||||
/* MC5 registers */
|
||||
|
||||
#define A_MC5_CONFIG 0xc04
|
||||
|
||||
#define S_TCAM_RESET 1
|
||||
#define V_TCAM_RESET(x) ((x) << S_TCAM_RESET)
|
||||
#define F_TCAM_RESET V_TCAM_RESET(1U)
|
||||
|
||||
#define S_M_BUS_ENABLE 5
|
||||
#define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE)
|
||||
#define F_M_BUS_ENABLE V_M_BUS_ENABLE(1U)
|
||||
|
||||
/* PCICFG registers */
|
||||
|
||||
#define A_PCICFG_PM_CSR 0x44
|
||||
#define A_PCICFG_VPD_ADDR 0x4a
|
||||
|
||||
#define S_VPD_OP_FLAG 15
|
||||
#define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG)
|
||||
#define F_VPD_OP_FLAG V_VPD_OP_FLAG(1U)
|
||||
|
||||
#define A_PCICFG_VPD_DATA 0x4c
|
||||
|
||||
#define A_PCICFG_INTR_ENABLE 0xf4
|
||||
#define A_PCICFG_INTR_CAUSE 0xf8
|
||||
|
||||
#define A_PCICFG_MODE 0xfc
|
||||
|
||||
#define S_PCI_MODE_64BIT 0
|
||||
#define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT)
|
||||
#define F_PCI_MODE_64BIT V_PCI_MODE_64BIT(1U)
|
||||
|
||||
#define S_PCI_MODE_PCIX 5
|
||||
#define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX)
|
||||
#define F_PCI_MODE_PCIX V_PCI_MODE_PCIX(1U)
|
||||
|
||||
#define S_PCI_MODE_CLK 6
|
||||
#define M_PCI_MODE_CLK 0x3
|
||||
#define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK)
|
||||
|
||||
#endif /* _CXGB_REGS_H_ */
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,105 @@
|
|||
/*****************************************************************************
|
||||
* *
|
||||
* File: sge.h *
|
||||
* $Revision: 1.11 $ *
|
||||
* $Date: 2005/06/21 22:10:55 $ *
|
||||
* Description: *
|
||||
* part of the Chelsio 10Gb Ethernet Driver. *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License, version 2, as *
|
||||
* published by the Free Software Foundation. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License along *
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
|
||||
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* http://www.chelsio.com *
|
||||
* *
|
||||
* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Maintainers: maintainers@chelsio.com *
|
||||
* *
|
||||
* Authors: Dimitrios Michailidis <dm@chelsio.com> *
|
||||
* Tina Yang <tainay@chelsio.com> *
|
||||
* Felix Marti <felix@chelsio.com> *
|
||||
* Scott Bardone <sbardone@chelsio.com> *
|
||||
* Kurt Ottaway <kottaway@chelsio.com> *
|
||||
* Frank DiMambro <frank@chelsio.com> *
|
||||
* *
|
||||
* History: *
|
||||
* *
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _CXGB_SGE_H_
|
||||
#define _CXGB_SGE_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#ifndef IRQ_RETVAL
|
||||
#define IRQ_RETVAL(x)
|
||||
typedef void irqreturn_t;
|
||||
#endif
|
||||
|
||||
typedef irqreturn_t (*intr_handler_t)(int, void *, struct pt_regs *);
|
||||
|
||||
struct sge_intr_counts {
|
||||
unsigned int respQ_empty; /* # times respQ empty */
|
||||
unsigned int respQ_overflow; /* # respQ overflow (fatal) */
|
||||
unsigned int freelistQ_empty; /* # times freelist empty */
|
||||
unsigned int pkt_too_big; /* packet too large (fatal) */
|
||||
unsigned int pkt_mismatch;
|
||||
unsigned int cmdQ_full[3]; /* not HW IRQ, host cmdQ[] full */
|
||||
unsigned int cmdQ_restarted[3];/* # of times cmdQ X was restarted */
|
||||
unsigned int ethernet_pkts; /* # of Ethernet packets received */
|
||||
unsigned int offload_pkts; /* # of offload packets received */
|
||||
unsigned int offload_bundles; /* # of offload pkt bundles delivered */
|
||||
unsigned int pure_rsps; /* # of non-payload responses */
|
||||
unsigned int unhandled_irqs; /* # of unhandled interrupts */
|
||||
unsigned int tx_ipfrags;
|
||||
unsigned int tx_reg_pkts;
|
||||
unsigned int tx_lso_pkts;
|
||||
unsigned int tx_do_cksum;
|
||||
};
|
||||
|
||||
struct sge_port_stats {
|
||||
unsigned long rx_cso_good; /* # of successful RX csum offloads */
|
||||
unsigned long tx_cso; /* # of TX checksum offloads */
|
||||
unsigned long vlan_xtract; /* # of VLAN tag extractions */
|
||||
unsigned long vlan_insert; /* # of VLAN tag extractions */
|
||||
unsigned long tso; /* # of TSO requests */
|
||||
unsigned long rx_drops; /* # of packets dropped due to no mem */
|
||||
};
|
||||
|
||||
struct sk_buff;
|
||||
struct net_device;
|
||||
struct adapter;
|
||||
struct sge_params;
|
||||
struct sge;
|
||||
|
||||
struct sge *t1_sge_create(struct adapter *, struct sge_params *);
|
||||
int t1_sge_configure(struct sge *, struct sge_params *);
|
||||
int t1_sge_set_coalesce_params(struct sge *, struct sge_params *);
|
||||
void t1_sge_destroy(struct sge *);
|
||||
intr_handler_t t1_select_intr_handler(adapter_t *adapter);
|
||||
unsigned int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
|
||||
unsigned int qid, struct net_device *netdev);
|
||||
int t1_start_xmit(struct sk_buff *skb, struct net_device *dev);
|
||||
void t1_set_vlan_accel(struct adapter *adapter, int on_off);
|
||||
void t1_sge_start(struct sge *);
|
||||
void t1_sge_stop(struct sge *);
|
||||
int t1_sge_intr_error_handler(struct sge *);
|
||||
void t1_sge_intr_enable(struct sge *);
|
||||
void t1_sge_intr_disable(struct sge *);
|
||||
void t1_sge_intr_clear(struct sge *);
|
||||
const struct sge_intr_counts *t1_sge_get_intr_counts(struct sge *sge);
|
||||
const struct sge_port_stats *t1_sge_get_port_stats(struct sge *sge, int port);
|
||||
|
||||
#endif /* _CXGB_SGE_H_ */
|
||||
|
|
@ -0,0 +1,812 @@
|
|||
/*****************************************************************************
|
||||
* *
|
||||
* File: subr.c *
|
||||
* $Revision: 1.27 $ *
|
||||
* $Date: 2005/06/22 01:08:36 $ *
|
||||
* Description: *
|
||||
* Various subroutines (intr,pio,etc.) used by Chelsio 10G Ethernet driver. *
|
||||
* part of the Chelsio 10Gb Ethernet Driver. *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License, version 2, as *
|
||||
* published by the Free Software Foundation. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License along *
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
|
||||
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* http://www.chelsio.com *
|
||||
* *
|
||||
* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Maintainers: maintainers@chelsio.com *
|
||||
* *
|
||||
* Authors: Dimitrios Michailidis <dm@chelsio.com> *
|
||||
* Tina Yang <tainay@chelsio.com> *
|
||||
* Felix Marti <felix@chelsio.com> *
|
||||
* Scott Bardone <sbardone@chelsio.com> *
|
||||
* Kurt Ottaway <kottaway@chelsio.com> *
|
||||
* Frank DiMambro <frank@chelsio.com> *
|
||||
* *
|
||||
* History: *
|
||||
* *
|
||||
****************************************************************************/
|
||||
|
||||
#include "common.h"
|
||||
#include "elmer0.h"
|
||||
#include "regs.h"
|
||||
#include "gmac.h"
|
||||
#include "cphy.h"
|
||||
#include "sge.h"
|
||||
#include "espi.h"
|
||||
|
||||
/**
|
||||
* t1_wait_op_done - wait until an operation is completed
|
||||
* @adapter: the adapter performing the operation
|
||||
* @reg: the register to check for completion
|
||||
* @mask: a single-bit field within @reg that indicates completion
|
||||
* @polarity: the value of the field when the operation is completed
|
||||
* @attempts: number of check iterations
|
||||
* @delay: delay in usecs between iterations
|
||||
*
|
||||
* Wait until an operation is completed by checking a bit in a register
|
||||
* up to @attempts times. Returns %0 if the operation completes and %1
|
||||
* otherwise.
|
||||
*/
|
||||
static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
|
||||
int attempts, int delay)
|
||||
{
|
||||
while (1) {
|
||||
u32 val = readl(adapter->regs + reg) & mask;
|
||||
|
||||
if (!!val == polarity)
|
||||
return 0;
|
||||
if (--attempts == 0)
|
||||
return 1;
|
||||
if (delay)
|
||||
udelay(delay);
|
||||
}
|
||||
}
|
||||
|
||||
#define TPI_ATTEMPTS 50
|
||||
|
||||
/*
|
||||
* Write a register over the TPI interface (unlocked and locked versions).
|
||||
*/
|
||||
static int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
|
||||
{
|
||||
int tpi_busy;
|
||||
|
||||
writel(addr, adapter->regs + A_TPI_ADDR);
|
||||
writel(value, adapter->regs + A_TPI_WR_DATA);
|
||||
writel(F_TPIWR, adapter->regs + A_TPI_CSR);
|
||||
|
||||
tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
|
||||
TPI_ATTEMPTS, 3);
|
||||
if (tpi_busy)
|
||||
CH_ALERT("%s: TPI write to 0x%x failed\n",
|
||||
adapter->name, addr);
|
||||
return tpi_busy;
|
||||
}
|
||||
|
||||
int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
|
||||
{
|
||||
int ret;
|
||||
|
||||
spin_lock(&(adapter)->tpi_lock);
|
||||
ret = __t1_tpi_write(adapter, addr, value);
|
||||
spin_unlock(&(adapter)->tpi_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read a register over the TPI interface (unlocked and locked versions).
|
||||
*/
|
||||
static int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
|
||||
{
|
||||
int tpi_busy;
|
||||
|
||||
writel(addr, adapter->regs + A_TPI_ADDR);
|
||||
writel(0, adapter->regs + A_TPI_CSR);
|
||||
|
||||
tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
|
||||
TPI_ATTEMPTS, 3);
|
||||
if (tpi_busy)
|
||||
CH_ALERT("%s: TPI read from 0x%x failed\n",
|
||||
adapter->name, addr);
|
||||
else
|
||||
*valp = readl(adapter->regs + A_TPI_RD_DATA);
|
||||
return tpi_busy;
|
||||
}
|
||||
|
||||
int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
|
||||
{
|
||||
int ret;
|
||||
|
||||
spin_lock(&(adapter)->tpi_lock);
|
||||
ret = __t1_tpi_read(adapter, addr, valp);
|
||||
spin_unlock(&(adapter)->tpi_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Called when a port's link settings change to propagate the new values to the
|
||||
* associated PHY and MAC. After performing the common tasks it invokes an
|
||||
* OS-specific handler.
|
||||
*/
|
||||
/* static */ void link_changed(adapter_t *adapter, int port_id)
|
||||
{
|
||||
int link_ok, speed, duplex, fc;
|
||||
struct cphy *phy = adapter->port[port_id].phy;
|
||||
struct link_config *lc = &adapter->port[port_id].link_config;
|
||||
|
||||
phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
|
||||
|
||||
lc->speed = speed < 0 ? SPEED_INVALID : speed;
|
||||
lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
|
||||
if (!(lc->requested_fc & PAUSE_AUTONEG))
|
||||
fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
|
||||
|
||||
if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
|
||||
/* Set MAC speed, duplex, and flow control to match PHY. */
|
||||
struct cmac *mac = adapter->port[port_id].mac;
|
||||
|
||||
mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
|
||||
lc->fc = (unsigned char)fc;
|
||||
}
|
||||
t1_link_changed(adapter, port_id, link_ok, speed, duplex, fc);
|
||||
}
|
||||
|
||||
static int t1_pci_intr_handler(adapter_t *adapter)
|
||||
{
|
||||
u32 pcix_cause;
|
||||
|
||||
pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
|
||||
|
||||
if (pcix_cause) {
|
||||
pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
|
||||
pcix_cause);
|
||||
t1_fatal_err(adapter); /* PCI errors are fatal */
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Wait until Elmer's MI1 interface is ready for new operations.
|
||||
*/
|
||||
static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
|
||||
{
|
||||
int attempts = 100, busy;
|
||||
|
||||
do {
|
||||
u32 val;
|
||||
|
||||
__t1_tpi_read(adapter, mi1_reg, &val);
|
||||
busy = val & F_MI1_OP_BUSY;
|
||||
if (busy)
|
||||
udelay(10);
|
||||
} while (busy && --attempts);
|
||||
if (busy)
|
||||
CH_ALERT("%s: MDIO operation timed out\n",
|
||||
adapter->name);
|
||||
return busy;
|
||||
}
|
||||
|
||||
/*
|
||||
* MI1 MDIO initialization.
|
||||
*/
|
||||
static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
|
||||
{
|
||||
u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1;
|
||||
u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) |
|
||||
V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);
|
||||
|
||||
if (!(bi->caps & SUPPORTED_10000baseT_Full))
|
||||
val |= V_MI1_SOF(1);
|
||||
t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
|
||||
}
|
||||
|
||||
static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int *valp)
|
||||
{
|
||||
u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
|
||||
|
||||
spin_lock(&(adapter)->tpi_lock);
|
||||
|
||||
/* Write the address we want. */
|
||||
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
|
||||
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
|
||||
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
|
||||
MI1_OP_INDIRECT_ADDRESS);
|
||||
mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
|
||||
|
||||
/* Write the operation we want. */
|
||||
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
|
||||
mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
|
||||
|
||||
/* Read the data. */
|
||||
__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
|
||||
spin_unlock(&(adapter)->tpi_lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int val)
|
||||
{
|
||||
u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
|
||||
|
||||
spin_lock(&(adapter)->tpi_lock);
|
||||
|
||||
/* Write the address we want. */
|
||||
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
|
||||
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
|
||||
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
|
||||
MI1_OP_INDIRECT_ADDRESS);
|
||||
mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
|
||||
|
||||
/* Write the data. */
|
||||
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
|
||||
__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
|
||||
mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
|
||||
spin_unlock(&(adapter)->tpi_lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct mdio_ops mi1_mdio_ext_ops = {
|
||||
mi1_mdio_init,
|
||||
mi1_mdio_ext_read,
|
||||
mi1_mdio_ext_write
|
||||
};
|
||||
|
||||
enum {
|
||||
CH_BRD_N110_1F,
|
||||
CH_BRD_N210_1F,
|
||||
};
|
||||
|
||||
static struct board_info t1_board[] = {
|
||||
|
||||
{ CHBT_BOARD_N110, 1/*ports#*/,
|
||||
SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
|
||||
CHBT_MAC_PM3393, CHBT_PHY_88X2010,
|
||||
125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
|
||||
1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
|
||||
0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
|
||||
&t1_mv88x201x_ops, &mi1_mdio_ext_ops,
|
||||
"Chelsio N110 1x10GBaseX NIC" },
|
||||
|
||||
{ CHBT_BOARD_N210, 1/*ports#*/,
|
||||
SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T2,
|
||||
CHBT_MAC_PM3393, CHBT_PHY_88X2010,
|
||||
125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
|
||||
1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
|
||||
0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
|
||||
&t1_mv88x201x_ops, &mi1_mdio_ext_ops,
|
||||
"Chelsio N210 1x10GBaseX NIC" },
|
||||
|
||||
};
|
||||
|
||||
struct pci_device_id t1_pci_tbl[] = {
|
||||
CH_DEVICE(7, 0, CH_BRD_N110_1F),
|
||||
CH_DEVICE(10, 1, CH_BRD_N210_1F),
|
||||
{ 0, }
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
|
||||
|
||||
/*
|
||||
* Return the board_info structure with a given index. Out-of-range indices
|
||||
* return NULL.
|
||||
*/
|
||||
const struct board_info *t1_get_board_info(unsigned int board_id)
|
||||
{
|
||||
return board_id < ARRAY_SIZE(t1_board) ? &t1_board[board_id] : NULL;
|
||||
}
|
||||
|
||||
struct chelsio_vpd_t {
|
||||
u32 format_version;
|
||||
u8 serial_number[16];
|
||||
u8 mac_base_address[6];
|
||||
u8 pad[2]; /* make multiple-of-4 size requirement explicit */
|
||||
};
|
||||
|
||||
#define EEPROMSIZE (8 * 1024)
|
||||
#define EEPROM_MAX_POLL 4
|
||||
|
||||
/*
|
||||
* Read SEEPROM. A zero is written to the flag register when the addres is
|
||||
* written to the Control register. The hardware device will set the flag to a
|
||||
* one when 4B have been transferred to the Data register.
|
||||
*/
|
||||
int t1_seeprom_read(adapter_t *adapter, u32 addr, u32 *data)
|
||||
{
|
||||
int i = EEPROM_MAX_POLL;
|
||||
u16 val;
|
||||
|
||||
if (addr >= EEPROMSIZE || (addr & 3))
|
||||
return -EINVAL;
|
||||
|
||||
pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
|
||||
do {
|
||||
udelay(50);
|
||||
pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
|
||||
} while (!(val & F_VPD_OP_FLAG) && --i);
|
||||
|
||||
if (!(val & F_VPD_OP_FLAG)) {
|
||||
CH_ERR("%s: reading EEPROM address 0x%x failed\n",
|
||||
adapter->name, addr);
|
||||
return -EIO;
|
||||
}
|
||||
pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, data);
|
||||
*data = le32_to_cpu(*data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
|
||||
{
|
||||
int addr, ret = 0;
|
||||
|
||||
for (addr = 0; !ret && addr < sizeof(*vpd); addr += sizeof(u32))
|
||||
ret = t1_seeprom_read(adapter, addr,
|
||||
(u32 *)((u8 *)vpd + addr));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read a port's MAC address from the VPD ROM.
|
||||
*/
|
||||
static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
|
||||
{
|
||||
struct chelsio_vpd_t vpd;
|
||||
|
||||
if (t1_eeprom_vpd_get(adapter, &vpd))
|
||||
return 1;
|
||||
memcpy(mac_addr, vpd.mac_base_address, 5);
|
||||
mac_addr[5] = vpd.mac_base_address[5] + index;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up the MAC/PHY according to the requested link settings.
|
||||
*
|
||||
* If the PHY can auto-negotiate first decide what to advertise, then
|
||||
* enable/disable auto-negotiation as desired and reset.
|
||||
*
|
||||
* If the PHY does not auto-negotiate we just reset it.
|
||||
*
|
||||
* If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
|
||||
* otherwise do it later based on the outcome of auto-negotiation.
|
||||
*/
|
||||
int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
|
||||
{
|
||||
unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
|
||||
|
||||
if (lc->supported & SUPPORTED_Autoneg) {
|
||||
lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
|
||||
if (fc) {
|
||||
lc->advertising |= ADVERTISED_ASYM_PAUSE;
|
||||
if (fc == (PAUSE_RX | PAUSE_TX))
|
||||
lc->advertising |= ADVERTISED_PAUSE;
|
||||
}
|
||||
phy->ops->advertise(phy, lc->advertising);
|
||||
|
||||
if (lc->autoneg == AUTONEG_DISABLE) {
|
||||
lc->speed = lc->requested_speed;
|
||||
lc->duplex = lc->requested_duplex;
|
||||
lc->fc = (unsigned char)fc;
|
||||
mac->ops->set_speed_duplex_fc(mac, lc->speed,
|
||||
lc->duplex, fc);
|
||||
/* Also disables autoneg */
|
||||
phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
|
||||
phy->ops->reset(phy, 0);
|
||||
} else
|
||||
phy->ops->autoneg_enable(phy); /* also resets PHY */
|
||||
} else {
|
||||
mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
|
||||
lc->fc = (unsigned char)fc;
|
||||
phy->ops->reset(phy, 0);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* External interrupt handler for boards using elmer0.
|
||||
*/
|
||||
int elmer0_ext_intr_handler(adapter_t *adapter)
|
||||
{
|
||||
struct cphy *phy;
|
||||
int phy_cause;
|
||||
u32 cause;
|
||||
|
||||
t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
|
||||
|
||||
switch (board_info(adapter)->board) {
|
||||
case CHBT_BOARD_N210:
|
||||
case CHBT_BOARD_N110:
|
||||
if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
|
||||
phy = adapter->port[0].phy;
|
||||
phy_cause = phy->ops->interrupt_handler(phy);
|
||||
if (phy_cause & cphy_cause_link_change)
|
||||
link_changed(adapter, 0);
|
||||
}
|
||||
break;
|
||||
}
|
||||
t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Enables all interrupts. */
|
||||
void t1_interrupts_enable(adapter_t *adapter)
|
||||
{
|
||||
unsigned int i;
|
||||
u32 pl_intr;
|
||||
|
||||
adapter->slow_intr_mask = F_PL_INTR_SGE_ERR;
|
||||
|
||||
t1_sge_intr_enable(adapter->sge);
|
||||
if (adapter->espi) {
|
||||
adapter->slow_intr_mask |= F_PL_INTR_ESPI;
|
||||
t1_espi_intr_enable(adapter->espi);
|
||||
}
|
||||
|
||||
/* Enable MAC/PHY interrupts for each port. */
|
||||
for_each_port(adapter, i) {
|
||||
adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);
|
||||
adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);
|
||||
}
|
||||
|
||||
/* Enable PCIX & external chip interrupts on ASIC boards. */
|
||||
pl_intr = readl(adapter->regs + A_PL_ENABLE);
|
||||
|
||||
/* PCI-X interrupts */
|
||||
pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
|
||||
0xffffffff);
|
||||
|
||||
adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
|
||||
pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
|
||||
writel(pl_intr, adapter->regs + A_PL_ENABLE);
|
||||
}
|
||||
|
||||
/* Disables all interrupts. */
|
||||
void t1_interrupts_disable(adapter_t* adapter)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
t1_sge_intr_disable(adapter->sge);
|
||||
if (adapter->espi)
|
||||
t1_espi_intr_disable(adapter->espi);
|
||||
|
||||
/* Disable MAC/PHY interrupts for each port. */
|
||||
for_each_port(adapter, i) {
|
||||
adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);
|
||||
adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);
|
||||
}
|
||||
|
||||
/* Disable PCIX & external chip interrupts. */
|
||||
writel(0, adapter->regs + A_PL_ENABLE);
|
||||
|
||||
/* PCI-X interrupts */
|
||||
pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
|
||||
|
||||
adapter->slow_intr_mask = 0;
|
||||
}
|
||||
|
||||
/* Clears all interrupts */
|
||||
void t1_interrupts_clear(adapter_t* adapter)
|
||||
{
|
||||
unsigned int i;
|
||||
u32 pl_intr;
|
||||
|
||||
|
||||
t1_sge_intr_clear(adapter->sge);
|
||||
if (adapter->espi)
|
||||
t1_espi_intr_clear(adapter->espi);
|
||||
|
||||
/* Clear MAC/PHY interrupts for each port. */
|
||||
for_each_port(adapter, i) {
|
||||
adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);
|
||||
adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);
|
||||
}
|
||||
|
||||
/* Enable interrupts for external devices. */
|
||||
pl_intr = readl(adapter->regs + A_PL_CAUSE);
|
||||
|
||||
writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
|
||||
adapter->regs + A_PL_CAUSE);
|
||||
|
||||
/* PCI-X interrupts */
|
||||
pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
|
||||
}
|
||||
|
||||
/*
|
||||
* Slow path interrupt handler for ASICs.
|
||||
*/
|
||||
int t1_slow_intr_handler(adapter_t *adapter)
|
||||
{
|
||||
u32 cause = readl(adapter->regs + A_PL_CAUSE);
|
||||
|
||||
cause &= adapter->slow_intr_mask;
|
||||
if (!cause)
|
||||
return 0;
|
||||
if (cause & F_PL_INTR_SGE_ERR)
|
||||
t1_sge_intr_error_handler(adapter->sge);
|
||||
if (cause & F_PL_INTR_ESPI)
|
||||
t1_espi_intr_handler(adapter->espi);
|
||||
if (cause & F_PL_INTR_PCIX)
|
||||
t1_pci_intr_handler(adapter);
|
||||
if (cause & F_PL_INTR_EXT)
|
||||
t1_elmer0_ext_intr(adapter);
|
||||
|
||||
/* Clear the interrupts just processed. */
|
||||
writel(cause, adapter->regs + A_PL_CAUSE);
|
||||
(void)readl(adapter->regs + A_PL_CAUSE); /* flush writes */
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Pause deadlock avoidance parameters */
|
||||
#define DROP_MSEC 16
|
||||
#define DROP_PKTS_CNT 1
|
||||
|
||||
static void set_csum_offload(adapter_t *adapter, u32 csum_bit, int enable)
|
||||
{
|
||||
u32 val = readl(adapter->regs + A_TP_GLOBAL_CONFIG);
|
||||
|
||||
if (enable)
|
||||
val |= csum_bit;
|
||||
else
|
||||
val &= ~csum_bit;
|
||||
writel(val, adapter->regs + A_TP_GLOBAL_CONFIG);
|
||||
}
|
||||
|
||||
void t1_tp_set_ip_checksum_offload(adapter_t *adapter, int enable)
|
||||
{
|
||||
set_csum_offload(adapter, F_IP_CSUM, enable);
|
||||
}
|
||||
|
||||
void t1_tp_set_udp_checksum_offload(adapter_t *adapter, int enable)
|
||||
{
|
||||
set_csum_offload(adapter, F_UDP_CSUM, enable);
|
||||
}
|
||||
|
||||
void t1_tp_set_tcp_checksum_offload(adapter_t *adapter, int enable)
|
||||
{
|
||||
set_csum_offload(adapter, F_TCP_CSUM, enable);
|
||||
}
|
||||
|
||||
static void t1_tp_reset(adapter_t *adapter, unsigned int tp_clk)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = F_TP_IN_CSPI_CPL | F_TP_IN_CSPI_CHECK_IP_CSUM |
|
||||
F_TP_IN_CSPI_CHECK_TCP_CSUM | F_TP_IN_ESPI_ETHERNET;
|
||||
val |= F_TP_IN_ESPI_CHECK_IP_CSUM |
|
||||
F_TP_IN_ESPI_CHECK_TCP_CSUM;
|
||||
writel(val, adapter->regs + A_TP_IN_CONFIG);
|
||||
writel(F_TP_OUT_CSPI_CPL |
|
||||
F_TP_OUT_ESPI_ETHERNET |
|
||||
F_TP_OUT_ESPI_GENERATE_IP_CSUM |
|
||||
F_TP_OUT_ESPI_GENERATE_TCP_CSUM,
|
||||
adapter->regs + A_TP_OUT_CONFIG);
|
||||
|
||||
val = readl(adapter->regs + A_TP_GLOBAL_CONFIG);
|
||||
val &= ~(F_IP_CSUM | F_UDP_CSUM | F_TCP_CSUM);
|
||||
writel(val, adapter->regs + A_TP_GLOBAL_CONFIG);
|
||||
|
||||
/*
|
||||
* Enable pause frame deadlock prevention.
|
||||
*/
|
||||
if (is_T2(adapter)) {
|
||||
u32 drop_ticks = DROP_MSEC * (tp_clk / 1000);
|
||||
|
||||
writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR |
|
||||
V_DROP_TICKS_CNT(drop_ticks) |
|
||||
V_NUM_PKTS_DROPPED(DROP_PKTS_CNT),
|
||||
adapter->regs + A_TP_TX_DROP_CONFIG);
|
||||
}
|
||||
|
||||
writel(F_TP_RESET, adapter->regs + A_TP_RESET);
|
||||
}
|
||||
|
||||
int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
|
||||
struct adapter_params *p)
|
||||
{
|
||||
p->chip_version = bi->chip_term;
|
||||
if (p->chip_version == CHBT_TERM_T1 ||
|
||||
p->chip_version == CHBT_TERM_T2) {
|
||||
u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
|
||||
|
||||
val = G_TP_PC_REV(val);
|
||||
if (val == 2)
|
||||
p->chip_revision = TERM_T1B;
|
||||
else if (val == 3)
|
||||
p->chip_revision = TERM_T2;
|
||||
else
|
||||
return -1;
|
||||
} else
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable board components other than the Chelsio chip, such as external MAC
|
||||
* and PHY.
|
||||
*/
|
||||
static int board_init(adapter_t *adapter, const struct board_info *bi)
|
||||
{
|
||||
switch (bi->board) {
|
||||
case CHBT_BOARD_N110:
|
||||
case CHBT_BOARD_N210:
|
||||
writel(V_TPIPAR(0xf), adapter->regs + A_TPI_PAR);
|
||||
t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize and configure the Terminator HW modules. Note that external
|
||||
* MAC and PHYs are initialized separately.
|
||||
*/
|
||||
int t1_init_hw_modules(adapter_t *adapter)
|
||||
{
|
||||
int err = -EIO;
|
||||
const struct board_info *bi = board_info(adapter);
|
||||
|
||||
if (!bi->clock_mc4) {
|
||||
u32 val = readl(adapter->regs + A_MC4_CFG);
|
||||
|
||||
writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
|
||||
writel(F_M_BUS_ENABLE | F_TCAM_RESET,
|
||||
adapter->regs + A_MC5_CONFIG);
|
||||
}
|
||||
|
||||
if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
|
||||
bi->espi_nports))
|
||||
goto out_err;
|
||||
|
||||
t1_tp_reset(adapter, bi->clock_core);
|
||||
|
||||
err = t1_sge_configure(adapter->sge, &adapter->params.sge);
|
||||
if (err)
|
||||
goto out_err;
|
||||
|
||||
err = 0;
|
||||
out_err:
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Determine a card's PCI mode.
|
||||
*/
|
||||
static void __devinit get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
|
||||
{
|
||||
static unsigned short speed_map[] = { 33, 66, 100, 133 };
|
||||
u32 pci_mode;
|
||||
|
||||
pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
|
||||
p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)];
|
||||
p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32;
|
||||
p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Release the structures holding the SW per-Terminator-HW-module state.
|
||||
*/
|
||||
void t1_free_sw_modules(adapter_t *adapter)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for_each_port(adapter, i) {
|
||||
struct cmac *mac = adapter->port[i].mac;
|
||||
struct cphy *phy = adapter->port[i].phy;
|
||||
|
||||
if (mac)
|
||||
mac->ops->destroy(mac);
|
||||
if (phy)
|
||||
phy->ops->destroy(phy);
|
||||
}
|
||||
|
||||
if (adapter->sge)
|
||||
t1_sge_destroy(adapter->sge);
|
||||
if (adapter->espi)
|
||||
t1_espi_destroy(adapter->espi);
|
||||
}
|
||||
|
||||
static void __devinit init_link_config(struct link_config *lc,
|
||||
const struct board_info *bi)
|
||||
{
|
||||
lc->supported = bi->caps;
|
||||
lc->requested_speed = lc->speed = SPEED_INVALID;
|
||||
lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
|
||||
lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
|
||||
if (lc->supported & SUPPORTED_Autoneg) {
|
||||
lc->advertising = lc->supported;
|
||||
lc->autoneg = AUTONEG_ENABLE;
|
||||
lc->requested_fc |= PAUSE_AUTONEG;
|
||||
} else {
|
||||
lc->advertising = 0;
|
||||
lc->autoneg = AUTONEG_DISABLE;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Allocate and initialize the data structures that hold the SW state of
|
||||
* the Terminator HW modules.
|
||||
*/
|
||||
int __devinit t1_init_sw_modules(adapter_t *adapter,
|
||||
const struct board_info *bi)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
adapter->params.brd_info = bi;
|
||||
adapter->params.nports = bi->port_number;
|
||||
adapter->params.stats_update_period = bi->gmac->stats_update_period;
|
||||
|
||||
adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
|
||||
if (!adapter->sge) {
|
||||
CH_ERR("%s: SGE initialization failed\n",
|
||||
adapter->name);
|
||||
goto error;
|
||||
}
|
||||
|
||||
if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
|
||||
CH_ERR("%s: ESPI initialization failed\n",
|
||||
adapter->name);
|
||||
goto error;
|
||||
}
|
||||
|
||||
board_init(adapter, bi);
|
||||
bi->mdio_ops->init(adapter, bi);
|
||||
if (bi->gphy->reset)
|
||||
bi->gphy->reset(adapter);
|
||||
if (bi->gmac->reset)
|
||||
bi->gmac->reset(adapter);
|
||||
|
||||
for_each_port(adapter, i) {
|
||||
u8 hw_addr[6];
|
||||
struct cmac *mac;
|
||||
int phy_addr = bi->mdio_phybaseaddr + i;
|
||||
|
||||
adapter->port[i].phy = bi->gphy->create(adapter, phy_addr,
|
||||
bi->mdio_ops);
|
||||
if (!adapter->port[i].phy) {
|
||||
CH_ERR("%s: PHY %d initialization failed\n",
|
||||
adapter->name, i);
|
||||
goto error;
|
||||
}
|
||||
|
||||
adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
|
||||
if (!mac) {
|
||||
CH_ERR("%s: MAC %d initialization failed\n",
|
||||
adapter->name, i);
|
||||
goto error;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the port's MAC addresses either from the EEPROM if one
|
||||
* exists or the one hardcoded in the MAC.
|
||||
*/
|
||||
if (vpd_macaddress_get(adapter, i, hw_addr)) {
|
||||
CH_ERR("%s: could not read MAC address from VPD ROM\n",
|
||||
adapter->port[i].dev->name);
|
||||
goto error;
|
||||
}
|
||||
memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);
|
||||
init_link_config(&adapter->port[i].link_config, bi);
|
||||
}
|
||||
|
||||
get_pci_mode(adapter, &adapter->params.pci);
|
||||
t1_interrupts_clear(adapter);
|
||||
return 0;
|
||||
|
||||
error:
|
||||
t1_free_sw_modules(adapter);
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
/*****************************************************************************
|
||||
* *
|
||||
* File: suni1x10gexp_regs.h *
|
||||
* $Revision: 1.9 $ *
|
||||
* $Date: 2005/06/22 00:17:04 $ *
|
||||
* Description: *
|
||||
* PMC/SIERRA (pm3393) MAC-PHY functionality. *
|
||||
* part of the Chelsio 10Gb Ethernet Driver. *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License, version 2, as *
|
||||
* published by the Free Software Foundation. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License along *
|
||||
* with this program; if not, write to the Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
|
||||
* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* http://www.chelsio.com *
|
||||
* *
|
||||
* Maintainers: maintainers@chelsio.com *
|
||||
* *
|
||||
* Authors: PMC/SIERRA *
|
||||
* *
|
||||
* History: *
|
||||
* *
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _CXGB_SUNI1x10GEXP_REGS_H_
|
||||
#define _CXGB_SUNI1x10GEXP_REGS_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/
|
||||
/******************************************************************************/
|
||||
/* Refer to the Register Bit Masks bellow for the naming of each register and */
|
||||
/* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */
|
||||
/******************************************************************************/
|
||||
|
||||
#define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004
|
||||
#define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS 0x000D
|
||||
#define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE 0x000E
|
||||
#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE 0x0102
|
||||
#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS 0x0104
|
||||
#define SUNI1x10GEXP_REG_RXXG_CONFIG_1 0x2040
|
||||
#define SUNI1x10GEXP_REG_RXXG_CONFIG_3 0x2042
|
||||
#define SUNI1x10GEXP_REG_RXXG_INTERRUPT 0x2043
|
||||
#define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH 0x2045
|
||||
#define SUNI1x10GEXP_REG_RXXG_SA_15_0 0x2046
|
||||
#define SUNI1x10GEXP_REG_RXXG_SA_31_16 0x2047
|
||||
#define SUNI1x10GEXP_REG_RXXG_SA_47_32 0x2048
|
||||
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW 0x204D
|
||||
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID 0x204E
|
||||
#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH 0x204F
|
||||
#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW 0x206A
|
||||
#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW 0x206B
|
||||
#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH 0x206C
|
||||
#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH 0x206D
|
||||
#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 0x206E
|
||||
#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 0x2070
|
||||
#define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE 0x2088
|
||||
#define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS 0x2089
|
||||
#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE 0x208B
|
||||
#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS 0x208C
|
||||
#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE 0x20C7
|
||||
#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS 0x20C8
|
||||
#define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 0x2101
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 0x2102
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2 0x2103
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3 0x2104
|
||||
#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0 0x2105
|
||||
#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 0x2106
|
||||
#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 0x2107
|
||||
#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 0x2108
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW 0x2110
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW 0x2114
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW 0x2120
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW 0x2124
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW 0x2128
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW 0x2130
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW 0x2138
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW 0x213C
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW 0x2140
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW 0x2144
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW 0x214C
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW 0x2150
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW 0x2154
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW 0x2158
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW 0x2194
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW 0x219C
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW 0x21A0
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW 0x21A8
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW 0x21B0
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW 0x21B8
|
||||
#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 0x21BC
|
||||
#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE 0x2209
|
||||
#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT 0x220A
|
||||
#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK 0x2282
|
||||
#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT 0x2283
|
||||
#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS 0x2300
|
||||
#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE 0x2301
|
||||
#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK 0x2302
|
||||
#define SUNI1x10GEXP_REG_TXXG_CONFIG_1 0x3040
|
||||
#define SUNI1x10GEXP_REG_TXXG_CONFIG_3 0x3042
|
||||
#define SUNI1x10GEXP_REG_TXXG_INTERRUPT 0x3043
|
||||
#define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE 0x3045
|
||||
#define SUNI1x10GEXP_REG_TXXG_SA_15_0 0x3047
|
||||
#define SUNI1x10GEXP_REG_TXXG_SA_31_16 0x3048
|
||||
#define SUNI1x10GEXP_REG_TXXG_SA_47_32 0x3049
|
||||
#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS 0x3084
|
||||
#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE 0x3085
|
||||
#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE 0x30C6
|
||||
#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS 0x30C7
|
||||
#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE 0x320C
|
||||
#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION 0x320D
|
||||
#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK 0x3282
|
||||
#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT 0x3283
|
||||
|
||||
/******************************************************************************/
|
||||
/* -- End register offset definitions -- */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/** SUNI-1x10GE-XP REGISTER BIT MASKS **/
|
||||
/******************************************************************************/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Register 0x0004: S/UNI-1x10GE-XP Device Status
|
||||
* Bit 9 TOP_SXRA_EXPIRED
|
||||
* Bit 8 TOP_MDIO_BUSY
|
||||
* Bit 7 TOP_DTRB
|
||||
* Bit 6 TOP_EXPIRED
|
||||
* Bit 5 TOP_PAUSED
|
||||
* Bit 4 TOP_PL4_ID_DOOL
|
||||
* Bit 3 TOP_PL4_IS_DOOL
|
||||
* Bit 2 TOP_PL4_ID_ROOL
|
||||
* Bit 1 TOP_PL4_IS_ROOL
|
||||
* Bit 0 TOP_PL4_OUT_ROOL
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED 0x0200
|
||||
#define SUNI1x10GEXP_BITMSK_TOP_EXPIRED 0x0040
|
||||
#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL 0x0010
|
||||
#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL 0x0008
|
||||
#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL 0x0004
|
||||
#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL 0x0002
|
||||
#define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL 0x0001
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Register 0x000E:PM3393 Global interrupt enable
|
||||
* Bit 15 TOP_INTE
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define SUNI1x10GEXP_BITMSK_TOP_INTE 0x8000
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Register 0x2040: RXXG Configuration 1
|
||||
* Bit 15 RXXG_RXEN
|
||||
* Bit 14 RXXG_ROCF
|
||||
* Bit 13 RXXG_PAD_STRIP
|
||||
* Bit 10 RXXG_PUREP
|
||||
* Bit 9 RXXG_LONGP
|
||||
* Bit 8 RXXG_PARF
|
||||
* Bit 7 RXXG_FLCHK
|
||||
* Bit 5 RXXG_PASS_CTRL
|
||||
* Bit 3 RXXG_CRC_STRIP
|
||||
* Bit 2-0 RXXG_MIFG
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define SUNI1x10GEXP_BITMSK_RXXG_RXEN 0x8000
|
||||
#define SUNI1x10GEXP_BITMSK_RXXG_PUREP 0x0400
|
||||
#define SUNI1x10GEXP_BITMSK_RXXG_FLCHK 0x0080
|
||||
#define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP 0x0008
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Register 0x2070: RXXG Address Filter Control 2
|
||||
* Bit 1 RXXG_PMODE
|
||||
* Bit 0 RXXG_MHASH_EN
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define SUNI1x10GEXP_BITMSK_RXXG_PMODE 0x0002
|
||||
#define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN 0x0001
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Register 0x2100: MSTAT Control
|
||||
* Bit 2 MSTAT_WRITE
|
||||
* Bit 1 MSTAT_CLEAR
|
||||
* Bit 0 MSTAT_SNAP
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR 0x0002
|
||||
#define SUNI1x10GEXP_BITMSK_MSTAT_SNAP 0x0001
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Register 0x3040: TXXG Configuration Register 1
|
||||
* Bit 15 TXXG_TXEN0
|
||||
* Bit 13 TXXG_HOSTPAUSE
|
||||
* Bit 12-7 TXXG_IPGT
|
||||
* Bit 5 TXXG_32BIT_ALIGN
|
||||
* Bit 4 TXXG_CRCEN
|
||||
* Bit 3 TXXG_FCTX
|
||||
* Bit 2 TXXG_FCRX
|
||||
* Bit 1 TXXG_PADEN
|
||||
* Bit 0 TXXG_SPRE
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define SUNI1x10GEXP_BITMSK_TXXG_TXEN0 0x8000
|
||||
#define SUNI1x10GEXP_BITOFF_TXXG_IPGT 7
|
||||
#define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN 0x0020
|
||||
#define SUNI1x10GEXP_BITMSK_TXXG_CRCEN 0x0010
|
||||
#define SUNI1x10GEXP_BITMSK_TXXG_FCTX 0x0008
|
||||
#define SUNI1x10GEXP_BITMSK_TXXG_FCRX 0x0004
|
||||
#define SUNI1x10GEXP_BITMSK_TXXG_PADEN 0x0002
|
||||
|
||||
#endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */
|
||||
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/*******************************************************************************
|
||||
|
||||
|
||||
Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
|
||||
Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the Free
|
||||
|
|
@ -156,7 +156,7 @@
|
|||
|
||||
#define DRV_NAME "e100"
|
||||
#define DRV_EXT "-NAPI"
|
||||
#define DRV_VERSION "3.4.8-k2"DRV_EXT
|
||||
#define DRV_VERSION "3.4.14-k2"DRV_EXT
|
||||
#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
|
||||
#define DRV_COPYRIGHT "Copyright(c) 1999-2005 Intel Corporation"
|
||||
#define PFX DRV_NAME ": "
|
||||
|
|
@ -785,6 +785,7 @@ static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
|
|||
}
|
||||
|
||||
#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
|
||||
#define E100_WAIT_SCB_FAST 20 /* delay like the old code */
|
||||
static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
|
@ -798,7 +799,7 @@ static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
|
|||
if(likely(!readb(&nic->csr->scb.cmd_lo)))
|
||||
break;
|
||||
cpu_relax();
|
||||
if(unlikely(i > (E100_WAIT_SCB_TIMEOUT >> 1)))
|
||||
if(unlikely(i > E100_WAIT_SCB_FAST))
|
||||
udelay(5);
|
||||
}
|
||||
if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
|
||||
|
|
@ -902,8 +903,8 @@ static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
|
|||
|
||||
static void e100_get_defaults(struct nic *nic)
|
||||
{
|
||||
struct param_range rfds = { .min = 16, .max = 256, .count = 64 };
|
||||
struct param_range cbs = { .min = 64, .max = 256, .count = 64 };
|
||||
struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
|
||||
struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
|
||||
|
||||
pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
|
||||
/* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
|
||||
|
|
@ -1006,25 +1007,213 @@ static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
|
|||
c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
|
||||
}
|
||||
|
||||
/********************************************************/
|
||||
/* Micro code for 8086:1229 Rev 8 */
|
||||
/********************************************************/
|
||||
|
||||
/* Parameter values for the D101M B-step */
|
||||
#define D101M_CPUSAVER_TIMER_DWORD 78
|
||||
#define D101M_CPUSAVER_BUNDLE_DWORD 65
|
||||
#define D101M_CPUSAVER_MIN_SIZE_DWORD 126
|
||||
|
||||
#define D101M_B_RCVBUNDLE_UCODE \
|
||||
{\
|
||||
0x00550215, 0xFFFF0437, 0xFFFFFFFF, 0x06A70789, 0xFFFFFFFF, 0x0558FFFF, \
|
||||
0x000C0001, 0x00101312, 0x000C0008, 0x00380216, \
|
||||
0x0010009C, 0x00204056, 0x002380CC, 0x00380056, \
|
||||
0x0010009C, 0x00244C0B, 0x00000800, 0x00124818, \
|
||||
0x00380438, 0x00000000, 0x00140000, 0x00380555, \
|
||||
0x00308000, 0x00100662, 0x00100561, 0x000E0408, \
|
||||
0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
|
||||
0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
|
||||
0x000C007E, 0x00222C21, 0x000C0002, 0x00103093, \
|
||||
0x00380C7A, 0x00080000, 0x00103090, 0x00380C7A, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x0010009C, 0x00244C2D, 0x00010004, 0x00041000, \
|
||||
0x003A0437, 0x00044010, 0x0038078A, 0x00000000, \
|
||||
0x00100099, 0x00206C7A, 0x0010009C, 0x00244C48, \
|
||||
0x00130824, 0x000C0001, 0x00101213, 0x00260C75, \
|
||||
0x00041000, 0x00010004, 0x00130826, 0x000C0006, \
|
||||
0x002206A8, 0x0013C926, 0x00101313, 0x003806A8, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
|
||||
0x00101210, 0x00380C34, 0x00000000, 0x00000000, \
|
||||
0x0021155B, 0x00100099, 0x00206559, 0x0010009C, \
|
||||
0x00244559, 0x00130836, 0x000C0000, 0x00220C62, \
|
||||
0x000C0001, 0x00101B13, 0x00229C0E, 0x00210C0E, \
|
||||
0x00226C0E, 0x00216C0E, 0x0022FC0E, 0x00215C0E, \
|
||||
0x00214C0E, 0x00380555, 0x00010004, 0x00041000, \
|
||||
0x00278C67, 0x00040800, 0x00018100, 0x003A0437, \
|
||||
0x00130826, 0x000C0001, 0x00220559, 0x00101313, \
|
||||
0x00380559, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00130831, 0x0010090B, 0x00124813, \
|
||||
0x000CFF80, 0x002606AB, 0x00041000, 0x00010004, \
|
||||
0x003806A8, 0x00000000, 0x00000000, 0x00000000, \
|
||||
}
|
||||
|
||||
/********************************************************/
|
||||
/* Micro code for 8086:1229 Rev 9 */
|
||||
/********************************************************/
|
||||
|
||||
/* Parameter values for the D101S */
|
||||
#define D101S_CPUSAVER_TIMER_DWORD 78
|
||||
#define D101S_CPUSAVER_BUNDLE_DWORD 67
|
||||
#define D101S_CPUSAVER_MIN_SIZE_DWORD 128
|
||||
|
||||
#define D101S_RCVBUNDLE_UCODE \
|
||||
{\
|
||||
0x00550242, 0xFFFF047E, 0xFFFFFFFF, 0x06FF0818, 0xFFFFFFFF, 0x05A6FFFF, \
|
||||
0x000C0001, 0x00101312, 0x000C0008, 0x00380243, \
|
||||
0x0010009C, 0x00204056, 0x002380D0, 0x00380056, \
|
||||
0x0010009C, 0x00244F8B, 0x00000800, 0x00124818, \
|
||||
0x0038047F, 0x00000000, 0x00140000, 0x003805A3, \
|
||||
0x00308000, 0x00100610, 0x00100561, 0x000E0408, \
|
||||
0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
|
||||
0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
|
||||
0x000C007E, 0x00222FA1, 0x000C0002, 0x00103093, \
|
||||
0x00380F90, 0x00080000, 0x00103090, 0x00380F90, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x0010009C, 0x00244FAD, 0x00010004, 0x00041000, \
|
||||
0x003A047E, 0x00044010, 0x00380819, 0x00000000, \
|
||||
0x00100099, 0x00206FFD, 0x0010009A, 0x0020AFFD, \
|
||||
0x0010009C, 0x00244FC8, 0x00130824, 0x000C0001, \
|
||||
0x00101213, 0x00260FF7, 0x00041000, 0x00010004, \
|
||||
0x00130826, 0x000C0006, 0x00220700, 0x0013C926, \
|
||||
0x00101313, 0x00380700, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
|
||||
0x00101210, 0x00380FB6, 0x00000000, 0x00000000, \
|
||||
0x002115A9, 0x00100099, 0x002065A7, 0x0010009A, \
|
||||
0x0020A5A7, 0x0010009C, 0x002445A7, 0x00130836, \
|
||||
0x000C0000, 0x00220FE4, 0x000C0001, 0x00101B13, \
|
||||
0x00229F8E, 0x00210F8E, 0x00226F8E, 0x00216F8E, \
|
||||
0x0022FF8E, 0x00215F8E, 0x00214F8E, 0x003805A3, \
|
||||
0x00010004, 0x00041000, 0x00278FE9, 0x00040800, \
|
||||
0x00018100, 0x003A047E, 0x00130826, 0x000C0001, \
|
||||
0x002205A7, 0x00101313, 0x003805A7, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00130831, \
|
||||
0x0010090B, 0x00124813, 0x000CFF80, 0x00260703, \
|
||||
0x00041000, 0x00010004, 0x00380700 \
|
||||
}
|
||||
|
||||
/********************************************************/
|
||||
/* Micro code for the 8086:1229 Rev F/10 */
|
||||
/********************************************************/
|
||||
|
||||
/* Parameter values for the D102 E-step */
|
||||
#define D102_E_CPUSAVER_TIMER_DWORD 42
|
||||
#define D102_E_CPUSAVER_BUNDLE_DWORD 54
|
||||
#define D102_E_CPUSAVER_MIN_SIZE_DWORD 46
|
||||
|
||||
#define D102_E_RCVBUNDLE_UCODE \
|
||||
{\
|
||||
0x007D028F, 0x0E4204F9, 0x14ED0C85, 0x14FA14E9, 0x0EF70E36, 0x1FFF1FFF, \
|
||||
0x00E014B9, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00E014BD, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00E014D5, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00E014C1, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00E014C8, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00200600, 0x00E014EE, 0x00000000, 0x00000000, \
|
||||
0x0030FF80, 0x00940E46, 0x00038200, 0x00102000, \
|
||||
0x00E00E43, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00300006, 0x00E014FB, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000, \
|
||||
0x00906EFD, 0x00900EFD, 0x00E00EF8, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
}
|
||||
|
||||
static void e100_load_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb)
|
||||
{
|
||||
int i;
|
||||
static const u32 ucode[UCODE_SIZE] = {
|
||||
/* NFS packets are misinterpreted as TCO packets and
|
||||
* incorrectly routed to the BMC over SMBus. This
|
||||
* microcode patch checks the fragmented IP bit in the
|
||||
* NFS/UDP header to distinguish between NFS and TCO. */
|
||||
0x0EF70E36, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF,
|
||||
0x1FFF1FFF, 0x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000,
|
||||
0x00906EFD, 0x00900EFD, 0x00E00EF8,
|
||||
};
|
||||
/* *INDENT-OFF* */
|
||||
static struct {
|
||||
u32 ucode[UCODE_SIZE + 1];
|
||||
u8 mac;
|
||||
u8 timer_dword;
|
||||
u8 bundle_dword;
|
||||
u8 min_size_dword;
|
||||
} ucode_opts[] = {
|
||||
{ D101M_B_RCVBUNDLE_UCODE,
|
||||
mac_82559_D101M,
|
||||
D101M_CPUSAVER_TIMER_DWORD,
|
||||
D101M_CPUSAVER_BUNDLE_DWORD,
|
||||
D101M_CPUSAVER_MIN_SIZE_DWORD },
|
||||
{ D101S_RCVBUNDLE_UCODE,
|
||||
mac_82559_D101S,
|
||||
D101S_CPUSAVER_TIMER_DWORD,
|
||||
D101S_CPUSAVER_BUNDLE_DWORD,
|
||||
D101S_CPUSAVER_MIN_SIZE_DWORD },
|
||||
{ D102_E_RCVBUNDLE_UCODE,
|
||||
mac_82551_F,
|
||||
D102_E_CPUSAVER_TIMER_DWORD,
|
||||
D102_E_CPUSAVER_BUNDLE_DWORD,
|
||||
D102_E_CPUSAVER_MIN_SIZE_DWORD },
|
||||
{ D102_E_RCVBUNDLE_UCODE,
|
||||
mac_82551_10,
|
||||
D102_E_CPUSAVER_TIMER_DWORD,
|
||||
D102_E_CPUSAVER_BUNDLE_DWORD,
|
||||
D102_E_CPUSAVER_MIN_SIZE_DWORD },
|
||||
{ {0}, 0, 0, 0, 0}
|
||||
}, *opts;
|
||||
/* *INDENT-ON* */
|
||||
|
||||
if(nic->mac == mac_82551_F || nic->mac == mac_82551_10) {
|
||||
for(i = 0; i < UCODE_SIZE; i++)
|
||||
cb->u.ucode[i] = cpu_to_le32(ucode[i]);
|
||||
cb->command = cpu_to_le16(cb_ucode);
|
||||
} else
|
||||
cb->command = cpu_to_le16(cb_nop);
|
||||
#define BUNDLESMALL 1
|
||||
#define BUNDLEMAX 50
|
||||
#define INTDELAY 15000
|
||||
|
||||
opts = ucode_opts;
|
||||
|
||||
/* do not load u-code for ICH devices */
|
||||
if (nic->flags & ich)
|
||||
return;
|
||||
|
||||
/* Search for ucode match against h/w rev_id */
|
||||
while (opts->mac) {
|
||||
if (nic->mac == opts->mac) {
|
||||
int i;
|
||||
u32 *ucode = opts->ucode;
|
||||
|
||||
/* Insert user-tunable settings */
|
||||
ucode[opts->timer_dword] &= 0xFFFF0000;
|
||||
ucode[opts->timer_dword] |=
|
||||
(u16) INTDELAY;
|
||||
ucode[opts->bundle_dword] &= 0xFFFF0000;
|
||||
ucode[opts->bundle_dword] |= (u16) BUNDLEMAX;
|
||||
ucode[opts->min_size_dword] &= 0xFFFF0000;
|
||||
ucode[opts->min_size_dword] |=
|
||||
(BUNDLESMALL) ? 0xFFFF : 0xFF80;
|
||||
|
||||
for(i = 0; i < UCODE_SIZE; i++)
|
||||
cb->u.ucode[i] = cpu_to_le32(ucode[i]);
|
||||
cb->command = cpu_to_le16(cb_ucode);
|
||||
return;
|
||||
}
|
||||
opts++;
|
||||
}
|
||||
|
||||
cb->command = cpu_to_le16(cb_nop);
|
||||
}
|
||||
|
||||
static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
|
||||
|
|
@ -1307,14 +1496,15 @@ static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb,
|
|||
{
|
||||
cb->command = nic->tx_command;
|
||||
/* interrupt every 16 packets regardless of delay */
|
||||
if((nic->cbs_avail & ~15) == nic->cbs_avail) cb->command |= cb_i;
|
||||
if((nic->cbs_avail & ~15) == nic->cbs_avail)
|
||||
cb->command |= cpu_to_le16(cb_i);
|
||||
cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
|
||||
cb->u.tcb.tcb_byte_count = 0;
|
||||
cb->u.tcb.threshold = nic->tx_threshold;
|
||||
cb->u.tcb.tbd_count = 1;
|
||||
cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
|
||||
skb->data, skb->len, PCI_DMA_TODEVICE));
|
||||
// check for mapping failure?
|
||||
/* check for mapping failure? */
|
||||
cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
|
||||
}
|
||||
|
||||
|
|
@ -1539,7 +1729,7 @@ static inline int e100_rx_indicate(struct nic *nic, struct rx *rx,
|
|||
/* Don't indicate if hardware indicates errors */
|
||||
nic->net_stats.rx_dropped++;
|
||||
dev_kfree_skb_any(skb);
|
||||
} else if(actual_size > nic->netdev->mtu + VLAN_ETH_HLEN) {
|
||||
} else if(actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
|
||||
/* Don't indicate oversized frames */
|
||||
nic->rx_over_length_errors++;
|
||||
nic->net_stats.rx_dropped++;
|
||||
|
|
@ -1706,6 +1896,7 @@ static int e100_poll(struct net_device *netdev, int *budget)
|
|||
static void e100_netpoll(struct net_device *netdev)
|
||||
{
|
||||
struct nic *nic = netdev_priv(netdev);
|
||||
|
||||
e100_disable_irq(nic);
|
||||
e100_intr(nic->pdev->irq, netdev, NULL);
|
||||
e100_tx_clean(nic);
|
||||
|
|
@ -2108,6 +2299,8 @@ static void e100_diag_test(struct net_device *netdev,
|
|||
}
|
||||
for(i = 0; i < E100_TEST_LEN; i++)
|
||||
test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
|
||||
|
||||
msleep_interruptible(4 * 1000);
|
||||
}
|
||||
|
||||
static int e100_phys_id(struct net_device *netdev, u32 data)
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -135,6 +135,18 @@ config DM9102
|
|||
<file:Documentation/networking/net-modules.txt>. The module will
|
||||
be called dmfe.
|
||||
|
||||
config ULI526X
|
||||
tristate "ULi M526x controller support"
|
||||
depends on NET_TULIP && PCI
|
||||
select CRC32
|
||||
---help---
|
||||
This driver is for ULi M5261/M5263 10/100M Ethernet Controller
|
||||
(<http://www.uli.com.tw/>).
|
||||
|
||||
To compile this driver as a module, choose M here and read
|
||||
<file:Documentation/networking/net-modules.txt>. The module will
|
||||
be called uli526x.
|
||||
|
||||
config PCMCIA_XIRCOM
|
||||
tristate "Xircom CardBus support (new driver)"
|
||||
depends on NET_TULIP && CARDBUS
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ obj-$(CONFIG_WINBOND_840) += winbond-840.o
|
|||
obj-$(CONFIG_DE2104X) += de2104x.o
|
||||
obj-$(CONFIG_TULIP) += tulip.o
|
||||
obj-$(CONFIG_DE4X5) += de4x5.o
|
||||
obj-$(CONFIG_ULI526X) += uli526x.o
|
||||
|
||||
# Declare multi-part drivers.
|
||||
|
||||
|
|
|
|||
|
|
@ -81,25 +81,6 @@ int tulip_mdio_read(struct net_device *dev, int phy_id, int location)
|
|||
return retval & 0xffff;
|
||||
}
|
||||
|
||||
if(tp->chip_id == ULI526X && tp->revision >= 0x40) {
|
||||
int value;
|
||||
int i = 1000;
|
||||
|
||||
value = ioread32(ioaddr + CSR9);
|
||||
iowrite32(value & 0xFFEFFFFF, ioaddr + CSR9);
|
||||
|
||||
value = (phy_id << 21) | (location << 16) | 0x08000000;
|
||||
iowrite32(value, ioaddr + CSR10);
|
||||
|
||||
while(--i > 0) {
|
||||
mdio_delay();
|
||||
if(ioread32(ioaddr + CSR10) & 0x10000000)
|
||||
break;
|
||||
}
|
||||
retval = ioread32(ioaddr + CSR10);
|
||||
spin_unlock_irqrestore(&tp->mii_lock, flags);
|
||||
return retval & 0xFFFF;
|
||||
}
|
||||
/* Establish sync by sending at least 32 logic ones. */
|
||||
for (i = 32; i >= 0; i--) {
|
||||
iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
|
||||
|
|
@ -159,23 +140,6 @@ void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val)
|
|||
spin_unlock_irqrestore(&tp->mii_lock, flags);
|
||||
return;
|
||||
}
|
||||
if (tp->chip_id == ULI526X && tp->revision >= 0x40) {
|
||||
int value;
|
||||
int i = 1000;
|
||||
|
||||
value = ioread32(ioaddr + CSR9);
|
||||
iowrite32(value & 0xFFEFFFFF, ioaddr + CSR9);
|
||||
|
||||
value = (phy_id << 21) | (location << 16) | 0x04000000 | (val & 0xFFFF);
|
||||
iowrite32(value, ioaddr + CSR10);
|
||||
|
||||
while(--i > 0) {
|
||||
if (ioread32(ioaddr + CSR10) & 0x10000000)
|
||||
break;
|
||||
}
|
||||
spin_unlock_irqrestore(&tp->mii_lock, flags);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Establish sync by sending 32 logic ones. */
|
||||
for (i = 32; i >= 0; i--) {
|
||||
|
|
|
|||
|
|
@ -39,7 +39,6 @@ void tulip_timer(unsigned long data)
|
|||
case MX98713:
|
||||
case COMPEX9881:
|
||||
case DM910X:
|
||||
case ULI526X:
|
||||
default: {
|
||||
struct medialeaf *mleaf;
|
||||
unsigned char *p;
|
||||
|
|
|
|||
|
|
@ -88,7 +88,6 @@ enum chips {
|
|||
I21145,
|
||||
DM910X,
|
||||
CONEXANT,
|
||||
ULI526X
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -482,11 +481,8 @@ static inline void tulip_stop_rxtx(struct tulip_private *tp)
|
|||
|
||||
static inline void tulip_restart_rxtx(struct tulip_private *tp)
|
||||
{
|
||||
if(!(tp->chip_id == ULI526X &&
|
||||
(tp->revision == 0x40 || tp->revision == 0x50))) {
|
||||
tulip_stop_rxtx(tp);
|
||||
udelay(5);
|
||||
}
|
||||
tulip_stop_rxtx(tp);
|
||||
udelay(5);
|
||||
tulip_start_rxtx(tp);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -199,9 +199,6 @@ struct tulip_chip_table tulip_tbl[] = {
|
|||
{ "Conexant LANfinity", 256, 0x0001ebef,
|
||||
HAS_MII | HAS_ACPI, tulip_timer },
|
||||
|
||||
/* ULi526X */
|
||||
{ "ULi M5261/M5263", 128, 0x0001ebef,
|
||||
HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI, tulip_timer },
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -239,8 +236,6 @@ static struct pci_device_id tulip_pci_tbl[] = {
|
|||
{ 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
|
||||
{ 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
|
||||
{ 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
|
||||
{ 0x10b9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ULI526X }, /* ALi 1563 integrated ethernet */
|
||||
{ 0x10b9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ULI526X }, /* ALi 1563 integrated ethernet */
|
||||
{ 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
|
||||
{ 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
|
||||
{ } /* terminate list */
|
||||
|
|
@ -522,7 +517,7 @@ static void tulip_tx_timeout(struct net_device *dev)
|
|||
dev->name);
|
||||
} else if (tp->chip_id == DC21140 || tp->chip_id == DC21142
|
||||
|| tp->chip_id == MX98713 || tp->chip_id == COMPEX9881
|
||||
|| tp->chip_id == DM910X || tp->chip_id == ULI526X) {
|
||||
|| tp->chip_id == DM910X) {
|
||||
printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, "
|
||||
"SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n",
|
||||
dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
|
||||
|
|
@ -1103,18 +1098,16 @@ static void set_rx_mode(struct net_device *dev)
|
|||
entry = tp->cur_tx++ % TX_RING_SIZE;
|
||||
|
||||
if (entry != 0) {
|
||||
/* Avoid a chip errata by prefixing a dummy entry. Don't do
|
||||
this on the ULI526X as it triggers a different problem */
|
||||
if (!(tp->chip_id == ULI526X && (tp->revision == 0x40 || tp->revision == 0x50))) {
|
||||
tp->tx_buffers[entry].skb = NULL;
|
||||
tp->tx_buffers[entry].mapping = 0;
|
||||
tp->tx_ring[entry].length =
|
||||
(entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
|
||||
tp->tx_ring[entry].buffer1 = 0;
|
||||
/* Must set DescOwned later to avoid race with chip */
|
||||
dummy = entry;
|
||||
entry = tp->cur_tx++ % TX_RING_SIZE;
|
||||
}
|
||||
/* Avoid a chip errata by prefixing a dummy entry. */
|
||||
tp->tx_buffers[entry].skb = NULL;
|
||||
tp->tx_buffers[entry].mapping = 0;
|
||||
tp->tx_ring[entry].length =
|
||||
(entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
|
||||
tp->tx_ring[entry].buffer1 = 0;
|
||||
/* Must set DescOwned later to avoid race with chip */
|
||||
dummy = entry;
|
||||
entry = tp->cur_tx++ % TX_RING_SIZE;
|
||||
|
||||
}
|
||||
|
||||
tp->tx_buffers[entry].skb = NULL;
|
||||
|
|
@ -1235,10 +1228,6 @@ static int tulip_uli_dm_quirk(struct pci_dev *pdev)
|
|||
{
|
||||
if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
|
||||
return 1;
|
||||
if (pdev->vendor == 0x10b9 && pdev->device == 0x5261)
|
||||
return 1;
|
||||
if (pdev->vendor == 0x10b9 && pdev->device == 0x5263)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1680,7 +1669,6 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
|
|||
switch (chip_idx) {
|
||||
case DC21140:
|
||||
case DM910X:
|
||||
case ULI526X:
|
||||
default:
|
||||
if (tp->mtable)
|
||||
iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -2145,6 +2145,7 @@
|
|||
#define PCI_DEVICE_ID_ENE_1225 0x1225
|
||||
#define PCI_DEVICE_ID_ENE_1410 0x1410
|
||||
#define PCI_DEVICE_ID_ENE_1420 0x1420
|
||||
#define PCI_VENDOR_ID_CHELSIO 0x1425
|
||||
|
||||
#define PCI_VENDOR_ID_SYBA 0x1592
|
||||
#define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782
|
||||
|
|
|
|||
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