ARM: S3C24XX: move s3c2443 irq code to irq.c
Prequisite for further optimizations. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Heiko Stuebner
Kukjin Kim
Родитель
20f6c781c7
Коммит
6b6289171b
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@ -39,7 +39,7 @@ obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o
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obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
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obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
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obj-$(CONFIG_CPU_S3C2443) += s3c2443.o irq-s3c2443.o clock-s3c2443.o
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obj-$(CONFIG_CPU_S3C2443) += s3c2443.o clock-s3c2443.o
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# PM
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@ -1,281 +0,0 @@
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/* linux/arch/arm/mach-s3c2443/irq.c
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*
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* Copyright (c) 2007 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <mach/regs-irq.h>
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#include <mach/regs-gpio.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include <plat/irq.h>
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#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
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static inline void s3c2443_irq_demux(unsigned int irq, unsigned int len)
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{
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unsigned int subsrc, submsk;
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unsigned int end;
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/* read the current pending interrupts, and the mask
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* for what it is available */
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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subsrc >>= (irq - S3C2410_IRQSUB(0));
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subsrc &= (1 << len)-1;
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end = len + irq;
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for (; irq < end && subsrc; irq++) {
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if (subsrc & 1)
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generic_handle_irq(irq);
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subsrc >>= 1;
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}
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}
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/* WDT/AC97 sub interrupts */
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static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
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{
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s3c2443_irq_demux(IRQ_S3C2443_WDT, 4);
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}
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#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
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#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
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static void s3c2443_irq_wdtac97_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
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}
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static void s3c2443_irq_wdtac97_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
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}
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static void s3c2443_irq_wdtac97_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
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}
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static struct irq_chip s3c2443_irq_wdtac97 = {
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.irq_mask = s3c2443_irq_wdtac97_mask,
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.irq_unmask = s3c2443_irq_wdtac97_unmask,
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.irq_ack = s3c2443_irq_wdtac97_ack,
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};
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/* LCD sub interrupts */
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static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
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{
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s3c2443_irq_demux(IRQ_S3C2443_LCD1, 4);
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}
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#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
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#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
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static void s3c2443_irq_lcd_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
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}
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static void s3c2443_irq_lcd_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_LCD);
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}
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static void s3c2443_irq_lcd_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
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}
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static struct irq_chip s3c2443_irq_lcd = {
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.irq_mask = s3c2443_irq_lcd_mask,
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.irq_unmask = s3c2443_irq_lcd_unmask,
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.irq_ack = s3c2443_irq_lcd_ack,
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};
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/* DMA sub interrupts */
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static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
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{
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s3c2443_irq_demux(IRQ_S3C2443_DMA0, 6);
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}
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#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
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#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
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static void s3c2443_irq_dma_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
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}
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static void s3c2443_irq_dma_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_DMA);
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}
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static void s3c2443_irq_dma_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
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}
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static struct irq_chip s3c2443_irq_dma = {
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.irq_mask = s3c2443_irq_dma_mask,
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.irq_unmask = s3c2443_irq_dma_unmask,
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.irq_ack = s3c2443_irq_dma_ack,
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};
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/* UART3 sub interrupts */
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static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
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{
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s3c2443_irq_demux(IRQ_S3C2443_RX3, 3);
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}
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#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
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#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
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static void s3c2443_irq_uart3_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
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}
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static void s3c2443_irq_uart3_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_UART3);
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}
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static void s3c2443_irq_uart3_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
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}
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static struct irq_chip s3c2443_irq_uart3 = {
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.irq_mask = s3c2443_irq_uart3_mask,
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.irq_unmask = s3c2443_irq_uart3_unmask,
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.irq_ack = s3c2443_irq_uart3_ack,
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};
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/* CAM sub interrupts */
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static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
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{
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s3c2443_irq_demux(IRQ_S3C2440_CAM_C, 4);
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}
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#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
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#define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P)
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static void s3c2443_irq_cam_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM);
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}
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static void s3c2443_irq_cam_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_CAM);
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}
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static void s3c2443_irq_cam_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM);
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}
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static struct irq_chip s3c2443_irq_cam = {
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.irq_mask = s3c2443_irq_cam_mask,
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.irq_unmask = s3c2443_irq_cam_unmask,
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.irq_ack = s3c2443_irq_cam_ack,
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};
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/* IRQ initialisation code */
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static int s3c2443_add_sub(unsigned int base,
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void (*demux)(unsigned int,
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struct irq_desc *),
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struct irq_chip *chip,
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unsigned int start, unsigned int end)
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{
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unsigned int irqno;
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irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
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irq_set_chained_handler(base, demux);
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for (irqno = start; irqno <= end; irqno++) {
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irq_set_chip_and_handler(irqno, chip, handle_level_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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return 0;
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}
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static int s3c2443_irq_add(struct device *dev,
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struct subsys_interface *sif)
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{
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printk("S3C2443: IRQ Support\n");
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s3c2443_add_sub(IRQ_CAM, s3c2443_irq_demux_cam, &s3c2443_irq_cam,
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IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P);
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s3c2443_add_sub(IRQ_LCD, s3c2443_irq_demux_lcd, &s3c2443_irq_lcd,
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IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4);
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s3c2443_add_sub(IRQ_S3C2443_DMA, s3c2443_irq_demux_dma,
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&s3c2443_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
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s3c2443_add_sub(IRQ_S3C2443_UART3, s3c2443_irq_demux_uart3,
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&s3c2443_irq_uart3,
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IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
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s3c2443_add_sub(IRQ_WDT, s3c2443_irq_demux_wdtac97,
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&s3c2443_irq_wdtac97,
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IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
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return 0;
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}
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static struct subsys_interface s3c2443_irq_interface = {
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.name = "s3c2443_irq",
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.subsys = &s3c2443_subsys,
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.add_dev = s3c2443_irq_add,
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};
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static int __init s3c2443_irq_init(void)
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{
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return subsys_interface_register(&s3c2443_irq_interface);
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}
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arch_initcall(s3c2443_irq_init);
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@ -730,3 +730,246 @@ void __init s3c2416_init_irq(void)
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}
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#endif
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#ifdef CONFIG_CPU_S3C2443
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#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
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static inline void s3c2443_irq_demux(unsigned int irq, unsigned int len)
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{
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unsigned int subsrc, submsk;
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unsigned int end;
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/* read the current pending interrupts, and the mask
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* for what it is available */
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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subsrc >>= (irq - S3C2410_IRQSUB(0));
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subsrc &= (1 << len)-1;
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end = len + irq;
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for (; irq < end && subsrc; irq++) {
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if (subsrc & 1)
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generic_handle_irq(irq);
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subsrc >>= 1;
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}
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}
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/* WDT/AC97 sub interrupts */
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static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
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{
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s3c2443_irq_demux(IRQ_S3C2443_WDT, 4);
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}
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#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
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#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
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static void s3c2443_irq_wdtac97_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
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}
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static void s3c2443_irq_wdtac97_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
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}
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static void s3c2443_irq_wdtac97_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
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}
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static struct irq_chip s3c2443_irq_wdtac97 = {
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.irq_mask = s3c2443_irq_wdtac97_mask,
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.irq_unmask = s3c2443_irq_wdtac97_unmask,
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.irq_ack = s3c2443_irq_wdtac97_ack,
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};
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/* LCD sub interrupts */
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static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
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{
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s3c2443_irq_demux(IRQ_S3C2443_LCD1, 4);
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}
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#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
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#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
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static void s3c2443_irq_lcd_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
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}
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static void s3c2443_irq_lcd_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_LCD);
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}
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static void s3c2443_irq_lcd_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
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}
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static struct irq_chip s3c2443_irq_lcd = {
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.irq_mask = s3c2443_irq_lcd_mask,
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.irq_unmask = s3c2443_irq_lcd_unmask,
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.irq_ack = s3c2443_irq_lcd_ack,
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};
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/* DMA sub interrupts */
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static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
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{
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s3c2443_irq_demux(IRQ_S3C2443_DMA0, 6);
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}
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#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
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#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
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static void s3c2443_irq_dma_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
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}
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static void s3c2443_irq_dma_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_DMA);
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}
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static void s3c2443_irq_dma_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
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}
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static struct irq_chip s3c2443_irq_dma = {
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.irq_mask = s3c2443_irq_dma_mask,
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.irq_unmask = s3c2443_irq_dma_unmask,
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.irq_ack = s3c2443_irq_dma_ack,
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};
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/* UART3 sub interrupts */
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|
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static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
s3c2443_irq_demux(IRQ_S3C2443_RX3, 3);
|
||||
}
|
||||
|
||||
#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
|
||||
#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
|
||||
|
||||
static void s3c2443_irq_uart3_mask(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
|
||||
}
|
||||
|
||||
static void s3c2443_irq_uart3_unmask(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_unmask(data->irq, INTMSK_UART3);
|
||||
}
|
||||
|
||||
static void s3c2443_irq_uart3_ack(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
|
||||
}
|
||||
|
||||
static struct irq_chip s3c2443_irq_uart3 = {
|
||||
.irq_mask = s3c2443_irq_uart3_mask,
|
||||
.irq_unmask = s3c2443_irq_uart3_unmask,
|
||||
.irq_ack = s3c2443_irq_uart3_ack,
|
||||
};
|
||||
|
||||
/* CAM sub interrupts */
|
||||
|
||||
static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
s3c2443_irq_demux(IRQ_S3C2440_CAM_C, 4);
|
||||
}
|
||||
|
||||
#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
|
||||
#define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P)
|
||||
|
||||
static void s3c2443_irq_cam_mask(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM);
|
||||
}
|
||||
|
||||
static void s3c2443_irq_cam_unmask(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_unmask(data->irq, INTMSK_CAM);
|
||||
}
|
||||
|
||||
static void s3c2443_irq_cam_ack(struct irq_data *data)
|
||||
{
|
||||
s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM);
|
||||
}
|
||||
|
||||
static struct irq_chip s3c2443_irq_cam = {
|
||||
.irq_mask = s3c2443_irq_cam_mask,
|
||||
.irq_unmask = s3c2443_irq_cam_unmask,
|
||||
.irq_ack = s3c2443_irq_cam_ack,
|
||||
};
|
||||
|
||||
/* IRQ initialisation code */
|
||||
|
||||
static int s3c2443_add_sub(unsigned int base,
|
||||
void (*demux)(unsigned int,
|
||||
struct irq_desc *),
|
||||
struct irq_chip *chip,
|
||||
unsigned int start, unsigned int end)
|
||||
{
|
||||
unsigned int irqno;
|
||||
|
||||
irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
|
||||
irq_set_chained_handler(base, demux);
|
||||
|
||||
for (irqno = start; irqno <= end; irqno++) {
|
||||
irq_set_chip_and_handler(irqno, chip, handle_level_irq);
|
||||
set_irq_flags(irqno, IRQF_VALID);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s3c2443_irq_add(struct device *dev,
|
||||
struct subsys_interface *sif)
|
||||
{
|
||||
printk("S3C2443: IRQ Support\n");
|
||||
|
||||
s3c2443_add_sub(IRQ_CAM, s3c2443_irq_demux_cam, &s3c2443_irq_cam,
|
||||
IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P);
|
||||
|
||||
s3c2443_add_sub(IRQ_LCD, s3c2443_irq_demux_lcd, &s3c2443_irq_lcd,
|
||||
IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4);
|
||||
|
||||
s3c2443_add_sub(IRQ_S3C2443_DMA, s3c2443_irq_demux_dma,
|
||||
&s3c2443_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
|
||||
|
||||
s3c2443_add_sub(IRQ_S3C2443_UART3, s3c2443_irq_demux_uart3,
|
||||
&s3c2443_irq_uart3,
|
||||
IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
|
||||
|
||||
s3c2443_add_sub(IRQ_WDT, s3c2443_irq_demux_wdtac97,
|
||||
&s3c2443_irq_wdtac97,
|
||||
IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct subsys_interface s3c2443_irq_interface = {
|
||||
.name = "s3c2443_irq",
|
||||
.subsys = &s3c2443_subsys,
|
||||
.add_dev = s3c2443_irq_add,
|
||||
};
|
||||
|
||||
static int __init s3c2443_irq_init(void)
|
||||
{
|
||||
return subsys_interface_register(&s3c2443_irq_interface);
|
||||
}
|
||||
|
||||
arch_initcall(s3c2443_irq_init);
|
||||
#endif
|
||||
|
|
|
|||
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