drm: rcar-du: lvds: Add R-Car Gen3 support
The LVDS encoder differs slightly in Gen3 SoCs in its PLL configuration. Add support for the Gen3 LVDS PLL parameters and startup procedure. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
Koji Matsuoka
Laurent Pinchart
Родитель
82e7c5e496
Коммит
6bc2e15cf2
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@ -21,10 +21,8 @@ config DRM_RCAR_HDMI
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config DRM_RCAR_LVDS
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bool "R-Car DU LVDS Encoder Support"
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depends on DRM_RCAR_DU
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depends on ARCH_R8A7790 || ARCH_R8A7791 || COMPILE_TEST
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help
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Enable support for the R-Car Display Unit embedded LVDS encoders
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(currently only on R8A7790 and R8A7791).
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Enable support for the R-Car Display Unit embedded LVDS encoders.
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config DRM_RCAR_VSP
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bool "R-Car DU VSP Compositor Support"
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@ -140,15 +140,21 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
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| RCAR_DU_FEATURE_VSP1_SOURCE,
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.num_crtcs = 4,
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.routes = {
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/* R8A7795 has one RGB output, and two HDMI and one LVDS
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* (currently unsupported) outputs
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/* R8A7795 has one RGB output, one LVDS output and two
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* (currently unsupported) HDMI outputs.
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*/
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[RCAR_DU_OUTPUT_DPAD0] = {
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.possible_crtcs = BIT(3),
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.encoder_type = DRM_MODE_ENCODER_NONE,
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.port = 0,
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},
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[RCAR_DU_OUTPUT_LVDS0] = {
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.possible_crtcs = BIT(0),
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.encoder_type = DRM_MODE_ENCODER_LVDS,
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.port = 3,
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},
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},
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.num_lvds = 1,
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};
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static const struct of_device_id rcar_du_of_table[] = {
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@ -38,22 +38,13 @@ static void rcar_lvds_write(struct rcar_du_lvdsenc *lvds, u32 reg, u32 data)
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iowrite32(data, lvds->mmio + reg);
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}
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static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
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struct rcar_du_crtc *rcrtc)
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static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds,
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struct rcar_du_crtc *rcrtc)
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{
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const struct drm_display_mode *mode = &rcrtc->crtc.mode;
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unsigned int freq = mode->clock;
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u32 lvdcr0;
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u32 lvdhcr;
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u32 pllcr;
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int ret;
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if (lvds->enabled)
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return 0;
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ret = clk_prepare_enable(lvds->clock);
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if (ret < 0)
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return ret;
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/* PLL clock configuration */
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if (freq < 39000)
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@ -67,6 +58,86 @@ static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
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rcar_lvds_write(lvds, LVDPLLCR, pllcr);
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/* Select the input, hardcode mode 0, enable LVDS operation and turn
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* bias circuitry on.
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*/
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lvdcr0 = LVDCR0_BEN | LVDCR0_LVEN;
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if (rcrtc->index == 2)
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lvdcr0 |= LVDCR0_DUSEL;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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/* Turn all the channels on. */
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rcar_lvds_write(lvds, LVDCR1,
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LVDCR1_CHSTBY_GEN2(3) | LVDCR1_CHSTBY_GEN2(2) |
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LVDCR1_CHSTBY_GEN2(1) | LVDCR1_CHSTBY_GEN2(0) |
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LVDCR1_CLKSTBY_GEN2);
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/* Turn the PLL on, wait for the startup delay, and turn the output
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* on.
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*/
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lvdcr0 |= LVDCR0_PLLON;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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usleep_range(100, 150);
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lvdcr0 |= LVDCR0_LVRES;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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}
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static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds,
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struct rcar_du_crtc *rcrtc)
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{
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const struct drm_display_mode *mode = &rcrtc->crtc.mode;
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unsigned int freq = mode->clock;
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u32 lvdcr0;
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u32 pllcr;
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/* PLL clock configuration */
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if (freq < 42000)
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pllcr = LVDPLLCR_PLLDIVCNT_42M;
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else if (freq < 85000)
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pllcr = LVDPLLCR_PLLDIVCNT_85M;
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else if (freq < 128000)
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pllcr = LVDPLLCR_PLLDIVCNT_128M;
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else
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pllcr = LVDPLLCR_PLLDIVCNT_148M;
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rcar_lvds_write(lvds, LVDPLLCR, pllcr);
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/* Turn the PLL on, set it to LVDS normal mode, wait for the startup
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* delay and turn the output on.
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*/
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lvdcr0 = LVDCR0_PLLON;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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lvdcr0 |= LVDCR0_PWD;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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usleep_range(100, 150);
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lvdcr0 |= LVDCR0_LVRES;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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/* Turn all the channels on. */
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rcar_lvds_write(lvds, LVDCR1,
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LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) |
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LVDCR1_CHSTBY_GEN3(1) | LVDCR1_CHSTBY_GEN3(0) |
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LVDCR1_CLKSTBY_GEN3);
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}
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static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
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struct rcar_du_crtc *rcrtc)
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{
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u32 lvdhcr;
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int ret;
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if (lvds->enabled)
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return 0;
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ret = clk_prepare_enable(lvds->clock);
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if (ret < 0)
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return ret;
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/* Hardcode the channels and control signals routing for now.
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*
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* HSYNC -> CTRL0
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@ -87,30 +158,14 @@ static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
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rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
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/* Select the input, hardcode mode 0, enable LVDS operation and turn
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* bias circuitry on.
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*/
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lvdcr0 = LVDCR0_BEN | LVDCR0_LVEN;
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if (rcrtc->index == 2)
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lvdcr0 |= LVDCR0_DUSEL;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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/* Turn all the channels on. */
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rcar_lvds_write(lvds, LVDCR1, LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
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LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
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/* Turn the PLL on, wait for the startup delay, and turn the output
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* on.
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*/
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lvdcr0 |= LVDCR0_PLLON;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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usleep_range(100, 150);
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lvdcr0 |= LVDCR0_LVRES;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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/* Perform generation-specific initialization. */
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if (lvds->dev->info->gen < 3)
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rcar_du_lvdsenc_start_gen2(lvds, rcrtc);
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else
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rcar_du_lvdsenc_start_gen3(lvds, rcrtc);
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lvds->enabled = true;
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return 0;
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}
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@ -143,10 +198,16 @@ int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, struct drm_crtc *crtc,
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void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds,
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struct drm_display_mode *mode)
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{
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/* The internal LVDS encoder has a clock frequency operating range of
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* 30MHz to 150MHz. Clamp the clock accordingly.
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struct rcar_du_device *rcdu = lvds->dev;
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/* The internal LVDS encoder has a restricted clock frequency operating
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* range (30MHz to 150MHz on Gen2, 25.175MHz to 148.5MHz on Gen3). Clamp
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* the clock accordingly.
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*/
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mode->clock = clamp(mode->clock, 30000, 150000);
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if (rcdu->info->gen < 3)
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mode->clock = clamp(mode->clock, 30000, 150000);
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else
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mode->clock = clamp(mode->clock, 25175, 148500);
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}
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static int rcar_du_lvdsenc_get_resources(struct rcar_du_lvdsenc *lvds,
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@ -1,7 +1,7 @@
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/*
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* rcar_lvds_regs.h -- R-Car LVDS Interface Registers Definitions
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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@ -15,28 +15,38 @@
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#define LVDCR0 0x0000
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#define LVDCR0_DUSEL (1 << 15)
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#define LVDCR0_DMD (1 << 12)
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#define LVDCR0_DMD (1 << 12) /* Gen2 only */
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#define LVDCR0_LVMD_MASK (0xf << 8)
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#define LVDCR0_LVMD_SHIFT 8
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#define LVDCR0_PLLON (1 << 4)
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#define LVDCR0_BEN (1 << 2)
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#define LVDCR0_LVEN (1 << 1)
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#define LVDCR0_PWD (1 << 2) /* Gen3 only */
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#define LVDCR0_BEN (1 << 2) /* Gen2 only */
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#define LVDCR0_LVEN (1 << 1) /* Gen2 only */
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#define LVDCR0_LVRES (1 << 0)
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#define LVDCR1 0x0004
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#define LVDCR1_CKSEL (1 << 15)
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#define LVDCR1_CHSTBY(n) (3 << (2 + (n) * 2))
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#define LVDCR1_CLKSTBY (3 << 0)
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#define LVDCR1_CKSEL (1 << 15) /* Gen2 only */
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#define LVDCR1_CHSTBY_GEN2(n) (3 << (2 + (n) * 2)) /* Gen2 only */
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#define LVDCR1_CHSTBY_GEN3(n) (1 << (2 + (n) * 2)) /* Gen3 only */
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#define LVDCR1_CLKSTBY_GEN2 (3 << 0) /* Gen2 only */
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#define LVDCR1_CLKSTBY_GEN3 (1 << 0) /* Gen3 only */
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#define LVDPLLCR 0x0008
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#define LVDPLLCR_CEEN (1 << 14)
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#define LVDPLLCR_FBEN (1 << 13)
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#define LVDPLLCR_COSEL (1 << 12)
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/* Gen2 */
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#define LVDPLLCR_PLLDLYCNT_150M (0x1bf << 0)
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#define LVDPLLCR_PLLDLYCNT_121M (0x22c << 0)
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#define LVDPLLCR_PLLDLYCNT_60M (0x77b << 0)
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#define LVDPLLCR_PLLDLYCNT_38M (0x69a << 0)
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#define LVDPLLCR_PLLDLYCNT_MASK (0x7ff << 0)
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/* Gen3 */
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#define LVDPLLCR_PLLDIVCNT_42M (0x014cb << 0)
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#define LVDPLLCR_PLLDIVCNT_85M (0x00a45 << 0)
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#define LVDPLLCR_PLLDIVCNT_128M (0x006c3 << 0)
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#define LVDPLLCR_PLLDIVCNT_148M (0x046c1 << 0)
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#define LVDPLLCR_PLLDIVCNT_MASK (0x7ffff << 0)
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#define LVDCTRCR 0x000c
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#define LVDCTRCR_CTR3SEL_ZERO (0 << 12)
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