[POWERPC] 83xx: Add device tree source for Wind River SBC834x board.
This adds the device tree source for the Wind River SBC834x board. It is based on the MPC834x_MDS DTS, with the biggest difference being the lack of BCSR and the PCI2 that the MDS gets via the PIB. That, and this file is also dts-v1 format. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Paul Gortmaker
Kumar Gala
Родитель
a43414ccb4
Коммит
6c538111e3
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/*
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* SBC8349E Device Tree Source
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*
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* Copyright 2007 Wind River Inc.
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*
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* Paul Gortmaker (see MAINTAINERS for contact information)
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*
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* -based largely on the Freescale MPC834x_MDS dts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "SBC8349E";
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compatible = "SBC834xE";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8349@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <0x20>; // 32 bytes
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i-cache-line-size = <0x20>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>; // from bootloader
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bus-frequency = <0>; // from bootloader
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clock-frequency = <0>; // from bootloader
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; // 256MB at 0
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};
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soc8349@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0x0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>;
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wdt@200 {
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compatible = "mpc83xx_wdt";
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reg = <0x200 0x100>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <0xe 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <0xf 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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};
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spi@7000 {
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compatible = "fsl_spi";
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reg = <0x7000 0x1000>;
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interrupts = <0x10 0x8>;
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interrupt-parent = <&ipic>;
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mode = "cpu";
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};
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/* phy type (ULPI or SERIAL) are only types supported for MPH */
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/* port = 0 or 1 */
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usb@22000 {
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compatible = "fsl-usb2-mph";
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reg = <0x22000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&ipic>;
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interrupts = <0x27 0x8>;
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phy_type = "ulpi";
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port1;
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};
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/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
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usb@23000 {
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device_type = "usb";
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compatible = "fsl-usb2-dr";
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reg = <0x23000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&ipic>;
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interrupts = <0x26 0x8>;
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dr_mode = "otg";
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phy_type = "ulpi";
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x24520 0x20>;
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phy0: ethernet-phy@19 {
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interrupt-parent = <&ipic>;
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interrupts = <0x14 0x8>;
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reg = <0x19>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1a {
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interrupt-parent = <&ipic>;
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interrupts = <0x15 0x8>;
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reg = <0x1a>;
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device_type = "ethernet-phy";
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};
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};
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enet0: ethernet@24000 {
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cell-index = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
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interrupt-parent = <&ipic>;
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phy-handle = <&phy0>;
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linux,network-index = <0>;
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};
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enet1: ethernet@25000 {
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cell-index = <1>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
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interrupt-parent = <&ipic>;
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phy-handle = <&phy1>;
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linux,network-index = <1>;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <0x9 0x8>;
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interrupt-parent = <&ipic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <0xa 0x8>;
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interrupt-parent = <&ipic>;
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};
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/* May need to remove if on a part without crypto engine */
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crypto@30000 {
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model = "SEC2";
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compatible = "talitos";
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reg = <0x30000 0x10000>;
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interrupts = <0xb 0x8>;
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interrupt-parent = <&ipic>;
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num-channels = <4>;
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channel-fifo-len = <0x18>;
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exec-units-mask = <0x0000007e>;
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/* desc mask is for rev2.0,
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* we need runtime fixup for >2.0 */
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descriptor-types-mask = <0x01010ebf>;
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};
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/* IPIC
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* interrupts cell = <intr #, sense>
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* sense values match linux IORESOURCE_IRQ_* defines:
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* sense == 8: Level, low assertion
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* sense == 2: Edge, high-to-low change
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*/
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ipic: pic@700 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x700 0x100>;
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device_type = "ipic";
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};
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};
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pci0: pci@e0008500 {
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cell-index = <1>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x11 */
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0x8800 0x0 0x0 0x1 &ipic 0x14 0x8
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0x8800 0x0 0x0 0x2 &ipic 0x15 0x8
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0x8800 0x0 0x0 0x3 &ipic 0x16 0x8
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0x8800 0x0 0x0 0x4 &ipic 0x17 0x8>;
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interrupt-parent = <&ipic>;
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interrupts = <0x42 0x8>;
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bus-range = <0 0>;
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ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
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0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
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clock-frequency = <66666666>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008500 0x100>;
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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};
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