x86: make amd.c have 64bit support code
Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Yinghai Lu
Ingo Molnar
Родитель
8d71a2ea0a
Коммит
6c62aa4a3c
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@ -16,6 +16,7 @@
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#include "cpu.h"
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#ifdef CONFIG_X86_32
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/*
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* B step AMD K6 before B 9730xxxx have hardware bugs that can cause
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* misexecution of code under Linux. Owners of such processors should
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@ -177,6 +178,26 @@ static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_K7);
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}
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#endif
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#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
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static int __cpuinit nearby_node(int apicid)
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{
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int i, node;
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for (i = apicid - 1; i >= 0; i--) {
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node = apicid_to_node[i];
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if (node != NUMA_NO_NODE && node_online(node))
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return node;
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}
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for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
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node = apicid_to_node[i];
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if (node != NUMA_NO_NODE && node_online(node))
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return node;
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}
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return first_node(node_online_map); /* Shouldn't happen */
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}
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#endif
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/*
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* On a AMD dual core setup the lower bits of the APIC id distingush the cores.
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@ -196,6 +217,42 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
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#endif
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}
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static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
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{
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#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
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int cpu = smp_processor_id();
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int node;
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unsigned apicid = hard_smp_processor_id();
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node = c->phys_proc_id;
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if (apicid_to_node[apicid] != NUMA_NO_NODE)
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node = apicid_to_node[apicid];
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if (!node_online(node)) {
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/* Two possibilities here:
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- The CPU is missing memory and no node was created.
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In that case try picking one from a nearby CPU
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- The APIC IDs differ from the HyperTransport node IDs
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which the K8 northbridge parsing fills in.
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Assume they are all increased by a constant offset,
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but in the same order as the HT nodeids.
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If that doesn't result in a usable node fall back to the
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path for the previous case. */
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int ht_nodeid = c->initial_apicid;
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if (ht_nodeid >= 0 &&
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apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
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node = apicid_to_node[ht_nodeid];
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/* Pick a nearby node */
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if (!node_online(node))
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node = nearby_node(apicid);
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}
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numa_set_node(cpu, node);
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printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
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#endif
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}
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static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_HT
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@ -226,13 +283,19 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
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{
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early_init_amd_mc(c);
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/* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
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if (c->x86_power & (1<<8))
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_SYSCALL32);
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#else
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/* Set MTRR capability flag if appropriate */
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if (c->x86_model == 13 || c->x86_model == 9 ||
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(c->x86_model == 8 && c->x86_mask >= 8))
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set_cpu_cap(c, X86_FEATURE_K6_MTRR);
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if (c->x86 == 5)
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if (c->x86_model == 13 || c->x86_model == 9 ||
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(c->x86_model == 8 && c->x86_mask >= 8))
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set_cpu_cap(c, X86_FEATURE_K6_MTRR);
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#endif
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}
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static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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@ -256,18 +319,31 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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early_init_amd(c);
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/*
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* FIXME: We should handle the K5 here. Set up the write
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* range and also turn on MSR 83 bits 4 and 31 (write alloc,
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* no bus pipeline)
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*/
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/*
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* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
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*/
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clear_cpu_cap(c, 0*32+31);
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#ifdef CONFIG_X86_64
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/* On C+ stepping K8 rep microcode works well for copy/memset */
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if (c->x86 == 0xf) {
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u32 level;
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level = cpuid_eax(1);
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if((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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}
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if (c->x86 == 0x10 || c->x86 == 0x11)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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#else
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/*
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* FIXME: We should handle the K5 here. Set up the write
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* range and also turn on MSR 83 bits 4 and 31 (write alloc,
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* no bus pipeline)
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*/
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switch (c->x86) {
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case 4:
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init_amd_k5(c);
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@ -283,7 +359,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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/* K6s reports MCEs but don't actually have all the MSRs */
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if (c->x86 < 6)
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clear_cpu_cap(c, X86_FEATURE_MCE);
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#endif
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/* Enable workaround for FXSAVE leak */
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if (c->x86 >= 6)
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set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
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@ -300,10 +378,14 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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display_cacheinfo(c);
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/* Multi core CPU? */
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if (c->extended_cpuid_level >= 0x80000008)
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if (c->extended_cpuid_level >= 0x80000008) {
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amd_detect_cmp(c);
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srat_detect_node(c);
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}
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#ifdef CONFIG_X86_32
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detect_ht(c);
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#endif
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if (c->extended_cpuid_level >= 0x80000006) {
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if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000))
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@ -319,8 +401,38 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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/* MFENCE stops RDTSC speculation */
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set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
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}
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#ifdef CONFIG_X86_64
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if (c->x86 == 0x10) {
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/* do this for boot cpu */
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if (c == &boot_cpu_data)
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check_enable_amd_mmconf_dmi();
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fam10h_check_enable_mmcfg();
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}
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if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
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unsigned long long tseg;
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/*
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* Split up direct mapping around the TSEG SMM area.
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* Don't do it for gbpages because there seems very little
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* benefit in doing so.
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*/
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if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
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printk(KERN_DEBUG "tseg: %010llx\n", tseg);
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if ((tseg>>PMD_SHIFT) <
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(max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) ||
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((tseg>>PMD_SHIFT) <
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(max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
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(tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
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set_memory_4k((unsigned long)__va(tseg), 1);
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}
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}
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#endif
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}
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#ifdef CONFIG_X86_32
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static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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{
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/* AMD errata T13 (order #21922) */
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@ -333,10 +445,12 @@ static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int
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}
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return size;
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}
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#endif
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static struct cpu_dev amd_cpu_dev __cpuinitdata = {
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.c_vendor = "AMD",
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.c_ident = { "AuthenticAMD" },
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#ifdef CONFIG_X86_32
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.c_models = {
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{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
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{
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@ -349,9 +463,10 @@ static struct cpu_dev amd_cpu_dev __cpuinitdata = {
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}
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},
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},
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.c_size_cache = amd_size_cache,
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#endif
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.c_early_init = early_init_amd,
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.c_init = init_amd,
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.c_size_cache = amd_size_cache,
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.c_x86_vendor = X86_VENDOR_AMD,
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};
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