crypto: hisilicon/qm - add controller reset interface
Add the main implementation of the controller reset interface, which is roughly divided into three parts, stop, reset, and reinitialization. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Shukun Tan
Herbert Xu
Родитель
35ee280fb1
Коммит
6c6dd5802c
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@ -1,6 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2019 HiSilicon Limited. */
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#include <asm/page.h>
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#include <linux/acpi.h>
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#include <linux/aer.h>
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#include <linux/bitmap.h>
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#include <linux/debugfs.h>
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#include <linux/dma-mapping.h>
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@ -122,9 +124,11 @@
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#define QM_DFX_CNT_CLR_CE 0x100118
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#define QM_ABNORMAL_INT_SOURCE 0x100000
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#define QM_ABNORMAL_INT_SOURCE_CLR GENMASK(12, 0)
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#define QM_ABNORMAL_INT_MASK 0x100004
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#define QM_ABNORMAL_INT_MASK_VALUE 0x1fff
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#define QM_ABNORMAL_INT_STATUS 0x100008
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#define QM_ABNORMAL_INT_SET 0x10000c
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#define QM_ABNORMAL_INF00 0x100010
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#define QM_FIFO_OVERFLOW_TYPE 0xc0
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#define QM_FIFO_OVERFLOW_TYPE_SHIFT 6
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@ -140,6 +144,25 @@
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#define QM_RAS_CE_TIMES_PER_IRQ 1
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#define QM_RAS_MSI_INT_SEL 0x1040f4
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#define QM_DEV_RESET_FLAG 0
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#define QM_RESET_WAIT_TIMEOUT 400
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#define QM_PEH_VENDOR_ID 0x1000d8
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#define ACC_VENDOR_ID_VALUE 0x5a5a
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#define QM_PEH_DFX_INFO0 0x1000fc
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#define ACC_PEH_SRIOV_CTRL_VF_MSE_SHIFT 3
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#define ACC_PEH_MSI_DISABLE GENMASK(31, 0)
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#define ACC_MASTER_GLOBAL_CTRL_SHUTDOWN 0x1
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#define ACC_MASTER_TRANS_RETURN_RW 3
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#define ACC_MASTER_TRANS_RETURN 0x300150
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#define ACC_MASTER_GLOBAL_CTRL 0x300000
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#define ACC_AM_CFG_PORT_WR_EN 0x30001c
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#define QM_RAS_NFE_MBIT_DISABLE ~QM_ECC_MBIT
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#define ACC_AM_ROB_ECC_INT_STS 0x300104
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#define ACC_ROB_ECC_ERR_MULTPL BIT(1)
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#define POLL_PERIOD 10
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#define POLL_TIMEOUT 1000
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#define MAX_WAIT_COUNTS 1000
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#define QM_CACHE_WB_START 0x204
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#define QM_CACHE_WB_DONE 0x208
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@ -1012,10 +1035,18 @@ static void qm_hw_error_init_v2(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
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{
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u32 irq_enable = ce | nfe | fe | msi;
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u32 irq_unmask = ~irq_enable;
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u32 error_status;
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qm->error_mask = ce | nfe | fe;
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qm->msi_mask = msi;
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/* clear QM hw residual error source */
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error_status = readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
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if (error_status) {
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error_status &= qm->error_mask;
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writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE);
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}
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/* configure error type */
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writel(ce, qm->io_base + QM_RAS_CE_ENABLE);
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writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD);
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@ -1080,6 +1111,9 @@ static pci_ers_result_t qm_hw_error_handle_v2(struct hisi_qm *qm)
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error_status = qm->error_mask & tmp;
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if (error_status) {
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if (error_status & QM_ECC_MBIT)
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qm->err_status.is_qm_ecc_mbit = true;
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qm_log_hw_error(qm, error_status);
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/* clear err sts */
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@ -1971,6 +2005,52 @@ int hisi_qm_start(struct hisi_qm *qm)
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}
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EXPORT_SYMBOL_GPL(hisi_qm_start);
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static int qm_restart(struct hisi_qm *qm)
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{
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struct device *dev = &qm->pdev->dev;
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struct hisi_qp *qp;
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int ret, i;
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ret = hisi_qm_start(qm);
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if (ret < 0)
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return ret;
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write_lock(&qm->qps_lock);
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for (i = 0; i < qm->qp_num; i++) {
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qp = qm->qp_array[i];
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if (qp) {
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ret = hisi_qm_start_qp(qp, 0);
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if (ret < 0) {
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dev_err(dev, "Failed to start qp%d!\n", i);
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write_unlock(&qm->qps_lock);
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return ret;
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}
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}
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}
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write_unlock(&qm->qps_lock);
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return 0;
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}
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/**
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* This function clears all queues memory in a qm. Reset of accelerator can
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* use this to clear queues.
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*/
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static void qm_clear_queues(struct hisi_qm *qm)
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{
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struct hisi_qp *qp;
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int i;
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for (i = 0; i < qm->qp_num; i++) {
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qp = qm->qp_array[i];
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if (qp)
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memset(qp->qdma.va, 0, qp->qdma.size);
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}
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memset(qm->qdma.va, 0, qm->qdma.size);
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}
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/**
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* hisi_qm_stop() - Stop a qm.
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* @qm: The qm which will be stopped.
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@ -2014,6 +2094,8 @@ int hisi_qm_stop(struct hisi_qm *qm)
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dev_err(dev, "Failed to set vft!\n");
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}
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qm_clear_queues(qm);
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return ret;
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}
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EXPORT_SYMBOL_GPL(hisi_qm_stop);
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@ -2431,6 +2513,9 @@ static pci_ers_result_t qm_dev_err_handle(struct hisi_qm *qm)
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/* get device hardware error status */
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err_sts = qm->err_ini->get_dev_hw_err_status(qm);
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if (err_sts) {
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if (err_sts & qm->err_ini->err_info.ecc_2bits_mask)
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qm->err_status.is_dev_ecc_mbit = true;
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if (!qm->err_ini->log_dev_hw_err) {
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dev_err(&qm->pdev->dev, "Device doesn't support log hw error!\n");
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return PCI_ERS_RESULT_NEED_RESET;
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@ -2481,6 +2566,465 @@ pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
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}
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EXPORT_SYMBOL_GPL(hisi_qm_dev_err_detected);
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static int qm_check_req_recv(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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int ret;
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u32 val;
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writel(ACC_VENDOR_ID_VALUE, qm->io_base + QM_PEH_VENDOR_ID);
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ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
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(val == ACC_VENDOR_ID_VALUE),
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POLL_PERIOD, POLL_TIMEOUT);
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if (ret) {
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dev_err(&pdev->dev, "Fails to read QM reg!\n");
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return ret;
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}
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writel(PCI_VENDOR_ID_HUAWEI, qm->io_base + QM_PEH_VENDOR_ID);
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ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
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(val == PCI_VENDOR_ID_HUAWEI),
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POLL_PERIOD, POLL_TIMEOUT);
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if (ret)
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dev_err(&pdev->dev, "Fails to read QM reg in the second time!\n");
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return ret;
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}
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static int qm_set_pf_mse(struct hisi_qm *qm, bool set)
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{
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struct pci_dev *pdev = qm->pdev;
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u16 cmd;
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int i;
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pci_read_config_word(pdev, PCI_COMMAND, &cmd);
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if (set)
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cmd |= PCI_COMMAND_MEMORY;
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else
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cmd &= ~PCI_COMMAND_MEMORY;
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pci_write_config_word(pdev, PCI_COMMAND, cmd);
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for (i = 0; i < MAX_WAIT_COUNTS; i++) {
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pci_read_config_word(pdev, PCI_COMMAND, &cmd);
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if (set == ((cmd & PCI_COMMAND_MEMORY) >> 1))
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return 0;
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static int qm_set_vf_mse(struct hisi_qm *qm, bool set)
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{
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struct pci_dev *pdev = qm->pdev;
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u16 sriov_ctrl;
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int pos;
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int i;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
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pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &sriov_ctrl);
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if (set)
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sriov_ctrl |= PCI_SRIOV_CTRL_MSE;
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else
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sriov_ctrl &= ~PCI_SRIOV_CTRL_MSE;
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pci_write_config_word(pdev, pos + PCI_SRIOV_CTRL, sriov_ctrl);
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for (i = 0; i < MAX_WAIT_COUNTS; i++) {
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pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &sriov_ctrl);
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if (set == (sriov_ctrl & PCI_SRIOV_CTRL_MSE) >>
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ACC_PEH_SRIOV_CTRL_VF_MSE_SHIFT)
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return 0;
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static int qm_set_msi(struct hisi_qm *qm, bool set)
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{
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struct pci_dev *pdev = qm->pdev;
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if (set) {
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pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_MASK_64,
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0);
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} else {
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pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_MASK_64,
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ACC_PEH_MSI_DISABLE);
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if (qm->err_status.is_qm_ecc_mbit ||
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qm->err_status.is_dev_ecc_mbit)
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return 0;
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mdelay(1);
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if (readl(qm->io_base + QM_PEH_DFX_INFO0))
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return -EFAULT;
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}
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return 0;
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}
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static int qm_vf_reset_prepare(struct hisi_qm *qm)
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{
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struct hisi_qm_list *qm_list = qm->qm_list;
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struct pci_dev *pdev = qm->pdev;
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struct pci_dev *virtfn;
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struct hisi_qm *vf_qm;
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int ret = 0;
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mutex_lock(&qm_list->lock);
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list_for_each_entry(vf_qm, &qm_list->list, list) {
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virtfn = vf_qm->pdev;
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if (virtfn == pdev)
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continue;
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if (pci_physfn(virtfn) == pdev) {
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ret = hisi_qm_stop(vf_qm);
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if (ret)
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goto stop_fail;
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}
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}
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stop_fail:
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mutex_unlock(&qm_list->lock);
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return ret;
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}
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static int qm_reset_prepare_ready(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
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int delay = 0;
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/* All reset requests need to be queued for processing */
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while (test_and_set_bit(QM_DEV_RESET_FLAG, &pf_qm->reset_flag)) {
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msleep(++delay);
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if (delay > QM_RESET_WAIT_TIMEOUT)
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return -EBUSY;
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}
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return 0;
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}
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static int qm_controller_reset_prepare(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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int ret;
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ret = qm_reset_prepare_ready(qm);
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if (ret) {
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pci_err(pdev, "Controller reset not ready!\n");
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return ret;
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}
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if (qm->vfs_num) {
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ret = qm_vf_reset_prepare(qm);
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if (ret) {
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pci_err(pdev, "Fails to stop VFs!\n");
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return ret;
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}
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}
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ret = hisi_qm_stop(qm);
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if (ret) {
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pci_err(pdev, "Fails to stop QM!\n");
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return ret;
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}
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return 0;
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}
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static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)
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{
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u32 nfe_enb = 0;
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if (!qm->err_status.is_dev_ecc_mbit &&
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qm->err_status.is_qm_ecc_mbit &&
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qm->err_ini->close_axi_master_ooo) {
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qm->err_ini->close_axi_master_ooo(qm);
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} else if (qm->err_status.is_dev_ecc_mbit &&
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!qm->err_status.is_qm_ecc_mbit &&
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!qm->err_ini->close_axi_master_ooo) {
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nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);
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writel(nfe_enb & QM_RAS_NFE_MBIT_DISABLE,
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qm->io_base + QM_RAS_NFE_ENABLE);
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writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);
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}
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}
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static int qm_soft_reset(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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int ret;
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u32 val;
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/* Ensure all doorbells and mailboxes received by QM */
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ret = qm_check_req_recv(qm);
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if (ret)
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return ret;
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if (qm->vfs_num) {
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ret = qm_set_vf_mse(qm, false);
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if (ret) {
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pci_err(pdev, "Fails to disable vf MSE bit.\n");
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return ret;
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}
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}
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ret = qm_set_msi(qm, false);
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if (ret) {
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pci_err(pdev, "Fails to disable PEH MSI bit.\n");
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return ret;
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}
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qm_dev_ecc_mbit_handle(qm);
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/* OOO register set and check */
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writel(ACC_MASTER_GLOBAL_CTRL_SHUTDOWN,
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qm->io_base + ACC_MASTER_GLOBAL_CTRL);
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/* If bus lock, reset chip */
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ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
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val,
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(val == ACC_MASTER_TRANS_RETURN_RW),
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POLL_PERIOD, POLL_TIMEOUT);
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if (ret) {
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pci_emerg(pdev, "Bus lock! Please reset system.\n");
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return ret;
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}
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ret = qm_set_pf_mse(qm, false);
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if (ret) {
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pci_err(pdev, "Fails to disable pf MSE bit.\n");
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return ret;
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}
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/* The reset related sub-control registers are not in PCI BAR */
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if (ACPI_HANDLE(&pdev->dev)) {
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unsigned long long value = 0;
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acpi_status s;
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s = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
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qm->err_ini->err_info.acpi_rst,
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NULL, &value);
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if (ACPI_FAILURE(s)) {
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pci_err(pdev, "NO controller reset method!\n");
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return -EIO;
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}
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if (value) {
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pci_err(pdev, "Reset step %llu failed!\n", value);
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return -EIO;
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}
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} else {
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pci_err(pdev, "No reset method!\n");
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return -EINVAL;
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}
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return 0;
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}
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static int qm_vf_reset_done(struct hisi_qm *qm)
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{
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struct hisi_qm_list *qm_list = qm->qm_list;
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struct pci_dev *pdev = qm->pdev;
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struct pci_dev *virtfn;
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struct hisi_qm *vf_qm;
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int ret = 0;
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mutex_lock(&qm_list->lock);
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list_for_each_entry(vf_qm, &qm_list->list, list) {
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virtfn = vf_qm->pdev;
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if (virtfn == pdev)
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continue;
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if (pci_physfn(virtfn) == pdev) {
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ret = qm_restart(vf_qm);
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if (ret)
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goto restart_fail;
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}
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}
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restart_fail:
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mutex_unlock(&qm_list->lock);
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return ret;
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}
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|
||||
static int qm_get_dev_err_status(struct hisi_qm *qm)
|
||||
{
|
||||
|
||||
return(qm->err_ini->get_dev_hw_err_status(qm) &
|
||||
qm->err_ini->err_info.ecc_2bits_mask);
|
||||
}
|
||||
|
||||
static int qm_dev_hw_init(struct hisi_qm *qm)
|
||||
{
|
||||
return qm->err_ini->hw_init(qm);
|
||||
}
|
||||
|
||||
static void qm_restart_prepare(struct hisi_qm *qm)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
if (!qm->err_status.is_qm_ecc_mbit &&
|
||||
!qm->err_status.is_dev_ecc_mbit)
|
||||
return;
|
||||
|
||||
/* temporarily close the OOO port used for PEH to write out MSI */
|
||||
value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
|
||||
writel(value & ~qm->err_ini->err_info.msi_wr_port,
|
||||
qm->io_base + ACC_AM_CFG_PORT_WR_EN);
|
||||
|
||||
/* clear dev ecc 2bit error source if having */
|
||||
value = qm_get_dev_err_status(qm);
|
||||
if (value && qm->err_ini->clear_dev_hw_err_status)
|
||||
qm->err_ini->clear_dev_hw_err_status(qm, value);
|
||||
|
||||
/* clear QM ecc mbit error source */
|
||||
writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SOURCE);
|
||||
|
||||
/* clear AM Reorder Buffer ecc mbit source */
|
||||
writel(ACC_ROB_ECC_ERR_MULTPL, qm->io_base + ACC_AM_ROB_ECC_INT_STS);
|
||||
|
||||
if (qm->err_ini->open_axi_master_ooo)
|
||||
qm->err_ini->open_axi_master_ooo(qm);
|
||||
}
|
||||
|
||||
static void qm_restart_done(struct hisi_qm *qm)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
if (!qm->err_status.is_qm_ecc_mbit &&
|
||||
!qm->err_status.is_dev_ecc_mbit)
|
||||
return;
|
||||
|
||||
/* open the OOO port for PEH to write out MSI */
|
||||
value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
|
||||
value |= qm->err_ini->err_info.msi_wr_port;
|
||||
writel(value, qm->io_base + ACC_AM_CFG_PORT_WR_EN);
|
||||
|
||||
qm->err_status.is_qm_ecc_mbit = false;
|
||||
qm->err_status.is_dev_ecc_mbit = false;
|
||||
}
|
||||
|
||||
static int qm_controller_reset_done(struct hisi_qm *qm)
|
||||
{
|
||||
struct pci_dev *pdev = qm->pdev;
|
||||
int ret;
|
||||
|
||||
ret = qm_set_msi(qm, true);
|
||||
if (ret) {
|
||||
pci_err(pdev, "Fails to enable PEH MSI bit!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = qm_set_pf_mse(qm, true);
|
||||
if (ret) {
|
||||
pci_err(pdev, "Fails to enable pf MSE bit!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (qm->vfs_num) {
|
||||
ret = qm_set_vf_mse(qm, true);
|
||||
if (ret) {
|
||||
pci_err(pdev, "Fails to enable vf MSE bit!\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = qm_dev_hw_init(qm);
|
||||
if (ret) {
|
||||
pci_err(pdev, "Failed to init device\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
qm_restart_prepare(qm);
|
||||
|
||||
ret = qm_restart(qm);
|
||||
if (ret) {
|
||||
pci_err(pdev, "Failed to start QM!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (qm->vfs_num) {
|
||||
ret = qm_vf_q_assign(qm, qm->vfs_num);
|
||||
if (ret) {
|
||||
pci_err(pdev, "Failed to assign queue!\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = qm_vf_reset_done(qm);
|
||||
if (ret) {
|
||||
pci_err(pdev, "Failed to start VFs!\n");
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
hisi_qm_dev_err_init(qm);
|
||||
qm_restart_done(qm);
|
||||
|
||||
clear_bit(QM_DEV_RESET_FLAG, &qm->reset_flag);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int qm_controller_reset(struct hisi_qm *qm)
|
||||
{
|
||||
struct pci_dev *pdev = qm->pdev;
|
||||
int ret;
|
||||
|
||||
pci_info(pdev, "Controller resetting...\n");
|
||||
|
||||
ret = qm_controller_reset_prepare(qm);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = qm_soft_reset(qm);
|
||||
if (ret) {
|
||||
pci_err(pdev, "Controller reset failed (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = qm_controller_reset_done(qm);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pci_info(pdev, "Controller reset complete\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* hisi_qm_dev_slot_reset() - slot reset
|
||||
* @pdev: the PCIe device
|
||||
*
|
||||
* This function offers QM relate PCIe device reset interface. Drivers which
|
||||
* use QM can use this function as slot_reset in its struct pci_error_handlers.
|
||||
*/
|
||||
pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev)
|
||||
{
|
||||
struct hisi_qm *qm = pci_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
if (pdev->is_virtfn)
|
||||
return PCI_ERS_RESULT_RECOVERED;
|
||||
|
||||
pci_aer_clear_nonfatal_status(pdev);
|
||||
|
||||
/* reset pcie device controller */
|
||||
ret = qm_controller_reset(qm);
|
||||
if (ret) {
|
||||
pci_err(pdev, "Controller reset failed (%d)\n", ret);
|
||||
return PCI_ERS_RESULT_DISCONNECT;
|
||||
}
|
||||
|
||||
return PCI_ERS_RESULT_RECOVERED;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(hisi_qm_dev_slot_reset);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
|
||||
MODULE_DESCRIPTION("HiSilicon Accelerator queue manager driver");
|
||||
|
|
|
|||
|
|
@ -133,16 +133,28 @@ struct hisi_qm_status {
|
|||
struct hisi_qm;
|
||||
|
||||
struct hisi_qm_err_info {
|
||||
char *acpi_rst;
|
||||
u32 msi_wr_port;
|
||||
u32 ecc_2bits_mask;
|
||||
u32 ce;
|
||||
u32 nfe;
|
||||
u32 fe;
|
||||
u32 msi;
|
||||
};
|
||||
|
||||
struct hisi_qm_err_status {
|
||||
u32 is_qm_ecc_mbit;
|
||||
u32 is_dev_ecc_mbit;
|
||||
};
|
||||
|
||||
struct hisi_qm_err_ini {
|
||||
int (*hw_init)(struct hisi_qm *qm);
|
||||
void (*hw_err_enable)(struct hisi_qm *qm);
|
||||
void (*hw_err_disable)(struct hisi_qm *qm);
|
||||
u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
|
||||
void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
|
||||
void (*open_axi_master_ooo)(struct hisi_qm *qm);
|
||||
void (*close_axi_master_ooo)(struct hisi_qm *qm);
|
||||
void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
|
||||
struct hisi_qm_err_info err_info;
|
||||
};
|
||||
|
|
@ -165,6 +177,7 @@ struct hisi_qm {
|
|||
u32 ctrl_qp_num;
|
||||
u32 vfs_num;
|
||||
struct list_head list;
|
||||
struct hisi_qm_list *qm_list;
|
||||
|
||||
struct qm_dma qdma;
|
||||
struct qm_sqc *sqc;
|
||||
|
|
@ -178,6 +191,8 @@ struct hisi_qm {
|
|||
|
||||
struct hisi_qm_status status;
|
||||
const struct hisi_qm_err_ini *err_ini;
|
||||
struct hisi_qm_err_status err_status;
|
||||
unsigned long reset_flag;
|
||||
|
||||
rwlock_t qps_lock;
|
||||
unsigned long *qp_bitmap;
|
||||
|
|
@ -298,6 +313,7 @@ void hisi_qm_dev_err_init(struct hisi_qm *qm);
|
|||
void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
|
||||
pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
|
||||
pci_channel_state_t state);
|
||||
pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
|
||||
|
||||
struct hisi_acc_sgl_pool;
|
||||
struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
|
||||
|
|
|
|||
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