ARM: 8197/1: vfp: Fix VFPv3 hwcap detection on CPUID based cpus
The subarchitecture field in the fpsid register is 7 bits wide on ARM CPUs using the CPUID identification scheme, spanning bits 22 to 16. The topmost bit is used to designate that the subarchitecture designer is not ARM when it is set to 1. On non-CPUID scheme CPUs the subarchitecture field is only 4 bits wide and the higher bits are used to indicate no double precision support (bit 20) and the FTSMX/FLDMX format (bits 21-22). The VFP support code only looks at bits 19-16 to determine the VFP version. On Qualcomm's processors (Krait and Scorpion) we should see that we have HWCAP_VFPv3 but we don't because bit 22 is set to 1 to indicate that the subarchitecture is not implemented by ARM and the rest of the bits are left as 0 because this is the first subarchitecture that Qualcomm has designed. Unfortunately we can't just widen the FPSID subarchitecture bitmask to consider all the bits on a CPUID scheme because there may be CPUs without the CPUID scheme that have VFP without double precision support and then the version would be a very wrong and large number. Instead, update the version detection logic to consider if the CPU is using the CPUID scheme. If the CPU is using CPUID scheme, use the MVFR registers to determine what version of VFP is supported. We already do this for VFPv4, so do something similar for VFPv3 and look for single or double precision support in MVFR0. Otherwise fall back to using FPSID to detect VFP support on non-CPUID scheme CPUs. We know that VFPv3 is only present in CPUs that have support for the CPUID scheme so this should be equivalent. Tested-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Stephen Boyd
Russell King
Родитель
6f0f2a9f0f
Коммит
6c96a4a6e2
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@ -22,6 +22,7 @@
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#define FPSID_NODOUBLE (1<<20)
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#define FPSID_ARCH_BIT (16)
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#define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
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#define FPSID_CPUID_ARCH_MASK (0x7F << FPSID_ARCH_BIT)
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#define FPSID_PART_BIT (8)
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#define FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
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#define FPSID_VARIANT_BIT (4)
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@ -75,6 +76,10 @@
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/* MVFR0 bits */
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#define MVFR0_A_SIMD_BIT (0)
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#define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT)
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#define MVFR0_SP_BIT (4)
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#define MVFR0_SP_MASK (0xf << MVFR0_SP_BIT)
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#define MVFR0_DP_BIT (8)
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#define MVFR0_DP_MASK (0xf << MVFR0_DP_BIT)
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/* Bit patterns for decoding the packaged operation descriptors */
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#define VFPOPDESC_LENGTH_BIT (9)
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@ -722,6 +722,7 @@ static int __init vfp_init(void)
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{
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unsigned int vfpsid;
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unsigned int cpu_arch = cpu_architecture();
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u32 mvfr0;
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if (cpu_arch >= CPU_ARCH_ARMv6)
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on_each_cpu(vfp_enable, NULL, 1);
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@ -738,63 +739,73 @@ static int __init vfp_init(void)
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vfp_vector = vfp_null_entry;
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pr_info("VFP support v0.3: ");
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if (VFP_arch)
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if (VFP_arch) {
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pr_cont("not present\n");
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else if (vfpsid & FPSID_NODOUBLE) {
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pr_cont("no double precision support\n");
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} else {
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hotcpu_notifier(vfp_hotplug, 0);
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VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; /* Extract the architecture version */
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pr_cont("implementor %02x architecture %d part %02x variant %x rev %x\n",
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(vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT,
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(vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT,
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(vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT,
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(vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT,
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(vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT);
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vfp_vector = vfp_support_entry;
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thread_register_notifier(&vfp_notifier_block);
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vfp_pm_init();
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/*
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* We detected VFP, and the support code is
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* in place; report VFP support to userspace.
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*/
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elf_hwcap |= HWCAP_VFP;
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#ifdef CONFIG_VFPv3
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if (VFP_arch >= 2) {
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elf_hwcap |= HWCAP_VFPv3;
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/*
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* Check for VFPv3 D16 and VFPv4 D16. CPUs in
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* this configuration only have 16 x 64bit
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* registers.
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*/
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if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK)) == 1)
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elf_hwcap |= HWCAP_VFPv3D16; /* also v4-D16 */
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else
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elf_hwcap |= HWCAP_VFPD32;
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}
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#endif
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return 0;
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/* Extract the architecture on CPUID scheme */
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} else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
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VFP_arch = vfpsid & FPSID_CPUID_ARCH_MASK;
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VFP_arch >>= FPSID_ARCH_BIT;
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/*
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* Check for the presence of the Advanced SIMD
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* load/store instructions, integer and single
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* precision floating point operations. Only check
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* for NEON if the hardware has the MVFR registers.
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*/
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if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
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#ifdef CONFIG_NEON
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if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
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elf_hwcap |= HWCAP_NEON;
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if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
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elf_hwcap |= HWCAP_NEON;
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#endif
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#ifdef CONFIG_VFPv3
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if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000)
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elf_hwcap |= HWCAP_VFPv4;
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#endif
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mvfr0 = fmrx(MVFR0);
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if (((mvfr0 & MVFR0_DP_MASK) >> MVFR0_DP_BIT) == 0x2 ||
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((mvfr0 & MVFR0_SP_MASK) >> MVFR0_SP_BIT) == 0x2) {
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elf_hwcap |= HWCAP_VFPv3;
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/*
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* Check for VFPv3 D16 and VFPv4 D16. CPUs in
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* this configuration only have 16 x 64bit
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* registers.
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*/
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if ((mvfr0 & MVFR0_A_SIMD_MASK) == 1)
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/* also v4-D16 */
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elf_hwcap |= HWCAP_VFPv3D16;
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else
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elf_hwcap |= HWCAP_VFPD32;
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}
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if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000)
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elf_hwcap |= HWCAP_VFPv4;
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#endif
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/* Extract the architecture version on pre-cpuid scheme */
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} else {
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if (vfpsid & FPSID_NODOUBLE) {
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pr_cont("no double precision support\n");
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return 0;
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}
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VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT;
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}
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hotcpu_notifier(vfp_hotplug, 0);
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vfp_vector = vfp_support_entry;
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thread_register_notifier(&vfp_notifier_block);
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vfp_pm_init();
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/*
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* We detected VFP, and the support code is
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* in place; report VFP support to userspace.
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*/
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elf_hwcap |= HWCAP_VFP;
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pr_cont("implementor %02x architecture %d part %02x variant %x rev %x\n",
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(vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT,
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VFP_arch,
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(vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT,
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(vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT,
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(vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT);
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return 0;
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}
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