Merge branch 'hns3-tm-fixes'
Yunsheng Lin says: ==================== TM related bugfixes for the HNS3 Ethernet Driver This patch set contains a few bugfixes related to hclge_tm module. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Коммит
6cc40834b4
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@ -49,7 +49,17 @@
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#define HNAE3_CLASS_NAME_SIZE 16
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#define HNAE3_DEV_INITED_B 0x0
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#define HNAE_DEV_SUPPORT_ROCE_B 0x1
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#define HNAE3_DEV_SUPPORT_ROCE_B 0x1
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#define HNAE3_DEV_SUPPORT_DCB_B 0x2
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#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\
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BIT(HNAE3_DEV_SUPPORT_ROCE_B))
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#define hnae3_dev_roce_supported(hdev) \
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hnae_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
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#define hnae3_dev_dcb_supported(hdev) \
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hnae_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
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#define ring_ptr_move_fw(ring, p) \
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((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
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@ -366,12 +376,12 @@ struct hnae3_ae_algo {
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struct hnae3_tc_info {
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u16 tqp_offset; /* TQP offset from base TQP */
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u16 tqp_count; /* Total TQPs */
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u8 up; /* user priority */
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u8 tc; /* TC index */
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bool enable; /* If this TC is enable or not */
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};
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#define HNAE3_MAX_TC 8
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#define HNAE3_MAX_USER_PRIO 8
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struct hnae3_knic_private_info {
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struct net_device *netdev; /* Set by KNIC client when init instance */
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u16 rss_size; /* Allocated RSS queues */
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@ -379,6 +389,7 @@ struct hnae3_knic_private_info {
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u16 num_desc;
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u8 num_tc; /* Total number of enabled TCs */
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u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */
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struct hnae3_tc_info tc_info[HNAE3_MAX_TC]; /* Idx of array is HW TC */
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u16 num_tqps; /* total number of TQPs in this handle */
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@ -270,7 +270,8 @@ struct hclge_tx_buff_alloc {
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struct hclge_rx_priv_buff {
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__le16 buf_num[HCLGE_TC_NUM];
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u8 rsv[8];
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__le16 shared_buf;
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u8 rsv[6];
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};
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struct hclge_query_version {
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@ -688,6 +689,7 @@ struct hclge_reset_tqp_queue {
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#define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
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#define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
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#define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
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#define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
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#define HCLGE_TYPE_CRQ 0
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#define HCLGE_TYPE_CSQ 1
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@ -46,17 +46,7 @@ static const struct pci_device_id ae_algo_pci_tbl[] = {
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{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
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{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
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{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
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/* Required last entry */
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{0, }
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};
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static const struct pci_device_id roce_pci_tbl[] = {
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{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
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{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
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{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
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{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
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{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
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/* Required last entry */
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/* required last entry */
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{0, }
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};
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@ -894,7 +884,7 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
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hdev->num_tqps = __le16_to_cpu(req->tqp_num);
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hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
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if (hnae_get_bit(hdev->ae_dev->flag, HNAE_DEV_SUPPORT_ROCE_B)) {
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if (hnae3_dev_roce_supported(hdev)) {
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hdev->num_roce_msix =
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hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
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HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
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@ -1454,7 +1444,11 @@ static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, u32 rx_all)
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tc_num = hclge_get_tc_num(hdev);
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pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
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shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
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if (hnae3_dev_dcb_supported(hdev))
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shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
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else
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shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
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shared_buf_tc = pfc_enable_num * hdev->mps +
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(tc_num - pfc_enable_num) * hdev->mps / 2 +
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hdev->mps;
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@ -1495,6 +1489,16 @@ int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size)
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struct hclge_priv_buf *priv;
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int i;
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/* When DCB is not supported, rx private
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* buffer is not allocated.
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*/
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if (!hnae3_dev_dcb_supported(hdev)) {
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if (!hclge_is_rx_buf_ok(hdev, rx_all))
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return -ENOMEM;
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return 0;
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}
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/* step 1, try to alloc private buffer for all enabled tc */
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for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
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priv = &hdev->priv_buf[i];
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@ -1510,6 +1514,11 @@ int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size)
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priv->wl.high = 2 * hdev->mps;
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priv->buf_size = priv->wl.high;
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}
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} else {
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priv->enable = 0;
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priv->wl.low = 0;
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priv->wl.high = 0;
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priv->buf_size = 0;
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}
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}
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@ -1522,8 +1531,15 @@ int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size)
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for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
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priv = &hdev->priv_buf[i];
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if (hdev->hw_tc_map & BIT(i))
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priv->enable = 1;
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priv->enable = 0;
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priv->wl.low = 0;
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priv->wl.high = 0;
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priv->buf_size = 0;
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if (!(hdev->hw_tc_map & BIT(i)))
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continue;
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priv->enable = 1;
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if (hdev->tm_info.hw_pfc_map & BIT(i)) {
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priv->wl.low = 128;
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@ -1616,6 +1632,10 @@ static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev)
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cpu_to_le16(true << HCLGE_TC0_PRI_BUF_EN_B);
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}
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req->shared_buf =
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cpu_to_le16((hdev->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
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(1 << HCLGE_TC0_PRI_BUF_EN_B));
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ret = hclge_cmd_send(&hdev->hw, &desc, 1);
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if (ret) {
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dev_err(&hdev->pdev->dev,
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@ -1782,18 +1802,22 @@ int hclge_buffer_alloc(struct hclge_dev *hdev)
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return ret;
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}
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ret = hclge_rx_priv_wl_config(hdev);
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if (ret) {
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dev_err(&hdev->pdev->dev,
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"could not configure rx private waterline %d\n", ret);
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return ret;
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}
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if (hnae3_dev_dcb_supported(hdev)) {
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ret = hclge_rx_priv_wl_config(hdev);
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if (ret) {
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dev_err(&hdev->pdev->dev,
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"could not configure rx private waterline %d\n",
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ret);
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return ret;
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}
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ret = hclge_common_thrd_config(hdev);
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if (ret) {
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dev_err(&hdev->pdev->dev,
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"could not configure common threshold %d\n", ret);
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return ret;
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ret = hclge_common_thrd_config(hdev);
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if (ret) {
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dev_err(&hdev->pdev->dev,
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"could not configure common threshold %d\n",
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ret);
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return ret;
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}
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}
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ret = hclge_common_wl_config(hdev);
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@ -2582,6 +2606,7 @@ static int hclge_rss_init_hw(struct hclge_dev *hdev)
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u16 tc_valid[HCLGE_MAX_TC_NUM];
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u16 tc_size[HCLGE_MAX_TC_NUM];
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u32 *rss_indir = NULL;
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u16 rss_size = 0, roundup_size;
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const u8 *key;
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int i, ret, j;
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@ -2596,7 +2621,13 @@ static int hclge_rss_init_hw(struct hclge_dev *hdev)
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for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
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for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
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vport[j].rss_indirection_tbl[i] =
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i % hdev->rss_size_max;
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i % vport[j].alloc_rss_size;
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/* vport 0 is for PF */
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if (j != 0)
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continue;
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rss_size = vport[j].alloc_rss_size;
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rss_indir[i] = vport[j].rss_indirection_tbl[i];
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}
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}
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@ -2613,42 +2644,31 @@ static int hclge_rss_init_hw(struct hclge_dev *hdev)
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if (ret)
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goto err;
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for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
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if (hdev->hw_tc_map & BIT(i))
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tc_valid[i] = 1;
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else
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tc_valid[i] = 0;
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switch (hdev->rss_size_max) {
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case HCLGE_RSS_TC_SIZE_0:
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tc_size[i] = 0;
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break;
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case HCLGE_RSS_TC_SIZE_1:
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tc_size[i] = 1;
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break;
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case HCLGE_RSS_TC_SIZE_2:
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tc_size[i] = 2;
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break;
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case HCLGE_RSS_TC_SIZE_3:
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tc_size[i] = 3;
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break;
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case HCLGE_RSS_TC_SIZE_4:
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tc_size[i] = 4;
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break;
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case HCLGE_RSS_TC_SIZE_5:
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tc_size[i] = 5;
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break;
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case HCLGE_RSS_TC_SIZE_6:
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tc_size[i] = 6;
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break;
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case HCLGE_RSS_TC_SIZE_7:
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tc_size[i] = 7;
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break;
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default:
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break;
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}
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tc_offset[i] = hdev->rss_size_max * i;
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/* Each TC have the same queue size, and tc_size set to hardware is
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* the log2 of roundup power of two of rss_size, the acutal queue
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* size is limited by indirection table.
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*/
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if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
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dev_err(&hdev->pdev->dev,
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"Configure rss tc size failed, invalid TC_SIZE = %d\n",
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rss_size);
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return -EINVAL;
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}
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roundup_size = roundup_pow_of_two(rss_size);
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roundup_size = ilog2(roundup_size);
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for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
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tc_valid[i] = 0;
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if (!(hdev->hw_tc_map & BIT(i)))
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continue;
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tc_valid[i] = 1;
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tc_size[i] = roundup_size;
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tc_offset[i] = rss_size * i;
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}
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ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
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err:
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@ -3932,8 +3952,7 @@ static int hclge_init_client_instance(struct hnae3_client *client,
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goto err;
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if (hdev->roce_client &&
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hnae_get_bit(hdev->ae_dev->flag,
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HNAE_DEV_SUPPORT_ROCE_B)) {
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hnae3_dev_roce_supported(hdev)) {
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struct hnae3_client *rc = hdev->roce_client;
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ret = hclge_init_roce_base_info(vport);
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@ -3956,8 +3975,7 @@ static int hclge_init_client_instance(struct hnae3_client *client,
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break;
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case HNAE3_CLIENT_ROCE:
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if (hnae_get_bit(hdev->ae_dev->flag,
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HNAE_DEV_SUPPORT_ROCE_B)) {
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if (hnae3_dev_roce_supported(hdev)) {
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hdev->roce_client = client;
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vport->roce.client = client;
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}
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@ -4069,7 +4087,6 @@ static void hclge_pci_uninit(struct hclge_dev *hdev)
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static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
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{
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struct pci_dev *pdev = ae_dev->pdev;
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const struct pci_device_id *id;
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struct hclge_dev *hdev;
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int ret;
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@ -4084,10 +4101,6 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
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hdev->ae_dev = ae_dev;
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ae_dev->priv = hdev;
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id = pci_match_id(roce_pci_tbl, ae_dev->pdev);
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if (id)
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hnae_set_bit(ae_dev->flag, HNAE_DEV_SUPPORT_ROCE_B, 1);
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ret = hclge_pci_init(hdev);
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if (ret) {
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dev_err(&pdev->dev, "PCI init failed\n");
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@ -4150,12 +4163,6 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
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return ret;
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}
|
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ret = hclge_rss_init_hw(hdev);
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if (ret) {
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dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
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return ret;
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}
|
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|
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ret = hclge_init_vlan_config(hdev);
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if (ret) {
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dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
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|
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@ -4168,6 +4175,12 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
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return ret;
|
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}
|
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|
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ret = hclge_rss_init_hw(hdev);
|
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if (ret) {
|
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dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
|
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return ret;
|
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}
|
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|
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setup_timer(&hdev->service_timer, hclge_service_timer,
|
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(unsigned long)hdev);
|
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INIT_WORK(&hdev->service_task, hclge_service_task);
|
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|
|
|
|||
|
|
@ -176,7 +176,6 @@ struct hclge_pg_info {
|
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struct hclge_tc_info {
|
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u8 tc_id;
|
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u8 tc_sch_mode; /* 0: sp; 1: dwrr */
|
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u8 up;
|
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u8 pgid;
|
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u32 bw_limit;
|
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};
|
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|
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@ -197,6 +196,7 @@ struct hclge_tm_info {
|
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u8 num_tc;
|
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u8 num_pg; /* It must be 1 if vNET-Base schd */
|
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u8 pg_dwrr[HCLGE_PG_NUM];
|
||||
u8 prio_tc[HNAE3_MAX_USER_PRIO];
|
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struct hclge_pg_info pg_info[HCLGE_PG_NUM];
|
||||
struct hclge_tc_info tc_info[HNAE3_MAX_TC];
|
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enum hclge_fc_mode fc_mode;
|
||||
|
|
@ -477,6 +477,7 @@ struct hclge_vport {
|
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u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
|
||||
/* User configured lookup table entries */
|
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u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
|
||||
u16 alloc_rss_size;
|
||||
|
||||
u16 qs_offset;
|
||||
u16 bw_limit; /* VSI BW Limit (0 = disabled) */
|
||||
|
|
|
|||
|
|
@ -128,9 +128,7 @@ static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id)
|
|||
{
|
||||
u8 tc;
|
||||
|
||||
for (tc = 0; tc < hdev->tm_info.num_tc; tc++)
|
||||
if (hdev->tm_info.tc_info[tc].up == pri_id)
|
||||
break;
|
||||
tc = hdev->tm_info.prio_tc[pri_id];
|
||||
|
||||
if (tc >= hdev->tm_info.num_tc)
|
||||
return -EINVAL;
|
||||
|
|
@ -158,7 +156,7 @@ static int hclge_up_to_tc_map(struct hclge_dev *hdev)
|
|||
|
||||
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false);
|
||||
|
||||
for (pri_id = 0; pri_id < hdev->tm_info.num_tc; pri_id++) {
|
||||
for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) {
|
||||
ret = hclge_fill_pri_array(hdev, pri, pri_id);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -280,11 +278,11 @@ static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev,
|
|||
|
||||
shap_cfg_cmd->pg_id = pg_id;
|
||||
|
||||
hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, IR_B, ir_b);
|
||||
hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, IR_U, ir_u);
|
||||
hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, IR_S, ir_s);
|
||||
hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, BS_B, bs_b);
|
||||
hclge_tm_set_feild(shap_cfg_cmd->pg_shapping_para, BS_S, bs_s);
|
||||
hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_B, ir_b);
|
||||
hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_U, ir_u);
|
||||
hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, IR_S, ir_s);
|
||||
hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, BS_B, bs_b);
|
||||
hclge_tm_set_field(shap_cfg_cmd->pg_shapping_para, BS_S, bs_s);
|
||||
|
||||
return hclge_cmd_send(&hdev->hw, &desc, 1);
|
||||
}
|
||||
|
|
@ -307,11 +305,11 @@ static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev,
|
|||
|
||||
shap_cfg_cmd->pri_id = pri_id;
|
||||
|
||||
hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, IR_B, ir_b);
|
||||
hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, IR_U, ir_u);
|
||||
hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, IR_S, ir_s);
|
||||
hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, BS_B, bs_b);
|
||||
hclge_tm_set_feild(shap_cfg_cmd->pri_shapping_para, BS_S, bs_s);
|
||||
hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_B, ir_b);
|
||||
hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_U, ir_u);
|
||||
hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, IR_S, ir_s);
|
||||
hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, BS_B, bs_b);
|
||||
hclge_tm_set_field(shap_cfg_cmd->pri_shapping_para, BS_S, bs_s);
|
||||
|
||||
return hclge_cmd_send(&hdev->hw, &desc, 1);
|
||||
}
|
||||
|
|
@ -397,6 +395,7 @@ static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
|
|||
kinfo->num_tqps / kinfo->num_tc);
|
||||
vport->qs_offset = hdev->tm_info.num_tc * vport->vport_id;
|
||||
vport->dwrr = 100; /* 100 percent as init */
|
||||
vport->alloc_rss_size = kinfo->rss_size;
|
||||
|
||||
for (i = 0; i < kinfo->num_tc; i++) {
|
||||
if (hdev->hw_tc_map & BIT(i)) {
|
||||
|
|
@ -404,16 +403,17 @@ static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
|
|||
kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
|
||||
kinfo->tc_info[i].tqp_count = kinfo->rss_size;
|
||||
kinfo->tc_info[i].tc = i;
|
||||
kinfo->tc_info[i].up = hdev->tm_info.tc_info[i].up;
|
||||
} else {
|
||||
/* Set to default queue if TC is disable */
|
||||
kinfo->tc_info[i].enable = false;
|
||||
kinfo->tc_info[i].tqp_offset = 0;
|
||||
kinfo->tc_info[i].tqp_count = 1;
|
||||
kinfo->tc_info[i].tc = 0;
|
||||
kinfo->tc_info[i].up = 0;
|
||||
}
|
||||
}
|
||||
|
||||
memcpy(kinfo->prio_tc, hdev->tm_info.prio_tc,
|
||||
FIELD_SIZEOF(struct hnae3_knic_private_info, prio_tc));
|
||||
}
|
||||
|
||||
static void hclge_tm_vport_info_update(struct hclge_dev *hdev)
|
||||
|
|
@ -435,12 +435,15 @@ static void hclge_tm_tc_info_init(struct hclge_dev *hdev)
|
|||
for (i = 0; i < hdev->tm_info.num_tc; i++) {
|
||||
hdev->tm_info.tc_info[i].tc_id = i;
|
||||
hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR;
|
||||
hdev->tm_info.tc_info[i].up = i;
|
||||
hdev->tm_info.tc_info[i].pgid = 0;
|
||||
hdev->tm_info.tc_info[i].bw_limit =
|
||||
hdev->tm_info.pg_info[0].bw_limit;
|
||||
}
|
||||
|
||||
for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
|
||||
hdev->tm_info.prio_tc[i] =
|
||||
(i >= hdev->tm_info.num_tc) ? 0 : i;
|
||||
|
||||
hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
|
||||
}
|
||||
|
||||
|
|
@ -976,6 +979,10 @@ int hclge_pause_setup_hw(struct hclge_dev *hdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Only DCB-supported dev supports qset back pressure setting */
|
||||
if (!hnae3_dev_dcb_supported(hdev))
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < hdev->tm_info.num_tc; i++) {
|
||||
ret = hclge_tm_qs_bp_cfg(hdev, i);
|
||||
if (ret)
|
||||
|
|
|
|||
|
|
@ -94,10 +94,10 @@ struct hclge_bp_to_qs_map_cmd {
|
|||
u32 rsvd1;
|
||||
};
|
||||
|
||||
#define hclge_tm_set_feild(dest, string, val) \
|
||||
#define hclge_tm_set_field(dest, string, val) \
|
||||
hnae_set_field((dest), (HCLGE_TM_SHAP_##string##_MSK), \
|
||||
(HCLGE_TM_SHAP_##string##_LSH), val)
|
||||
#define hclge_tm_get_feild(src, string) \
|
||||
#define hclge_tm_get_field(src, string) \
|
||||
hnae_get_field((src), (HCLGE_TM_SHAP_##string##_MSK), \
|
||||
(HCLGE_TM_SHAP_##string##_LSH))
|
||||
|
||||
|
|
|
|||
|
|
@ -41,11 +41,16 @@ static struct hnae3_client client;
|
|||
static const struct pci_device_id hns3_pci_tbl[] = {
|
||||
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
|
||||
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
|
||||
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
|
||||
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
|
||||
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
|
||||
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
|
||||
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
|
||||
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
|
||||
HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
|
||||
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
|
||||
HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
|
||||
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
|
||||
HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
|
||||
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
|
||||
HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
|
||||
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
|
||||
HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
|
||||
/* required last entry */
|
||||
{0, }
|
||||
};
|
||||
|
|
@ -1348,6 +1353,7 @@ static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
}
|
||||
|
||||
ae_dev->pdev = pdev;
|
||||
ae_dev->flag = ent->driver_data;
|
||||
ae_dev->dev_type = HNAE3_DEV_KNIC;
|
||||
pci_set_drvdata(pdev, ae_dev);
|
||||
|
||||
|
|
|
|||
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