drm/i915: add pipe_config->pixel_multiplier
Used by SDVO (and hopefully, eventually HDMI, if we ever get around to fixing up the low dotclock CEA modes ...). This required adding a new encoder->mode_set callback to be able to pass around the intel_crtc_config. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
Родитель
7ae892337e
Коммит
6cc5f341b5
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@ -4337,14 +4337,15 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
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}
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static void vlv_update_pll(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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intel_clock_t *clock, intel_clock_t *reduced_clock,
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int num_connectors)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct drm_display_mode *adjusted_mode =
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&intel_crtc->config.adjusted_mode;
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struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
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int pipe = intel_crtc->pipe;
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u32 dpll, mdiv, pdiv;
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u32 bestn, bestm1, bestm2, bestp1, bestp2;
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@ -4411,11 +4412,11 @@ static void vlv_update_pll(struct drm_crtc *crtc,
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temp = 0;
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if (is_sdvo) {
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temp = intel_mode_get_pixel_multiplier(adjusted_mode);
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if (temp > 1)
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temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
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else
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temp = 0;
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temp = 0;
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if (intel_crtc->config.pixel_multiplier > 1) {
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temp = (intel_crtc->config.pixel_multiplier - 1)
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<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
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}
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}
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I915_WRITE(DPLL_MD(pipe), temp);
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POSTING_READ(DPLL_MD(pipe));
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@ -4441,14 +4442,15 @@ static void vlv_update_pll(struct drm_crtc *crtc,
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}
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static void i9xx_update_pll(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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intel_clock_t *clock, intel_clock_t *reduced_clock,
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int num_connectors)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct drm_display_mode *adjusted_mode =
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&intel_crtc->config.adjusted_mode;
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struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
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struct intel_encoder *encoder;
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int pipe = intel_crtc->pipe;
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u32 dpll;
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@ -4465,11 +4467,12 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
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dpll |= DPLLB_MODE_LVDS;
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else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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if (is_sdvo) {
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int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
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if (pixel_multiplier > 1) {
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if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
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dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
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if ((intel_crtc->config.pixel_multiplier > 1) &&
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(IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
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dpll |= (intel_crtc->config.pixel_multiplier - 1)
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<< SDVO_MULTIPLIER_SHIFT_HIRES;
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}
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dpll |= DPLL_DVO_HIGH_SPEED;
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}
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@ -4534,11 +4537,11 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
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if (INTEL_INFO(dev)->gen >= 4) {
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u32 temp = 0;
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if (is_sdvo) {
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temp = intel_mode_get_pixel_multiplier(adjusted_mode);
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if (temp > 1)
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temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
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else
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temp = 0;
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temp = 0;
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if (intel_crtc->config.pixel_multiplier > 1) {
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temp = (intel_crtc->config.pixel_multiplier - 1)
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<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
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}
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}
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I915_WRITE(DPLL_MD(pipe), temp);
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} else {
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@ -4748,11 +4751,11 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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has_reduced_clock ? &reduced_clock : NULL,
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num_connectors);
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else if (IS_VALLEYVIEW(dev))
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vlv_update_pll(crtc, mode, adjusted_mode, &clock,
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vlv_update_pll(crtc, &clock,
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has_reduced_clock ? &reduced_clock : NULL,
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num_connectors);
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else
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i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
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i9xx_update_pll(crtc, &clock,
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has_reduced_clock ? &reduced_clock : NULL,
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num_connectors);
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@ -5466,17 +5469,18 @@ int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
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return bps / (link_bw * 8) + 1;
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}
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static void ironlake_set_m_n(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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static void ironlake_set_m_n(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct drm_display_mode *adjusted_mode =
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&intel_crtc->config.adjusted_mode;
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struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
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enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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struct intel_encoder *intel_encoder, *edp_encoder = NULL;
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struct intel_link_m_n m_n = {0};
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int target_clock, pixel_multiplier, lane, link_bw;
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int target_clock, lane, link_bw;
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bool is_dp = false, is_cpu_edp = false;
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for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
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@ -5494,7 +5498,6 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
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}
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/* FDI link */
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pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
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lane = 0;
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/* CPU eDP doesn't require FDI link, so just set DP M/N
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according to current link config */
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@ -5525,8 +5528,8 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
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intel_crtc->fdi_lanes = lane;
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if (pixel_multiplier > 1)
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link_bw *= pixel_multiplier;
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if (intel_crtc->config.pixel_multiplier > 1)
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link_bw *= intel_crtc->config.pixel_multiplier;
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intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
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I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
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@ -5536,7 +5539,6 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
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}
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static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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struct drm_display_mode *adjusted_mode,
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intel_clock_t *clock, u32 fp)
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{
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struct drm_crtc *crtc = &intel_crtc->base;
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@ -5544,7 +5546,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_encoder *intel_encoder;
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uint32_t dpll;
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int factor, pixel_multiplier, num_connectors = 0;
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int factor, num_connectors = 0;
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bool is_lvds = false, is_sdvo = false, is_tv = false;
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bool is_dp = false, is_cpu_edp = false;
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@ -5595,9 +5597,9 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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if (is_sdvo) {
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pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
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if (pixel_multiplier > 1) {
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dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
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if (intel_crtc->config.pixel_multiplier > 1) {
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dpll |= (intel_crtc->config.pixel_multiplier - 1)
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<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
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}
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dpll |= DPLL_DVO_HIGH_SPEED;
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}
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@ -5701,7 +5703,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
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reduced_clock.m2;
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dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
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dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
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DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
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drm_mode_debug_printmodeline(mode);
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@ -5755,7 +5757,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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/* Note, this also computes intel_crtc->fdi_lanes which is used below in
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* ironlake_check_fdi_lanes. */
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ironlake_set_m_n(crtc, mode, adjusted_mode);
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ironlake_set_m_n(crtc);
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fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
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@ -5871,7 +5873,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
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intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
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if (!is_dp || is_cpu_edp)
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ironlake_set_m_n(crtc, mode, adjusted_mode);
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ironlake_set_m_n(crtc);
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haswell_set_pipeconf(crtc, adjusted_mode, dither);
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@ -5924,8 +5926,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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encoder->base.base.id,
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drm_get_encoder_name(&encoder->base),
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mode->base.id, mode->name);
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encoder_funcs = encoder->base.helper_private;
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encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
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if (encoder->mode_set) {
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encoder->mode_set(encoder);
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} else {
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encoder_funcs = encoder->base.helper_private;
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encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
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}
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}
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return 0;
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@ -102,8 +102,6 @@
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#define INTEL_DVO_CHIP_TVOUT 4
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/* drm_display_mode->private_flags */
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#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
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#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
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#define INTEL_MODE_DP_FORCE_6BPC (0x10)
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/*
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* Set when limited 16-235 (as opposed to full 0-255) RGB color range is
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@ -111,20 +109,6 @@
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*/
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#define INTEL_MODE_LIMITED_COLOR_RANGE (0x40)
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static inline void
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intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
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int multiplier)
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{
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mode->clock *= multiplier;
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mode->private_flags |= multiplier;
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}
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static inline int
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intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
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{
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return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
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}
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struct intel_framebuffer {
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struct drm_framebuffer base;
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struct drm_i915_gem_object *obj;
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@ -159,6 +143,7 @@ struct intel_encoder {
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void (*pre_pll_enable)(struct intel_encoder *);
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void (*pre_enable)(struct intel_encoder *);
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void (*enable)(struct intel_encoder *);
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void (*mode_set)(struct intel_encoder *intel_encoder);
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void (*disable)(struct intel_encoder *);
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void (*post_disable)(struct intel_encoder *);
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/* Read out the current hw state of this connector, returning true if
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@ -205,6 +190,8 @@ struct intel_crtc_config {
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* changes the crtc timings in the mode to prevent the crtc fixup from
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* overwriting them. Currently only lvds needs that. */
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bool timings_set;
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/* Used by SDVO (and if we ever fix it, HDMI). */
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unsigned pixel_multiplier;
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};
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struct intel_crtc {
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@ -788,7 +788,6 @@ static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
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v_sync_offset = mode->vsync_start - mode->vdisplay;
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mode_clock = mode->clock;
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mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
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mode_clock /= 10;
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dtd->part1.clock = mode_clock;
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@ -1041,12 +1040,12 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
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return true;
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}
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static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_config *pipe_config)
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{
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struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
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int multiplier;
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struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
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struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
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struct drm_display_mode *mode = &pipe_config->requested_mode;
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/* We need to construct preferred input timings based on our
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* output timings. To do that, we have to set the output
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@ -1073,8 +1072,9 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
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/* Make the CRTC code factor in the SDVO pixel multiplier. The
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* SDVO device will factor out the multiplier during mode_set.
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*/
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multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
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intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
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pipe_config->pixel_multiplier =
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intel_sdvo_get_pixel_multiplier(adjusted_mode);
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adjusted_mode->clock *= pipe_config->pixel_multiplier;
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if (intel_sdvo->color_range_auto) {
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/* See CEA-861-E - 5.1 Default Encoding Parameters */
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@ -1093,19 +1093,19 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
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return true;
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}
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static void intel_sdvo_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_device *dev = intel_encoder->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = encoder->crtc;
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struct drm_crtc *crtc = intel_encoder->base.crtc;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
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struct drm_display_mode *adjusted_mode =
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&intel_crtc->config.adjusted_mode;
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struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
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struct intel_sdvo *intel_sdvo = to_intel_sdvo(&intel_encoder->base);
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u32 sdvox;
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struct intel_sdvo_in_out_map in_out;
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struct intel_sdvo_dtd input_dtd, output_dtd;
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int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
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int rate;
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if (!mode)
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@ -1165,7 +1165,7 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
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DRM_INFO("Setting input timings on %s failed\n",
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SDVO_NAME(intel_sdvo));
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switch (pixel_multiplier) {
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switch (intel_crtc->config.pixel_multiplier) {
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default:
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case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
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case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
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@ -1209,7 +1209,8 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
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} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
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/* done in crtc_mode_set as it lives inside the dpll register */
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} else {
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sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
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sdvox |= (intel_crtc->config.pixel_multiplier - 1)
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<< SDVO_PORT_MULTIPLY_SHIFT;
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}
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if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
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@ -2041,8 +2042,6 @@ done:
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}
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static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
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.mode_fixup = intel_sdvo_mode_fixup,
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.mode_set = intel_sdvo_mode_set,
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};
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static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
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@ -2787,7 +2786,9 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
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drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
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intel_encoder->compute_config = intel_sdvo_compute_config;
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intel_encoder->disable = intel_disable_sdvo;
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intel_encoder->mode_set = intel_sdvo_mode_set;
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intel_encoder->enable = intel_enable_sdvo;
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intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
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Загрузка…
Ссылка в новой задаче