powerpc: rework FSL Book-E PTE access and TLB miss
This converts the FSL Book-E PTE access and TLB miss handling to match with the recent changes to 44x that introduce support for non-atomic PTE operations in pgtable-ppc32.h and removes write back to the PTE from the TLB miss handlers. In addition, the DSI interrupt code no longer tries to fixup write permission, this is left to generic code, and _PAGE_HWWRITE is gone. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
Родитель
2d07db33d1
Коммит
6cfd8990e2
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@ -483,90 +483,16 @@ interrupt_base:
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/* Data Storage Interrupt */
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START_EXCEPTION(DataStorage)
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mtspr SPRN_SPRG0, r10 /* Save some working registers */
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mtspr SPRN_SPRG1, r11
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mtspr SPRN_SPRG4W, r12
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mtspr SPRN_SPRG5W, r13
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mfcr r11
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mtspr SPRN_SPRG7W, r11
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/*
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* Check if it was a store fault, if not then bail
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* because a user tried to access a kernel or
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* read-protected page. Otherwise, get the
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* offending address and handle it.
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*/
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mfspr r10, SPRN_ESR
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andis. r10, r10, ESR_ST@h
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beq 2f
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mfspr r10, SPRN_DEAR /* Get faulting address */
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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lis r11, PAGE_OFFSET@h
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cmplw 0, r10, r11
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bge 2f
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/* Get the PGD for the current thread */
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3:
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mfspr r11,SPRN_SPRG3
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lwz r11,PGDIR(r11)
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4:
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FIND_PTE
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/* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
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andi. r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
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cmpwi 0, r13, _PAGE_RW|_PAGE_USER
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bne 2f /* Bail if not */
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/* Update 'changed'. */
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ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
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stw r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */
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/* MAS2 not updated as the entry does exist in the tlb, this
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fault taken to detect state transition (eg: COW -> DIRTY)
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*/
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andi. r11, r11, _PAGE_HWEXEC
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rlwimi r11, r11, 31, 27, 27 /* SX <- _PAGE_HWEXEC */
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ori r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
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/* update search PID in MAS6, AS = 0 */
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mfspr r12, SPRN_PID0
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slwi r12, r12, 16
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mtspr SPRN_MAS6, r12
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/* find the TLB index that caused the fault. It has to be here. */
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tlbsx 0, r10
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/* only update the perm bits, assume the RPN is fine */
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mfspr r12, SPRN_MAS3
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rlwimi r12, r11, 0, 20, 31
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mtspr SPRN_MAS3,r12
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tlbwe
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/* Done...restore registers and get out of here. */
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mfspr r11, SPRN_SPRG7R
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mtcr r11
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mfspr r13, SPRN_SPRG5R
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mfspr r12, SPRN_SPRG4R
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mfspr r11, SPRN_SPRG1
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mfspr r10, SPRN_SPRG0
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rfi /* Force context change */
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2:
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/*
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* The bailout. Restore registers to pre-exception conditions
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* and call the heavyweights to help us out.
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*/
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mfspr r11, SPRN_SPRG7R
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mtcr r11
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mfspr r13, SPRN_SPRG5R
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mfspr r12, SPRN_SPRG4R
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mfspr r11, SPRN_SPRG1
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mfspr r10, SPRN_SPRG0
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b data_access
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NORMAL_EXCEPTION_PROLOG
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mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
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stw r5,_ESR(r11)
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mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
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andis. r10,r5,(ESR_ILK|ESR_DLK)@h
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bne 1f
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EXC_XFER_EE_LITE(0x0300, handle_page_fault)
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1:
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addi r3,r1,STACK_FRAME_OVERHEAD
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EXC_XFER_EE_LITE(0x0300, CacheLockingException)
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/* Instruction Storage Interrupt */
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INSTRUCTION_STORAGE_EXCEPTION
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@ -645,15 +571,30 @@ interrupt_base:
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lwz r11,PGDIR(r11)
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4:
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/* Mask of required permission bits. Note that while we
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* do copy ESR:ST to _PAGE_RW position as trying to write
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* to an RO page is pretty common, we don't do it with
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* _PAGE_DIRTY. We could do it, but it's a fairly rare
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* event so I'd rather take the overhead when it happens
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* rather than adding an instruction here. We should measure
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* whether the whole thing is worth it in the first place
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* as we could avoid loading SPRN_ESR completely in the first
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* place...
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*
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* TODO: Is it worth doing that mfspr & rlwimi in the first
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* place or can we save a couple of instructions here ?
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*/
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mfspr r12,SPRN_ESR
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li r13,_PAGE_PRESENT|_PAGE_ACCESSED
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rlwimi r13,r12,11,29,29
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FIND_PTE
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andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
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beq 2f /* Bail if not present */
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andc. r13,r13,r11 /* Check permission */
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bne 2f /* Bail if permission mismach */
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#ifdef CONFIG_PTE_64BIT
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lwz r13, 0(r12)
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#endif
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ori r11, r11, _PAGE_ACCESSED
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stw r11, PTE_FLAGS_OFFSET(r12)
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/* Jump to common tlb load */
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b finish_tlb_load
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@ -667,7 +608,7 @@ interrupt_base:
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mfspr r12, SPRN_SPRG4R
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mfspr r11, SPRN_SPRG1
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mfspr r10, SPRN_SPRG0
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b data_access
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b DataStorage
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/* Instruction TLB Error Interrupt */
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/*
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@ -705,15 +646,16 @@ interrupt_base:
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lwz r11,PGDIR(r11)
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4:
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/* Make up the required permissions */
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li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
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FIND_PTE
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andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
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beq 2f /* Bail if not present */
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andc. r13,r13,r11 /* Check permission */
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bne 2f /* Bail if permission mismach */
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#ifdef CONFIG_PTE_64BIT
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lwz r13, 0(r12)
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#endif
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ori r11, r11, _PAGE_ACCESSED
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stw r11, PTE_FLAGS_OFFSET(r12)
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/* Jump to common TLB load point */
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b finish_tlb_load
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@ -769,28 +711,12 @@ interrupt_base:
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*/
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/*
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* Data TLB exceptions will bail out to this point
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* if they can't resolve the lightweight TLB fault.
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*/
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data_access:
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NORMAL_EXCEPTION_PROLOG
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mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
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stw r5,_ESR(r11)
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mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
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andis. r10,r5,(ESR_ILK|ESR_DLK)@h
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bne 1f
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EXC_XFER_EE_LITE(0x0300, handle_page_fault)
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1:
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addi r3,r1,STACK_FRAME_OVERHEAD
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EXC_XFER_EE_LITE(0x0300, CacheLockingException)
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/*
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* Both the instruction and data TLB miss get to this
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* point to load the TLB.
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* r10 - EA of fault
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* r11 - TLB (info from Linux PTE)
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* r12, r13 - available to use
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* r12 - available to use
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* r13 - upper bits of PTE (if PTE_64BIT) or available to use
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* CR5 - results of addr >= PAGE_OFFSET
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* MAS0, MAS1 - loaded with proper value when we get here
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* MAS2, MAS3 - will need additional info from Linux PTE
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@ -812,19 +738,13 @@ finish_tlb_load:
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#endif
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mtspr SPRN_MAS2, r12
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bge 5, 1f
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/* is user addr */
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andi. r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
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li r10, (_PAGE_HWEXEC | _PAGE_PRESENT)
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rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
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and r12, r11, r10
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andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
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srwi r10, r12, 1
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or r12, r12, r10 /* Copy user perms into supervisor */
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iseleq r12, 0, r12
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b 2f
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/* is kernel addr */
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1: rlwinm r12, r11, 31, 29, 29 /* Extract _PAGE_HWWRITE into SW */
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ori r12, r12, (MAS3_SX | MAS3_SR)
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slwi r10, r12, 1
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or r10, r10, r12
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iseleq r12, r12, r10
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#ifdef CONFIG_PTE_64BIT
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2: rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */
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@ -295,10 +295,10 @@ extern int icache_44x_need_flush;
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#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
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#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
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#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
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#define _PAGE_ACCESSED 0x00004 /* S: Page referenced */
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#define _PAGE_HWWRITE 0x00008 /* H: Dirty & RW, set in exception */
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#define _PAGE_RW 0x00010 /* S: Write permission */
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#define _PAGE_HWEXEC 0x00020 /* H: UX permission */
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#define _PAGE_RW 0x00004 /* S: Write permission (SW) */
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#define _PAGE_DIRTY 0x00008 /* S: Page dirty */
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#define _PAGE_HWEXEC 0x00010 /* H: SX permission */
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#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
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#define _PAGE_ENDIAN 0x00040 /* H: E bit */
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#define _PAGE_GUARDED 0x00080 /* H: G bit */
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@ -307,21 +307,14 @@ extern int icache_44x_need_flush;
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#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
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#ifdef CONFIG_PTE_64BIT
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#define _PAGE_DIRTY 0x08000 /* S: Page dirty */
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/* ERPN in a PTE never gets cleared, ignore it */
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#define _PTE_NONE_MASK 0xffffffffffff0000ULL
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#else
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#define _PAGE_DIRTY 0x00800 /* S: Page dirty */
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#endif
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#define _PMD_PRESENT 0
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#define _PMD_PRESENT_MASK (PAGE_MASK)
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#define _PMD_BAD (~PAGE_MASK)
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/* Until my rework is finished, FSL BookE still needs atomic PTE updates */
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#define PTE_ATOMIC_UPDATES 1
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#elif defined(CONFIG_8xx)
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/* Definitions for 8xx embedded chips. */
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#define _PAGE_PRESENT 0x0001 /* Page is valid */
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