powerpc/4xx: Extended DCR support v2
This adds supports to the "extended" DCR addressing via the indirect mfdcrx/mtdcrx instructions supported by some 4xx cores (440H6 and later). I enabled the feature for now only on AMCC 460 chips. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
Paul Mackerras
Родитель
fecba96268
Коммит
6d2170be45
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@ -164,6 +164,7 @@ extern const char *powerpc_base_platform;
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#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
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#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
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#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000)
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#define CPU_FTR_INDEXED_DCR ASM_CONST(0x0000000020000000)
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/*
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* Add the 64-bit processor unique features in the top half of the word;
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@ -369,6 +370,8 @@ extern const char *powerpc_base_platform;
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#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
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#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
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#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
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#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
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CPU_FTR_INDEXED_DCR)
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#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
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CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
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CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
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@ -455,7 +458,7 @@ enum {
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CPU_FTRS_40X |
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#endif
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#ifdef CONFIG_44x
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CPU_FTRS_44X |
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CPU_FTRS_44X | CPU_FTRS_440x6 |
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#endif
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#ifdef CONFIG_E200
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CPU_FTRS_E200 |
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@ -495,7 +498,7 @@ enum {
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CPU_FTRS_40X &
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#endif
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#ifdef CONFIG_44x
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CPU_FTRS_44X &
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CPU_FTRS_44X & CPU_FTRS_440x6 &
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#endif
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#ifdef CONFIG_E200
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CPU_FTRS_E200 &
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@ -23,6 +23,7 @@
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#ifndef __ASSEMBLY__
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#include <linux/spinlock.h>
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#include <asm/cputable.h>
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typedef struct {
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unsigned int base;
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@ -39,23 +40,45 @@ static inline bool dcr_map_ok_native(dcr_host_native_t host)
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#define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)
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#define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
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/* Device Control Registers */
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void __mtdcr(int reg, unsigned int val);
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unsigned int __mfdcr(int reg);
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/* Table based DCR accessors */
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extern void __mtdcr(unsigned int reg, unsigned int val);
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extern unsigned int __mfdcr(unsigned int reg);
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/* mfdcrx/mtdcrx instruction based accessors. We hand code
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* the opcodes in order not to depend on newer binutils
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*/
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static inline unsigned int mfdcrx(unsigned int reg)
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{
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unsigned int ret;
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asm volatile(".long 0x7c000206 | (%0 << 21) | (%1 << 16)"
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: "=r" (ret) : "r" (reg));
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return ret;
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}
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static inline void mtdcrx(unsigned int reg, unsigned int val)
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{
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asm volatile(".long 0x7c000306 | (%0 << 21) | (%1 << 16)"
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: : "r" (val), "r" (reg));
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}
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#define mfdcr(rn) \
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({unsigned int rval; \
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if (__builtin_constant_p(rn)) \
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if (__builtin_constant_p(rn) && rn < 1024) \
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asm volatile("mfdcr %0," __stringify(rn) \
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: "=r" (rval)); \
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else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \
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rval = mfdcrx(rn); \
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else \
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rval = __mfdcr(rn); \
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rval;})
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#define mtdcr(rn, v) \
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do { \
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if (__builtin_constant_p(rn)) \
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if (__builtin_constant_p(rn) && rn < 1024) \
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asm volatile("mtdcr " __stringify(rn) ",%0" \
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: : "r" (v)); \
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else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \
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mtdcrx(rn, v); \
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else \
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__mtdcr(rn, v); \
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} while (0)
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@ -69,8 +92,13 @@ static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
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unsigned int val;
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spin_lock_irqsave(&dcr_ind_lock, flags);
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__mtdcr(base_addr, reg);
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val = __mfdcr(base_data);
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if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
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mtdcrx(base_addr, reg);
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val = mfdcrx(base_data);
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} else {
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__mtdcr(base_addr, reg);
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val = __mfdcr(base_data);
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}
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spin_unlock_irqrestore(&dcr_ind_lock, flags);
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return val;
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}
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@ -81,8 +109,13 @@ static inline void __mtdcri(int base_addr, int base_data, int reg,
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unsigned long flags;
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spin_lock_irqsave(&dcr_ind_lock, flags);
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__mtdcr(base_addr, reg);
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__mtdcr(base_data, val);
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if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
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mtdcrx(base_addr, reg);
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mtdcrx(base_data, val);
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} else {
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__mtdcr(base_addr, reg);
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__mtdcr(base_data, val);
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}
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spin_unlock_irqrestore(&dcr_ind_lock, flags);
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}
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@ -93,9 +126,15 @@ static inline void __dcri_clrset(int base_addr, int base_data, int reg,
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unsigned int val;
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spin_lock_irqsave(&dcr_ind_lock, flags);
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__mtdcr(base_addr, reg);
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val = (__mfdcr(base_data) & ~clr) | set;
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__mtdcr(base_data, val);
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if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
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mtdcrx(base_addr, reg);
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val = (mfdcrx(base_data) & ~clr) | set;
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mtdcrx(base_data, val);
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} else {
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__mtdcr(base_addr, reg);
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val = (__mfdcr(base_data) & ~clr) | set;
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__mtdcr(base_data, val);
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}
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spin_unlock_irqrestore(&dcr_ind_lock, flags);
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}
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@ -1509,7 +1509,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.pvr_mask = 0xffff0002,
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.pvr_value = 0x13020002,
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.cpu_name = "460EX",
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.cpu_features = CPU_FTRS_44X,
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.cpu_features = CPU_FTRS_440x6,
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.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@ -1521,7 +1521,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.pvr_mask = 0xffff0002,
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.pvr_value = 0x13020000,
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.cpu_name = "460GT",
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.cpu_features = CPU_FTRS_44X,
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.cpu_features = CPU_FTRS_440x6,
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.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@ -11,14 +11,20 @@
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#include <asm/ppc_asm.h>
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#include <asm/processor.h>
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#include <asm/bug.h>
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#define DCR_ACCESS_PROLOG(table) \
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cmpli cr0,r3,1024; \
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rlwinm r3,r3,4,18,27; \
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lis r5,table@h; \
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ori r5,r5,table@l; \
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add r3,r3,r5; \
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bge- 1f; \
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mtctr r3; \
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bctr
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bctr; \
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1: trap; \
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EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0; \
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blr
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_GLOBAL(__mfdcr)
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DCR_ACCESS_PROLOG(__mfdcr_table)
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