dt-bindings: clk: qcom: Document MSM8976 Global Clock Controller
Document the required properties and firmware clocks for gcc-msm8976 to operate nominally, and add header definitions for referencing the clocks from firmware. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211208091036.132334-2-marijn.suijten@somainline.org
This commit is contained in:
Marijn Suijten
Bjorn Andersson
Родитель
db0c944ee9
Коммит
6d24d9546d
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for MSM8976
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on MSM8976.
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See also:
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- dt-bindings/clock/qcom,gcc-msm8976.h
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properties:
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compatible:
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enum:
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- qcom,gcc-msm8976
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- qcom,gcc-msm8976-v1.1
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clocks:
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items:
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- description: XO source
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- description: Always-on XO source
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- description: Pixel clock from DSI PHY0
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY1
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- description: Byte clock from DSI PHY1
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clock-names:
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items:
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- const: xo
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- const: xo_a
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- const: dsi0pll
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- const: dsi0pllbyte
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- const: dsi1pll
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- const: dsi1pllbyte
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vdd_gfx-supply:
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description:
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Phandle to voltage regulator providing power to the GX domain.
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- vdd_gfx-supply
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@1800000 {
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compatible = "qcom,gcc-msm8976";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0x1800000 0x80000>;
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clocks = <&xo_board>,
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<&xo_board>,
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<&dsi0_phy 1>,
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<&dsi0_phy 0>,
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<&dsi1_phy 1>,
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<&dsi1_phy 0>;
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clock-names = "xo",
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"xo_a",
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"dsi0pll",
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"dsi0pllbyte",
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"dsi1pll",
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"dsi1pllbyte";
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vdd_gfx-supply = <&pm8004_s5>;
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};
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...
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2016, The Linux Foundation. All rights reserved.
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* Copyright (C) 2016-2021, AngeloGioacchino Del Regno
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* <angelogioacchino.delregno@somainline.org>
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*/
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#ifndef _DT_BINDINGS_CLK_MSM_GCC_8976_H
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#define _DT_BINDINGS_CLK_MSM_GCC_8976_H
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#define GPLL0 0
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#define GPLL2 1
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#define GPLL3 2
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#define GPLL4 3
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#define GPLL6 4
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#define GPLL0_CLK_SRC 5
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#define GPLL2_CLK_SRC 6
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#define GPLL3_CLK_SRC 7
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#define GPLL4_CLK_SRC 8
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#define GPLL6_CLK_SRC 9
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 10
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 11
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 12
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 13
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 14
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 15
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 16
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 17
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#define GCC_BLSP1_UART1_APPS_CLK 18
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#define GCC_BLSP1_UART2_APPS_CLK 19
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#define GCC_BLSP2_QUP1_I2C_APPS_CLK 20
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#define GCC_BLSP2_QUP1_SPI_APPS_CLK 21
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#define GCC_BLSP2_QUP2_I2C_APPS_CLK 22
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#define GCC_BLSP2_QUP2_SPI_APPS_CLK 23
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#define GCC_BLSP2_QUP3_I2C_APPS_CLK 24
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#define GCC_BLSP2_QUP3_SPI_APPS_CLK 25
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#define GCC_BLSP2_QUP4_I2C_APPS_CLK 26
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#define GCC_BLSP2_QUP4_SPI_APPS_CLK 27
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#define GCC_BLSP2_UART1_APPS_CLK 28
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#define GCC_BLSP2_UART2_APPS_CLK 29
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#define GCC_CAMSS_CCI_AHB_CLK 30
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#define GCC_CAMSS_CCI_CLK 31
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#define GCC_CAMSS_CPP_AHB_CLK 32
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#define GCC_CAMSS_CPP_AXI_CLK 33
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#define GCC_CAMSS_CPP_CLK 34
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#define GCC_CAMSS_CSI0_AHB_CLK 35
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#define GCC_CAMSS_CSI0_CLK 36
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#define GCC_CAMSS_CSI0PHY_CLK 37
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#define GCC_CAMSS_CSI0PIX_CLK 38
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#define GCC_CAMSS_CSI0RDI_CLK 39
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#define GCC_CAMSS_CSI1_AHB_CLK 40
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#define GCC_CAMSS_CSI1_CLK 41
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#define GCC_CAMSS_CSI1PHY_CLK 42
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#define GCC_CAMSS_CSI1PIX_CLK 43
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#define GCC_CAMSS_CSI1RDI_CLK 44
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#define GCC_CAMSS_CSI2_AHB_CLK 45
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#define GCC_CAMSS_CSI2_CLK 46
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#define GCC_CAMSS_CSI2PHY_CLK 47
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#define GCC_CAMSS_CSI2PIX_CLK 48
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#define GCC_CAMSS_CSI2RDI_CLK 49
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#define GCC_CAMSS_CSI_VFE0_CLK 50
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#define GCC_CAMSS_CSI_VFE1_CLK 51
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#define GCC_CAMSS_GP0_CLK 52
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#define GCC_CAMSS_GP1_CLK 53
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#define GCC_CAMSS_ISPIF_AHB_CLK 54
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#define GCC_CAMSS_JPEG0_CLK 55
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#define GCC_CAMSS_JPEG_AHB_CLK 56
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#define GCC_CAMSS_JPEG_AXI_CLK 57
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#define GCC_CAMSS_MCLK0_CLK 58
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#define GCC_CAMSS_MCLK1_CLK 59
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#define GCC_CAMSS_MCLK2_CLK 60
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#define GCC_CAMSS_MICRO_AHB_CLK 61
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#define GCC_CAMSS_CSI0PHYTIMER_CLK 62
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#define GCC_CAMSS_CSI1PHYTIMER_CLK 63
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#define GCC_CAMSS_AHB_CLK 64
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#define GCC_CAMSS_TOP_AHB_CLK 65
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#define GCC_CAMSS_VFE0_CLK 66
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#define GCC_CAMSS_VFE_AHB_CLK 67
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#define GCC_CAMSS_VFE_AXI_CLK 68
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#define GCC_CAMSS_VFE1_AHB_CLK 69
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#define GCC_CAMSS_VFE1_AXI_CLK 70
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#define GCC_CAMSS_VFE1_CLK 71
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#define GCC_DCC_CLK 72
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#define GCC_GP1_CLK 73
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#define GCC_GP2_CLK 74
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#define GCC_GP3_CLK 75
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#define GCC_MDSS_AHB_CLK 76
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#define GCC_MDSS_AXI_CLK 77
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#define GCC_MDSS_ESC0_CLK 78
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#define GCC_MDSS_ESC1_CLK 79
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#define GCC_MDSS_MDP_CLK 80
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#define GCC_MDSS_VSYNC_CLK 81
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#define GCC_MSS_CFG_AHB_CLK 82
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#define GCC_MSS_Q6_BIMC_AXI_CLK 83
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#define GCC_PDM2_CLK 84
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#define GCC_PRNG_AHB_CLK 85
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#define GCC_PDM_AHB_CLK 86
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#define GCC_RBCPR_GFX_AHB_CLK 87
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#define GCC_RBCPR_GFX_CLK 88
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#define GCC_SDCC1_AHB_CLK 89
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#define GCC_SDCC1_APPS_CLK 90
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#define GCC_SDCC1_ICE_CORE_CLK 91
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#define GCC_SDCC2_AHB_CLK 92
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#define GCC_SDCC2_APPS_CLK 93
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#define GCC_SDCC3_AHB_CLK 94
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#define GCC_SDCC3_APPS_CLK 95
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#define GCC_USB2A_PHY_SLEEP_CLK 96
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#define GCC_USB_HS_PHY_CFG_AHB_CLK 97
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#define GCC_USB_FS_AHB_CLK 98
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#define GCC_USB_FS_IC_CLK 99
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#define GCC_USB_FS_SYSTEM_CLK 100
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#define GCC_USB_HS_AHB_CLK 101
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#define GCC_USB_HS_SYSTEM_CLK 102
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#define GCC_VENUS0_AHB_CLK 103
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#define GCC_VENUS0_AXI_CLK 104
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#define GCC_VENUS0_CORE0_VCODEC0_CLK 105
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#define GCC_VENUS0_CORE1_VCODEC0_CLK 106
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#define GCC_VENUS0_VCODEC0_CLK 107
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#define GCC_APSS_AHB_CLK 108
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#define GCC_APSS_AXI_CLK 109
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#define GCC_BLSP1_AHB_CLK 110
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#define GCC_BLSP2_AHB_CLK 111
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#define GCC_BOOT_ROM_AHB_CLK 112
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#define GCC_CRYPTO_AHB_CLK 113
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#define GCC_CRYPTO_AXI_CLK 114
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#define GCC_CRYPTO_CLK 115
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#define GCC_CPP_TBU_CLK 116
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#define GCC_APSS_TCU_CLK 117
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#define GCC_JPEG_TBU_CLK 118
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#define GCC_MDP_RT_TBU_CLK 119
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#define GCC_MDP_TBU_CLK 120
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#define GCC_SMMU_CFG_CLK 121
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#define GCC_VENUS_1_TBU_CLK 122
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#define GCC_VENUS_TBU_CLK 123
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#define GCC_VFE1_TBU_CLK 124
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#define GCC_VFE_TBU_CLK 125
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#define GCC_APS_0_CLK 126
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#define GCC_APS_1_CLK 127
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#define APS_0_CLK_SRC 128
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#define APS_1_CLK_SRC 129
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#define APSS_AHB_CLK_SRC 130
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 131
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 132
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 133
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 134
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 135
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 136
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 137
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 138
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#define BLSP1_UART1_APPS_CLK_SRC 139
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#define BLSP1_UART2_APPS_CLK_SRC 140
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#define BLSP2_QUP1_I2C_APPS_CLK_SRC 141
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#define BLSP2_QUP1_SPI_APPS_CLK_SRC 142
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#define BLSP2_QUP2_I2C_APPS_CLK_SRC 143
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#define BLSP2_QUP2_SPI_APPS_CLK_SRC 144
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#define BLSP2_QUP3_I2C_APPS_CLK_SRC 145
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#define BLSP2_QUP3_SPI_APPS_CLK_SRC 146
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#define BLSP2_QUP4_I2C_APPS_CLK_SRC 147
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#define BLSP2_QUP4_SPI_APPS_CLK_SRC 148
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#define BLSP2_UART1_APPS_CLK_SRC 149
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#define BLSP2_UART2_APPS_CLK_SRC 150
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#define CCI_CLK_SRC 151
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#define CPP_CLK_SRC 152
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#define CSI0_CLK_SRC 153
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#define CSI1_CLK_SRC 154
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#define CSI2_CLK_SRC 155
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#define CAMSS_GP0_CLK_SRC 156
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#define CAMSS_GP1_CLK_SRC 157
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#define JPEG0_CLK_SRC 158
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#define MCLK0_CLK_SRC 159
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#define MCLK1_CLK_SRC 160
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#define MCLK2_CLK_SRC 161
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#define CSI0PHYTIMER_CLK_SRC 162
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#define CSI1PHYTIMER_CLK_SRC 163
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#define CAMSS_TOP_AHB_CLK_SRC 164
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#define VFE0_CLK_SRC 165
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#define VFE1_CLK_SRC 166
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#define CRYPTO_CLK_SRC 167
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#define GP1_CLK_SRC 168
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#define GP2_CLK_SRC 169
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#define GP3_CLK_SRC 170
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#define ESC0_CLK_SRC 171
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#define ESC1_CLK_SRC 172
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#define MDP_CLK_SRC 173
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#define VSYNC_CLK_SRC 174
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#define PDM2_CLK_SRC 175
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#define RBCPR_GFX_CLK_SRC 176
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#define SDCC1_APPS_CLK_SRC 177
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#define SDCC1_ICE_CORE_CLK_SRC 178
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#define SDCC2_APPS_CLK_SRC 179
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#define SDCC3_APPS_CLK_SRC 180
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#define USB_FS_IC_CLK_SRC 181
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#define USB_FS_SYSTEM_CLK_SRC 182
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#define USB_HS_SYSTEM_CLK_SRC 183
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#define VCODEC0_CLK_SRC 184
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#define GCC_MDSS_BYTE0_CLK_SRC 185
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#define GCC_MDSS_BYTE1_CLK_SRC 186
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#define GCC_MDSS_BYTE0_CLK 187
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#define GCC_MDSS_BYTE1_CLK 188
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#define GCC_MDSS_PCLK0_CLK_SRC 189
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#define GCC_MDSS_PCLK1_CLK_SRC 190
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#define GCC_MDSS_PCLK0_CLK 191
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#define GCC_MDSS_PCLK1_CLK 192
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#define GCC_GFX3D_CLK_SRC 193
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#define GCC_GFX3D_OXILI_CLK 194
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#define GCC_GFX3D_BIMC_CLK 195
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#define GCC_GFX3D_OXILI_AHB_CLK 196
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#define GCC_GFX3D_OXILI_AON_CLK 197
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#define GCC_GFX3D_OXILI_GMEM_CLK 198
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#define GCC_GFX3D_OXILI_TIMER_CLK 199
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#define GCC_GFX3D_TBU0_CLK 200
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#define GCC_GFX3D_TBU1_CLK 201
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#define GCC_GFX3D_TCU_CLK 202
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#define GCC_GFX3D_GTCU_AHB_CLK 203
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/* GCC block resets */
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#define RST_CAMSS_MICRO_BCR 0
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#define RST_USB_HS_BCR 1
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#define RST_QUSB2_PHY_BCR 2
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#define RST_USB2_HS_PHY_ONLY_BCR 3
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#define RST_USB_HS_PHY_CFG_AHB_BCR 4
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#define RST_USB_FS_BCR 5
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#define RST_CAMSS_CSI1PIX_BCR 6
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#define RST_CAMSS_CSI_VFE1_BCR 7
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#define RST_CAMSS_VFE1_BCR 8
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#define RST_CAMSS_CPP_BCR 9
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/* GDSCs */
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#define VENUS_GDSC 0
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#define VENUS_CORE0_GDSC 1
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#define VENUS_CORE1_GDSC 2
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#define MDSS_GDSC 3
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#define JPEG_GDSC 4
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#define VFE0_GDSC 5
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#define VFE1_GDSC 6
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#define CPP_GDSC 7
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#define OXILI_GX_GDSC 8
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#define OXILI_CX_GDSC 9
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#endif /* _DT_BINDINGS_CLK_MSM_GCC_8976_H */
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