drm fixes for 5.5-rc6
core: - mst Fix NO_STOP_BIT bit offset (Wayne) fb_helper: - fb_helper: Fix bits_per_pixel param set behavior to round up (Geert) sun4i: - Fix RGB_DIV clock min divider on old hardware (Chen-Yu) amdgpu: - Stability fix for raven - Reduce pixel encoding to if max clock is exceeded on HDMI to allow additional high res modes - enable DRIVER_SYNCOBJ_TIMELINE for amdgpu i915: - Fix GitLab issue #446 causing GPU hangs: Do not restore invalid RS state - Fix GitLab issue #846: Restore coarse power gating that was disabled by initial RC66 context corruption security fixes. - Revertf6ec948309("drm/i915: extend audio CDCLK>=2*BCLK constraint to more platforms") to avoid screen flicker - Fix to fill in unitialized uabi_instance in virtual engine uAPI - Add two missing W/As for ICL and EHL -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJeF/BHAAoJEAx081l5xIa+ZXIP/1QnW01qbYbhjtZng73taeAF Fj8WbSsek8NZqkXMFt/BbPhTnC1udTjb60MYp0drW0XZAEyOuU9lPzgDzhq7ktj3 0ZUhhArnyZAcBHMLstWSlj8m4xNRJIrQkP758nMg5/iUvPL8WEAG2LFhuxxqYK65 3gCUtxXDoQbmy2F5V/LsCUGC50EiL21rdV0OYhYtevA+dwJwI/p1aCmnFFBCXf+l mDolL5F1Kt3PIRPaP5AREqaIBRqUqqs8RL3fA1z60qTLtq7uYlFkAzXNboJrOsWF 3UG/0EX24xkO98BxEERSNJ04ZFqgf13ut92tWhWKQwvAKn1CGY2iO9oO8OIhWJBY F1AV7cRpAwA1wHzbyxk80sMveyd0yuM3VzSLk/iCg6meM1qvfpkaGqAl7i10QJkf 1eqkDVRlpWzQ9b+0+zM/5/uFO4+dQpHxgw7hyxtL1IPulKNo2RI04If3plXgv+2l 1iOqDMpit2z8wc/x9CQUaV6BUrdZKSHU1KhRjZlX2qw2KL15UBfozCDdT1+wJ55Q XW+UE8+ZbbyfLqi3Y35vTM+mVOL5uUAj+1N0Zo/JjcDiVTBjHhDk4GGPog0e4bG5 CczqetOIozY7NhACJw5YenNEchDl/3BURRnVMwCaCro38FN8h40psQmcoeXoH3K/ bJR15rRdoJr/QL1rTNzz =YPe6 -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2020-01-10' of git://anongit.freedesktop.org/drm/drm Pull drm fixes from Dave Airlie: "Pre-LCA pull request I'm not sure how things will look next week, myself and Daniel are at LCA and I'm speaking quite late, so if I get my talk finished I'll probably process fixes. This week has a bunch of i915 fixes, some amdgpu fixes, one sun4i, one core MST, and one core fb_helper fix. More details below: core: - mst Fix NO_STOP_BIT bit offset (Wayne) fb_helper: - fb_helper: Fix bits_per_pixel param set behavior to round up (Geert) sun4i: - Fix RGB_DIV clock min divider on old hardware (Chen-Yu) amdgpu: - Stability fix for raven - Reduce pixel encoding to if max clock is exceeded on HDMI to allow additional high res modes - enable DRIVER_SYNCOBJ_TIMELINE for amdgpu i915: - Fix GitLab issue #446 causing GPU hangs: Do not restore invalid RS state - Fix GitLab issue #846: Restore coarse power gating that was disabled by initial RC66 context corruption security fixes. - Revertf6ec948309("drm/i915: extend audio CDCLK>=2*BCLK constraint to more platforms") to avoid screen flicker - Fix to fill in unitialized uabi_instance in virtual engine uAPI - Add two missing W/As for ICL and EHL" * tag 'drm-fixes-2020-01-10' of git://anongit.freedesktop.org/drm/drm: drm/amdgpu: add DRIVER_SYNCOBJ_TIMELINE to amdgpu drm/amd/display: Reduce HDMI pixel encoding if max clock is exceeded Revert "drm/amdgpu: Set no-retry as default." drm/fb-helper: Round up bits_per_pixel if possible drm/sun4i: tcon: Set RGB DCLK min. divider based on hardware model drm/i915/dp: Disable Port sync mode correctly on teardown drm/i915: Add Wa_1407352427:icl,ehl drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehl drm/i915/gt: Restore coarse power gating drm/i915/gt: Do not restore invalid RS state drm/i915: Limit audio CDCLK>=2*BCLK constraint back to GLK only drm/i915/gt: Mark up virtual engine uabi_instance drm/dp_mst: correct the shifting in DP_REMOTE_I2C_READ
This commit is contained in:
Linus Torvalds
Коммит
6d25ef7735
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@ -142,7 +142,7 @@ int amdgpu_async_gfx_ring = 1;
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int amdgpu_mcbp = 0;
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int amdgpu_discovery = -1;
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int amdgpu_mes = 0;
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int amdgpu_noretry = 1;
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int amdgpu_noretry;
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int amdgpu_force_asic_type = -1;
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struct amdgpu_mgpu_info mgpu_info = {
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@ -588,7 +588,7 @@ MODULE_PARM_DESC(mes,
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module_param_named(mes, amdgpu_mes, int, 0444);
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MODULE_PARM_DESC(noretry,
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"Disable retry faults (0 = retry enabled, 1 = retry disabled (default))");
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"Disable retry faults (0 = retry enabled (default), 1 = retry disabled)");
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module_param_named(noretry, amdgpu_noretry, int, 0644);
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/**
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@ -1359,7 +1359,8 @@ static struct drm_driver kms_driver = {
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.driver_features =
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DRIVER_USE_AGP | DRIVER_ATOMIC |
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DRIVER_GEM |
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DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
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DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
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DRIVER_SYNCOBJ_TIMELINE,
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.load = amdgpu_driver_load_kms,
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.open = amdgpu_driver_open_kms,
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.postclose = amdgpu_driver_postclose_kms,
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@ -3356,27 +3356,21 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
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return color_space;
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}
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static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
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{
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if (timing_out->display_color_depth <= COLOR_DEPTH_888)
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return;
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timing_out->display_color_depth--;
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}
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static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
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const struct drm_display_info *info)
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static bool adjust_colour_depth_from_display_info(
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struct dc_crtc_timing *timing_out,
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const struct drm_display_info *info)
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{
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enum dc_color_depth depth = timing_out->display_color_depth;
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int normalized_clk;
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if (timing_out->display_color_depth <= COLOR_DEPTH_888)
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return;
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do {
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normalized_clk = timing_out->pix_clk_100hz / 10;
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/* YCbCr 4:2:0 requires additional adjustment of 1/2 */
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if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
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normalized_clk /= 2;
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/* Adjusting pix clock following on HDMI spec based on colour depth */
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switch (timing_out->display_color_depth) {
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switch (depth) {
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case COLOR_DEPTH_888:
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break;
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case COLOR_DEPTH_101010:
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normalized_clk = (normalized_clk * 30) / 24;
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break;
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@ -3387,14 +3381,15 @@ static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_
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normalized_clk = (normalized_clk * 48) / 24;
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break;
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default:
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return;
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/* The above depths are the only ones valid for HDMI. */
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return false;
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}
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if (normalized_clk <= info->max_tmds_clock)
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return;
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reduce_mode_colour_depth(timing_out);
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} while (timing_out->display_color_depth > COLOR_DEPTH_888);
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if (normalized_clk <= info->max_tmds_clock) {
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timing_out->display_color_depth = depth;
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return true;
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}
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} while (--depth > COLOR_DEPTH_666);
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return false;
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}
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static void fill_stream_properties_from_drm_display_mode(
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@ -3474,8 +3469,14 @@ static void fill_stream_properties_from_drm_display_mode(
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stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
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stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
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if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
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adjust_colour_depth_from_display_info(timing_out, info);
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if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
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if (!adjust_colour_depth_from_display_info(timing_out, info) &&
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drm_mode_is_420_also(info, mode_in) &&
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timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
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timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
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adjust_colour_depth_from_display_info(timing_out, info);
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}
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}
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}
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static void fill_audio_info(struct audio_info *audio_info,
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@ -393,7 +393,7 @@ drm_dp_encode_sideband_req(const struct drm_dp_sideband_msg_req_body *req,
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memcpy(&buf[idx], req->u.i2c_read.transactions[i].bytes, req->u.i2c_read.transactions[i].num_bytes);
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idx += req->u.i2c_read.transactions[i].num_bytes;
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buf[idx] = (req->u.i2c_read.transactions[i].no_stop_bit & 0x1) << 5;
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buf[idx] = (req->u.i2c_read.transactions[i].no_stop_bit & 0x1) << 4;
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buf[idx] |= (req->u.i2c_read.transactions[i].i2c_transaction_delay & 0xf);
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idx++;
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}
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@ -1283,7 +1283,7 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
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* Changes struct fb_var_screeninfo are currently not pushed back
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* to KMS, hence fail if different settings are requested.
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*/
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if (var->bits_per_pixel != fb->format->cpp[0] * 8 ||
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if (var->bits_per_pixel > fb->format->cpp[0] * 8 ||
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var->xres > fb->width || var->yres > fb->height ||
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var->xres_virtual > fb->width || var->yres_virtual > fb->height) {
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DRM_DEBUG("fb requested width/height/bpp can't fit in current fb "
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@ -1308,6 +1308,11 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
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drm_fb_helper_fill_pixel_fmt(var, fb->format->depth);
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}
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/*
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* Likewise, bits_per_pixel should be rounded up to a supported value.
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*/
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var->bits_per_pixel = fb->format->cpp[0] * 8;
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/*
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* drm fbdev emulation doesn't support changing the pixel format at all,
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* so reject all pixel format changing requests.
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@ -856,7 +856,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
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}
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/* Force CDCLK to 2*BCLK as long as we need audio powered. */
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if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
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if (IS_GEMINILAKE(dev_priv))
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glk_force_audio_cdclk(dev_priv, true);
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if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
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@ -875,7 +875,7 @@ static void i915_audio_component_put_power(struct device *kdev,
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/* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
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if (--dev_priv->audio_power_refcount == 0)
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if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
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if (IS_GEMINILAKE(dev_priv))
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glk_force_audio_cdclk(dev_priv, false);
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intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
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@ -4515,8 +4515,6 @@ static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_
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{
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struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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i915_reg_t reg;
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u32 trans_ddi_func_ctl2_val;
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if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
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return;
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@ -4524,10 +4522,7 @@ static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_
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DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
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transcoder_name(old_crtc_state->cpu_transcoder));
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reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
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trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
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PORT_SYNC_MODE_MASTER_SELECT_MASK);
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I915_WRITE(reg, trans_ddi_func_ctl2_val);
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I915_WRITE(TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder), 0);
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}
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static void intel_fdi_normal_train(struct intel_crtc *crtc)
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@ -4416,9 +4416,11 @@ intel_execlists_create_virtual(struct i915_gem_context *ctx,
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ve->base.gt = siblings[0]->gt;
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ve->base.uncore = siblings[0]->uncore;
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ve->base.id = -1;
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ve->base.class = OTHER_CLASS;
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ve->base.uabi_class = I915_ENGINE_CLASS_INVALID;
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ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
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ve->base.uabi_instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
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/*
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* The decision on whether to submit a request using semaphores
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@ -1413,14 +1413,6 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
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int len;
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u32 *cs;
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flags |= MI_MM_SPACE_GTT;
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if (IS_HASWELL(i915))
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/* These flags are for resource streamer on HSW+ */
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flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
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else
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/* We need to save the extended state for powersaving modes */
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flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
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len = 4;
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if (IS_GEN(i915, 7))
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len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
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@ -1589,22 +1581,21 @@ static int switch_context(struct i915_request *rq)
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}
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if (ce->state) {
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u32 hw_flags;
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u32 flags;
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GEM_BUG_ON(rq->engine->id != RCS0);
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/*
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* The kernel context(s) is treated as pure scratch and is not
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* expected to retain any state (as we sacrifice it during
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* suspend and on resume it may be corrupted). This is ok,
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* as nothing actually executes using the kernel context; it
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* is purely used for flushing user contexts.
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*/
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hw_flags = 0;
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if (i915_gem_context_is_kernel(rq->gem_context))
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hw_flags = MI_RESTORE_INHIBIT;
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/* For resource streamer on HSW+ and power context elsewhere */
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BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN != MI_SAVE_EXT_STATE_EN);
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BUILD_BUG_ON(HSW_MI_RS_RESTORE_STATE_EN != MI_RESTORE_EXT_STATE_EN);
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ret = mi_set_context(rq, hw_flags);
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flags = MI_SAVE_EXT_STATE_EN | MI_MM_SPACE_GTT;
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if (!i915_gem_context_is_kernel(rq->gem_context))
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flags |= MI_RESTORE_EXT_STATE_EN;
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else
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flags |= MI_RESTORE_INHIBIT;
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ret = mi_set_context(rq, flags);
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if (ret)
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return ret;
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}
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|
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@ -1660,8 +1660,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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(IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
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/* WaRsDisableCoarsePowerGating:skl,cnl */
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#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
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(IS_CANNONLAKE(dev_priv) || IS_GEN(dev_priv, 9))
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#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
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(IS_CANNONLAKE(dev_priv) || \
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IS_SKL_GT3(dev_priv) || \
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IS_SKL_GT4(dev_priv))
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|
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#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
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#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
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|
|
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|
|
@ -4177,7 +4177,13 @@ enum {
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#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
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#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
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#define VFUNIT_CLKGATE_DIS (1 << 20)
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#define VFUNIT_CLKGATE_DIS REG_BIT(20)
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#define HSUNIT_CLKGATE_DIS REG_BIT(8)
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#define VSUNIT_CLKGATE_DIS REG_BIT(3)
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#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
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#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
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#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
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|
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#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
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#define CGPSF_CLKGATE_DIS (1 << 3)
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|
|
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|
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@ -6565,6 +6565,17 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
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/* WaEnable32PlaneMode:icl */
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I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
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_MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
|
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|
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/*
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* Wa_1408615072:icl,ehl (vsunit)
|
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* Wa_1407596294:icl,ehl (hsunit)
|
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*/
|
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intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE,
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0, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
|
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|
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/* Wa_1407352427:icl,ehl */
|
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intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
|
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0, PSDUNIT_CLKGATE_DIS);
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}
|
||||
|
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static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
|
||||
|
|
|
|||
|
|
@ -489,7 +489,7 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
|
|||
|
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WARN_ON(!tcon->quirks->has_channel_0);
|
||||
|
||||
tcon->dclk_min_div = 1;
|
||||
tcon->dclk_min_div = tcon->quirks->dclk_min_div;
|
||||
tcon->dclk_max_div = 127;
|
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sun4i_tcon0_mode_set_common(tcon, mode);
|
||||
|
||||
|
|
@ -1426,12 +1426,14 @@ static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon,
|
|||
static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
|
||||
.has_channel_0 = true,
|
||||
.has_channel_1 = true,
|
||||
.dclk_min_div = 4,
|
||||
.set_mux = sun4i_a10_tcon_set_mux,
|
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};
|
||||
|
||||
static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
|
||||
.has_channel_0 = true,
|
||||
.has_channel_1 = true,
|
||||
.dclk_min_div = 4,
|
||||
.set_mux = sun5i_a13_tcon_set_mux,
|
||||
};
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||||
|
||||
|
|
@ -1440,6 +1442,7 @@ static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
|
|||
.has_channel_1 = true,
|
||||
.has_lvds_alt = true,
|
||||
.needs_de_be_mux = true,
|
||||
.dclk_min_div = 1,
|
||||
.set_mux = sun6i_tcon_set_mux,
|
||||
};
|
||||
|
||||
|
|
@ -1447,11 +1450,13 @@ static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
|
|||
.has_channel_0 = true,
|
||||
.has_channel_1 = true,
|
||||
.needs_de_be_mux = true,
|
||||
.dclk_min_div = 1,
|
||||
};
|
||||
|
||||
static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
|
||||
.has_channel_0 = true,
|
||||
.has_channel_1 = true,
|
||||
.dclk_min_div = 4,
|
||||
/* Same display pipeline structure as A10 */
|
||||
.set_mux = sun4i_a10_tcon_set_mux,
|
||||
};
|
||||
|
|
@ -1459,11 +1464,13 @@ static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
|
|||
static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
|
||||
.has_channel_0 = true,
|
||||
.has_lvds_alt = true,
|
||||
.dclk_min_div = 1,
|
||||
};
|
||||
|
||||
static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
|
||||
.supports_lvds = true,
|
||||
.has_channel_0 = true,
|
||||
.dclk_min_div = 1,
|
||||
};
|
||||
|
||||
static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {
|
||||
|
|
@ -1477,11 +1484,13 @@ static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
|
|||
|
||||
static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
|
||||
.has_channel_0 = true,
|
||||
.dclk_min_div = 1,
|
||||
};
|
||||
|
||||
static const struct sun4i_tcon_quirks sun9i_a80_tcon_lcd_quirks = {
|
||||
.has_channel_0 = true,
|
||||
.needs_edp_reset = true,
|
||||
.has_channel_0 = true,
|
||||
.needs_edp_reset = true,
|
||||
.dclk_min_div = 1,
|
||||
};
|
||||
|
||||
static const struct sun4i_tcon_quirks sun9i_a80_tcon_tv_quirks = {
|
||||
|
|
|
|||
|
|
@ -224,6 +224,7 @@ struct sun4i_tcon_quirks {
|
|||
bool needs_de_be_mux; /* sun6i needs mux to select backend */
|
||||
bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */
|
||||
bool supports_lvds; /* Does the TCON support an LVDS output? */
|
||||
u8 dclk_min_div; /* minimum divider for TCON0 DCLK */
|
||||
|
||||
/* callback to handle tcon muxing options */
|
||||
int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);
|
||||
|
|
|
|||
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