drm/i915: s/vlv_num_wm_levels/intel_wm_num_levels/
Rename the VLV/CHV max_level->num_levels helper to have an intel_ prefix since it's not VLV/CHV specific and I'll want to use it on other platforms as well. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170421181432.15216-4-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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868b0c08b2
Коммит
6d5019b681
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@ -648,6 +648,11 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
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return wm_size;
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}
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static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
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{
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return dev_priv->wm.max_level + 1;
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}
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static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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{
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@ -1136,18 +1141,13 @@ static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
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return 0;
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}
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static int vlv_num_wm_levels(struct drm_i915_private *dev_priv)
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{
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return dev_priv->wm.max_level + 1;
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}
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/* mark all levels starting from 'level' as invalid */
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static void vlv_invalidate_wms(struct intel_crtc *crtc,
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struct vlv_wm_state *wm_state, int level)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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for (; level < vlv_num_wm_levels(dev_priv); level++) {
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for (; level < intel_wm_num_levels(dev_priv); level++) {
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enum plane_id plane_id;
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for_each_plane_id_on_crtc(crtc, plane_id)
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@ -1174,7 +1174,7 @@ static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
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int level, enum plane_id plane_id, u16 value)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
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int num_levels = vlv_num_wm_levels(dev_priv);
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int num_levels = intel_wm_num_levels(dev_priv);
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bool dirty = false;
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for (; level < num_levels; level++) {
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@ -1192,7 +1192,7 @@ static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
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{
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struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
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enum plane_id plane_id = plane->id;
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int num_levels = vlv_num_wm_levels(to_i915(plane->base.dev));
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int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
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int level;
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bool dirty = false;
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@ -1306,7 +1306,7 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
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}
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/* initially allow all levels */
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wm_state->num_levels = vlv_num_wm_levels(dev_priv);
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wm_state->num_levels = intel_wm_num_levels(dev_priv);
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/*
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* Note that enabling cxsr with no primary/sprite planes
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* enabled can wedge the pipe. Hence we only allow cxsr
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