iommu/vt-d: Remove deferred invalidation
Deferred invalidation is an ECS specific feature. It will not be supported when IOMMU works in scalable mode. As we deprecated the ECS support, remove deferred invalidation and cleanup the code. Cc: Ashok Raj <ashok.raj@intel.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Kevin Tian <kevin.tian@intel.com> Cc: Liu Yi L <yi.l.liu@intel.com> Cc: Sanjay Kumar <sanjay.k.kumar@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -1700,7 +1700,6 @@ static void free_dmar_iommu(struct intel_iommu *iommu)
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if (pasid_supported(iommu)) {
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if (ecap_prs(iommu->ecap))
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intel_svm_finish_prq(iommu);
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intel_svm_exit(iommu);
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}
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#endif
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}
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@ -31,15 +31,8 @@
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static irqreturn_t prq_event_thread(int irq, void *d);
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struct pasid_state_entry {
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u64 val;
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};
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int intel_svm_init(struct intel_iommu *iommu)
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{
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struct page *pages;
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int order;
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if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
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!cap_fl1gp_support(iommu->cap))
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return -EINVAL;
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@ -48,39 +41,6 @@ int intel_svm_init(struct intel_iommu *iommu)
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!cap_5lp_support(iommu->cap))
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return -EINVAL;
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/* Start at 2 because it's defined as 2^(1+PSS) */
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iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
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/* Eventually I'm promised we will get a multi-level PASID table
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* and it won't have to be physically contiguous. Until then,
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* limit the size because 8MiB contiguous allocations can be hard
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* to come by. The limit of 0x20000, which is 1MiB for each of
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* the PASID and PASID-state tables, is somewhat arbitrary. */
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if (iommu->pasid_max > 0x20000)
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iommu->pasid_max = 0x20000;
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order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
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if (ecap_dis(iommu->ecap)) {
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pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
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if (pages)
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iommu->pasid_state_table = page_address(pages);
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else
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pr_warn("IOMMU: %s: Failed to allocate PASID state table\n",
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iommu->name);
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}
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return 0;
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}
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int intel_svm_exit(struct intel_iommu *iommu)
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{
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int order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
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if (iommu->pasid_state_table) {
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free_pages((unsigned long)iommu->pasid_state_table, order);
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iommu->pasid_state_table = NULL;
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}
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return 0;
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}
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@ -214,11 +174,6 @@ static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
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{
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struct intel_svm_dev *sdev;
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/* Try deferred invalidate if available */
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if (svm->iommu->pasid_state_table &&
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!cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
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return;
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rcu_read_lock();
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list_for_each_entry_rcu(sdev, &svm->devs, list)
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intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
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@ -541,15 +541,8 @@ struct intel_iommu {
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struct iommu_flush flush;
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#endif
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#ifdef CONFIG_INTEL_IOMMU_SVM
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/* These are large and need to be contiguous, so we allocate just
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* one for now. We'll maybe want to rethink that if we truly give
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* devices away to userspace processes (e.g. for DPDK) and don't
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* want to trust that userspace will use *only* the PASID it was
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* told to. But while it's all driver-arbitrated, we're fine. */
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struct pasid_state_entry *pasid_state_table;
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struct page_req_dsc *prq;
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unsigned char prq_name[16]; /* Name for PRQ interrupt */
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u32 pasid_max;
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#endif
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struct q_inval *qi; /* Queued invalidation info */
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u32 *iommu_state; /* Store iommu states between suspend and resume.*/
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@ -663,7 +656,6 @@ void iommu_flush_write_buffer(struct intel_iommu *iommu);
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#ifdef CONFIG_INTEL_IOMMU_SVM
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int intel_svm_init(struct intel_iommu *iommu);
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int intel_svm_exit(struct intel_iommu *iommu);
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extern int intel_svm_enable_prq(struct intel_iommu *iommu);
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extern int intel_svm_finish_prq(struct intel_iommu *iommu);
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