mtd: fsmc_nand: pass the ale and cmd resource via resource
Do not use the platform_data to pass resource and be smart in the drivers. Just pass it via resource Switch to devm_request_and_ioremap at the sametime Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-By: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
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6d7b42a447
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@ -3,9 +3,7 @@
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Required properties:
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- compatible : "st,spear600-fsmc-nand"
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- reg : Address range of the mtd chip
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- reg-names: Should contain the reg names "fsmc_regs" and "nand_data"
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- st,ale-off : Chip specific offset to ALE
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- st,cle-off : Chip specific offset to CLE
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- reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
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Optional properties:
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- bank-width : Width (in bytes) of the device. If not present, the width
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@ -19,10 +17,10 @@ Example:
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xd1800000 0x1000 /* FSMC Register */
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0xd2000000 0x4000>; /* NAND Base */
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reg-names = "fsmc_regs", "nand_data";
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st,ale-off = <0x20000>;
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st,cle-off = <0x10000>;
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0xd2000000 0x0010 /* NAND Base DATA */
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0xd2020000 0x0010 /* NAND Base ADDR */
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0xd2010000 0x0010>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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bank-width = <1>;
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nand-skip-bbtscan;
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@ -104,15 +104,15 @@
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compatible = "st,spear600-fsmc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xb0000000 0x1000 /* FSMC Register */
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0xb0800000 0x0010>; /* NAND Base */
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reg-names = "fsmc_regs", "nand_data";
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reg = <0xb0000000 0x1000 /* FSMC Register*/
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0xb0800000 0x0010 /* NAND Base DATA */
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0xb0820000 0x0010 /* NAND Base ADDR */
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0xb0810000 0x0010>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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interrupts = <0 20 0x4
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0 21 0x4
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0 22 0x4
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0 23 0x4>;
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st,ale-off = <0x20000>;
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st,cle-off = <0x10000>;
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status = "disabled";
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};
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@ -38,10 +38,10 @@
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x94000000 0x1000 /* FSMC Register */
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0x80000000 0x0010>; /* NAND Base */
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reg-names = "fsmc_regs", "nand_data";
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st,ale-off = <0x20000>;
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st,cle-off = <0x10000>;
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0x80000000 0x0010 /* NAND Base DATA */
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0x80020000 0x0010 /* NAND Base ADDR */
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0x80010000 0x0010>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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status = "disabled";
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};
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@ -32,10 +32,10 @@
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x44000000 0x1000 /* FSMC Register */
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0x40000000 0x0010>; /* NAND Base */
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reg-names = "fsmc_regs", "nand_data";
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st,ale-off = <0x10000>;
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st,cle-off = <0x20000>;
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0x40000000 0x0010 /* NAND Base DATA */
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0x40020000 0x0010 /* NAND Base ADDR */
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0x40010000 0x0010>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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status = "disabled";
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};
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@ -38,10 +38,10 @@
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x4c000000 0x1000 /* FSMC Register */
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0x50000000 0x0010>; /* NAND Base */
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reg-names = "fsmc_regs", "nand_data";
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st,ale-off = <0x20000>;
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st,cle-off = <0x10000>;
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0x50000000 0x0010 /* NAND Base DATA */
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0x50020000 0x0010 /* NAND Base ADDR */
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0x50010000 0x0010>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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status = "disabled";
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};
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@ -67,10 +67,10 @@
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xd1800000 0x1000 /* FSMC Register */
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0xd2000000 0x4000>; /* NAND Base */
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reg-names = "fsmc_regs", "nand_data";
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st,ale-off = <0x20000>;
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st,cle-off = <0x10000>;
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0xd2000000 0x0010 /* NAND Base DATA */
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0xd2020000 0x0010 /* NAND Base ADDR */
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0xd2010000 0x0010>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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status = "disabled";
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};
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@ -251,6 +251,18 @@ static struct resource rtc_resources[] = {
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* but these are not yet used by the driver.
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*/
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static struct resource fsmc_resources[] = {
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{
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.name = "nand_addr",
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.start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
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.end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "nand_cmd",
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.start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
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.end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "nand_data",
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.start = U300_NAND_CS0_PHYS_BASE,
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@ -1496,8 +1508,6 @@ static struct fsmc_nand_platform_data nand_platform_data = {
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.nr_partitions = ARRAY_SIZE(u300_partitions),
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.options = NAND_SKIP_BBTSCAN,
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.width = FSMC_NAND_BW8,
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.ale_off = PLAT_NAND_ALE,
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.cle_off = PLAT_NAND_CLE,
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};
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static struct platform_device nand_device = {
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@ -876,8 +876,6 @@ static int __devinit fsmc_nand_probe_config_dt(struct platform_device *pdev,
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return -EINVAL;
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}
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}
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of_property_read_u32(np, "st,ale-off", &pdata->ale_off);
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of_property_read_u32(np, "st,cle-off", &pdata->cle_off);
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if (of_get_property(np, "nand-skip-bbtscan", NULL))
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pdata->options = NAND_SKIP_BBTSCAN;
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@ -935,41 +933,28 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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if (!res)
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return -EINVAL;
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if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
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pdev->name)) {
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dev_err(&pdev->dev, "Failed to get memory data resourse\n");
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return -ENOENT;
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}
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host->data_pa = (dma_addr_t)res->start;
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host->data_va = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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host->data_va = devm_request_and_ioremap(&pdev->dev, res);
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if (!host->data_va) {
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dev_err(&pdev->dev, "data ioremap failed\n");
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return -ENOMEM;
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}
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host->data_pa = (dma_addr_t)res->start;
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if (!devm_request_mem_region(&pdev->dev, res->start + pdata->ale_off,
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resource_size(res), pdev->name)) {
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dev_err(&pdev->dev, "Failed to get memory ale resourse\n");
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return -ENOENT;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
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if (!res)
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return -EINVAL;
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host->addr_va = devm_ioremap(&pdev->dev, res->start + pdata->ale_off,
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resource_size(res));
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host->addr_va = devm_request_and_ioremap(&pdev->dev, res);
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if (!host->addr_va) {
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dev_err(&pdev->dev, "ale ioremap failed\n");
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return -ENOMEM;
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}
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if (!devm_request_mem_region(&pdev->dev, res->start + pdata->cle_off,
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resource_size(res), pdev->name)) {
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dev_err(&pdev->dev, "Failed to get memory cle resourse\n");
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return -ENOENT;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
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if (!res)
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return -EINVAL;
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host->cmd_va = devm_ioremap(&pdev->dev, res->start + pdata->cle_off,
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resource_size(res));
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host->cmd_va = devm_request_and_ioremap(&pdev->dev, res);
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if (!host->cmd_va) {
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dev_err(&pdev->dev, "ale ioremap failed\n");
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return -ENOMEM;
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@ -979,14 +964,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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if (!res)
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return -EINVAL;
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if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
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pdev->name)) {
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dev_err(&pdev->dev, "Failed to get memory regs resourse\n");
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return -ENOENT;
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}
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host->regs_va = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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host->regs_va = devm_request_and_ioremap(&pdev->dev, res);
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if (!host->regs_va) {
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dev_err(&pdev->dev, "regs ioremap failed\n");
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return -ENOMEM;
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@ -155,9 +155,6 @@ struct fsmc_nand_platform_data {
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unsigned int width;
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unsigned int bank;
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/* CLE, ALE offsets */
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unsigned int cle_off;
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unsigned int ale_off;
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enum access_mode mode;
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void (*select_bank)(uint32_t bank, uint32_t busw);
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