ARM: tegra: Pass uncompress.h UART selection to DEBUG_LL
uncompress.h now saves the selected UART's physical address in Tegra's IRAM, along with a cookie to indicate validity. The first time it's run, macro addruart in debug-macro.S looks for this cookie, and if it's present, uses the UART address stored there. If not, the static value TEGRA_DEBUG_UART_BASE is used, as was previous behaviour. The static behaviour will thus be used when not booting using a zImage. This work was inspired by work by Doug Anderson <dianders@chromium.org>; see http://lkml.org/lkml/2011/9/26/284. However, this patch relies on the data passing describe above, rather than duplicating the UART selection logic in debug-macro.S; the latest selection logic is more complex due to the need to check reset/clock bits too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Doug Anderson <dianders@chromium.org> Acked-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Stephen Warren
Olof Johansson
Родитель
fe2639892c
Коммит
6d7d7b3ecd
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@ -33,6 +33,23 @@
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#include "clock.h"
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#include "fuse.h"
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/*
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* Storage for debug-macro.S's state.
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*
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* This must be in .data not .bss so that it gets initialized each time the
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* kernel is loaded. The data is declared here rather than debug-macro.S so
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* that multiple inclusions of debug-macro.S point at the same data.
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*/
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#define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
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u32 tegra_uart_config[3] = {
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/* Debug UART initialization required */
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1,
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/* Debug UART physical address */
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(u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
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/* Debug UART virtual address */
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(u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
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};
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#ifdef CONFIG_OF
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static const struct of_device_id tegra_dt_irq_match[] __initconst = {
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{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
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@ -1,11 +1,17 @@
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/*
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* arch/arm/mach-tegra/include/mach/debug-macro.S
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*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (C) 2010,2011 Google, Inc.
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* Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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* Erik Gilling <konkers@google.com>
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* Doug Anderson <dianders@chromium.org>
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* Stephen Warren <swarren@nvidia.com>
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*
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* Portions based on mach-omap2's debug-macro.S
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* Copyright (C) 1994-1999 Russell King
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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@ -18,18 +24,78 @@
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*
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*/
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#include <linux/serial_reg.h>
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#include <mach/io.h>
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#include <mach/iomap.h>
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#include <mach/irammap.h>
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.macro addruart, rp, rv, tmp
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ldr \rp, =IO_APB_PHYS @ physical
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ldr \rv, =IO_APB_VIRT @ virtual
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orr \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF)
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orr \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF00)
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orr \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF)
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orr \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF00)
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.endm
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.macro addruart, rp, rv, tmp
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adr \rp, 99f @ actual addr of 99f
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ldr \rv, [\rp] @ linked addr is stored there
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sub \rv, \rv, \rp @ offset between the two
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ldr \rp, [\rp, #4] @ linked tegra_uart_config
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sub \tmp, \rp, \rv @ actual tegra_uart_config
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ldr \rp, [\tmp] @ Load tegra_uart_config
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cmp \rp, #1 @ needs intitialization?
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bne 100f @ no; go load the addresses
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mov \rv, #0 @ yes; record init is done
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str \rv, [\tmp]
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mov \rp, #TEGRA_IRAM_BASE @ See if cookie is in IRAM
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ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET]
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movw \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE & 0xffff
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movt \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE >> 16
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cmp \rv, \rp @ Cookie present?
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bne 100f @ No, use default UART
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mov \rp, #TEGRA_IRAM_BASE @ Load UART address from IRAM
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ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET + 4]
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str \rv, [\tmp, #4] @ Store in tegra_uart_phys
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sub \rv, \rv, #IO_APB_PHYS @ Calculate virt address
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add \rv, \rv, #IO_APB_VIRT
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str \rv, [\tmp, #8] @ Store in tegra_uart_virt
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b 100f
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#define UART_SHIFT 2
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#include <asm/hardware/debug-8250.S>
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.align
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99: .word .
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.word tegra_uart_config
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.ltorg
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100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
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ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
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.endm
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#define UART_SHIFT 2
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/*
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* Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
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* check to make sure that we aren't in the CONFIG_TEGRA_DEBUG_UART_NONE case.
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* We use the fact that all 5 valid UART addresses all have something in the
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* 2nd-to-lowest byte.
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*/
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.macro senduart, rd, rx
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tst \rx, #0x0000ff00
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strneb \rd, [\rx, #UART_TX << UART_SHIFT]
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1001:
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.endm
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.macro busyuart, rd, rx
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tst \rx, #0x0000ff00
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beq 1002f
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1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
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and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
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teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
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bne 1001b
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1002:
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.endm
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.macro waituart, rd, rx
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#ifdef FLOW_CONTROL
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tst \rx, #0x0000ff00
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beq 1002f
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1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
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tst \rd, #UART_MSR_CTS
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beq 1001b
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1002:
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#endif
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.endm
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@ -0,0 +1,35 @@
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MACH_TEGRA_IRAMMAP_H
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#define __MACH_TEGRA_IRAMMAP_H
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#include <asm/sizes.h>
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/* The first 1K of IRAM is permanently reserved for the CPU reset handler */
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#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
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#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K
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/*
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* These locations are written to by uncompress.h, and read by debug-macro.S.
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* The first word holds the cookie value if the data is valid. The second
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* word holds the UART physical address.
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*/
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#define TEGRA_IRAM_DEBUG_UART_OFFSET SZ_1K
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#define TEGRA_IRAM_DEBUG_UART_SIZE 8
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#define TEGRA_IRAM_DEBUG_UART_COOKIE 0x55415254
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#endif
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (C) 2011 Google, Inc.
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* Copyright (C) 2011 NVIDIA CORPORATION. All Rights Reserved.
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* Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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@ -30,6 +30,7 @@
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#include <linux/serial_reg.h>
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#include <mach/iomap.h>
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#include <mach/irammap.h>
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#define DEBUG_UART_SHIFT 2
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@ -49,6 +50,17 @@ static inline void flush(void)
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{
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}
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static inline void save_uart_address(void)
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{
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u32 *buf = (u32 *)(TEGRA_IRAM_BASE + TEGRA_IRAM_DEBUG_UART_OFFSET);
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if (uart) {
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buf[0] = TEGRA_IRAM_DEBUG_UART_COOKIE;
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buf[1] = (u32)uart;
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} else
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buf[0] = 0;
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}
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/*
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* Setup before decompression. This is where we do UART selection for
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* earlyprintk and init the uart_base register.
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@ -125,6 +137,7 @@ static inline void arch_decomp_setup(void)
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}
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if (i == ARRAY_SIZE(uarts))
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uart = (volatile u8 *)TEGRA_DEBUG_UART_BASE;
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save_uart_address();
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if (uart == NULL)
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return;
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