ASoC: meson: add axg fifo base driver
Amlogic's axg SoCs have two types of fifos which are the memory interfaces of the audio subsystem. FRDDR provides the playback interface while TODDR provides the capture interface. The way these fifos operate is very similar. Only a few settings are specific to each. They implement the same pcm driver here and the specifics of each will be dealt with the related DAI driver. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jerome Brunet
Mark Brown
Родитель
e32d99af68
Коммит
6dc4fa179f
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@ -57,6 +57,7 @@ source "sound/soc/kirkwood/Kconfig"
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source "sound/soc/img/Kconfig"
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source "sound/soc/intel/Kconfig"
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source "sound/soc/mediatek/Kconfig"
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source "sound/soc/meson/Kconfig"
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source "sound/soc/mxs/Kconfig"
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source "sound/soc/pxa/Kconfig"
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source "sound/soc/qcom/Kconfig"
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@ -38,6 +38,7 @@ obj-$(CONFIG_SND_SOC) += jz4740/
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obj-$(CONFIG_SND_SOC) += img/
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obj-$(CONFIG_SND_SOC) += intel/
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obj-$(CONFIG_SND_SOC) += mediatek/
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obj-$(CONFIG_SND_SOC) += meson/
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obj-$(CONFIG_SND_SOC) += mxs/
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obj-$(CONFIG_SND_SOC) += nuc900/
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obj-$(CONFIG_SND_SOC) += omap/
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@ -0,0 +1,8 @@
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menu "ASoC support for Amlogic platforms"
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depends on ARCH_MESON || COMPILE_TEST
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config SND_MESON_AXG_FIFO
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tristate
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select REGMAP_MMIO
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endmenu
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@ -0,0 +1,5 @@
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# SPDX-License-Identifier: (GPL-2.0 OR MIT)
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snd-soc-meson-axg-fifo-objs := axg-fifo.o
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obj-$(CONFIG_SND_MESON_AXG_FIFO) += snd-soc-meson-axg-fifo.o
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@ -0,0 +1,341 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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//
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// Copyright (c) 2018 BayLibre, SAS.
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// Author: Jerome Brunet <jbrunet@baylibre.com>
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#include <linux/clk.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include "axg-fifo.h"
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/*
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* This file implements the platform operations common to the playback and
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* capture frontend DAI. The logic behind this two types of fifo is very
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* similar but some difference exist.
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* These differences the respective DAI drivers
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*/
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static struct snd_pcm_hardware axg_fifo_hw = {
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.info = (SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_BLOCK_TRANSFER |
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SNDRV_PCM_INFO_PAUSE),
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.formats = AXG_FIFO_FORMATS,
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.rate_min = 5512,
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.rate_max = 192000,
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.channels_min = 1,
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.channels_max = AXG_FIFO_CH_MAX,
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.period_bytes_min = AXG_FIFO_MIN_DEPTH,
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.period_bytes_max = UINT_MAX,
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.periods_min = 2,
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.periods_max = UINT_MAX,
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/* No real justification for this */
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.buffer_bytes_max = 1 * 1024 * 1024,
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};
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static struct snd_soc_dai *axg_fifo_dai(struct snd_pcm_substream *ss)
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{
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struct snd_soc_pcm_runtime *rtd = ss->private_data;
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return rtd->cpu_dai;
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}
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static struct axg_fifo *axg_fifo_data(struct snd_pcm_substream *ss)
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{
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struct snd_soc_dai *dai = axg_fifo_dai(ss);
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return snd_soc_dai_get_drvdata(dai);
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}
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static struct device *axg_fifo_dev(struct snd_pcm_substream *ss)
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{
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struct snd_soc_dai *dai = axg_fifo_dai(ss);
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return dai->dev;
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}
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static void __dma_enable(struct axg_fifo *fifo, bool enable)
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{
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regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN,
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enable ? CTRL0_DMA_EN : 0);
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}
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static int axg_fifo_pcm_trigger(struct snd_pcm_substream *ss, int cmd)
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{
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struct axg_fifo *fifo = axg_fifo_data(ss);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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__dma_enable(fifo, true);
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break;
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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case SNDRV_PCM_TRIGGER_STOP:
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__dma_enable(fifo, false);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_pcm_substream *ss)
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{
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struct axg_fifo *fifo = axg_fifo_data(ss);
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struct snd_pcm_runtime *runtime = ss->runtime;
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unsigned int addr;
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regmap_read(fifo->map, FIFO_STATUS2, &addr);
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return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr);
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}
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static int axg_fifo_pcm_hw_params(struct snd_pcm_substream *ss,
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struct snd_pcm_hw_params *params)
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{
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struct snd_pcm_runtime *runtime = ss->runtime;
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struct axg_fifo *fifo = axg_fifo_data(ss);
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dma_addr_t end_ptr;
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unsigned int burst_num;
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int ret;
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ret = snd_pcm_lib_malloc_pages(ss, params_buffer_bytes(params));
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if (ret < 0)
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return ret;
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/* Setup dma memory pointers */
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end_ptr = runtime->dma_addr + runtime->dma_bytes - AXG_FIFO_BURST;
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regmap_write(fifo->map, FIFO_START_ADDR, runtime->dma_addr);
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regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr);
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/* Setup interrupt periodicity */
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burst_num = params_period_bytes(params) / AXG_FIFO_BURST;
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regmap_write(fifo->map, FIFO_INT_ADDR, burst_num);
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/* Enable block count irq */
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regmap_update_bits(fifo->map, FIFO_CTRL0,
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CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT),
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CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT));
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return 0;
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}
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static int axg_fifo_pcm_hw_free(struct snd_pcm_substream *ss)
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{
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struct axg_fifo *fifo = axg_fifo_data(ss);
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/* Disable the block count irq */
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regmap_update_bits(fifo->map, FIFO_CTRL0,
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CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0);
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return snd_pcm_lib_free_pages(ss);
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}
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static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)
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{
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regmap_update_bits(fifo->map, FIFO_CTRL1,
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CTRL1_INT_CLR(FIFO_INT_MASK),
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CTRL1_INT_CLR(mask));
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/* Clear must also be cleared */
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regmap_update_bits(fifo->map, FIFO_CTRL1,
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CTRL1_INT_CLR(FIFO_INT_MASK),
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0);
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}
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static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id)
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{
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struct snd_pcm_substream *ss = dev_id;
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struct axg_fifo *fifo = axg_fifo_data(ss);
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unsigned int status;
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regmap_read(fifo->map, FIFO_STATUS1, &status);
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status = STATUS1_INT_STS(status) & FIFO_INT_MASK;
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if (status & FIFO_INT_COUNT_REPEAT)
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snd_pcm_period_elapsed(ss);
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else
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dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n",
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status);
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/* Ack irqs */
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axg_fifo_ack_irq(fifo, status);
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return !status ? IRQ_NONE : IRQ_HANDLED;
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}
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static int axg_fifo_pcm_open(struct snd_pcm_substream *ss)
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{
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struct axg_fifo *fifo = axg_fifo_data(ss);
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struct device *dev = axg_fifo_dev(ss);
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int ret;
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snd_soc_set_runtime_hwparams(ss, &axg_fifo_hw);
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/*
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* Make sure the buffer and period size are multiple of the FIFO
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* minimum depth size
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*/
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ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
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SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
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AXG_FIFO_MIN_DEPTH);
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if (ret)
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return ret;
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ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
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SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
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AXG_FIFO_MIN_DEPTH);
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if (ret)
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return ret;
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ret = request_irq(fifo->irq, axg_fifo_pcm_irq_block, 0,
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dev_name(dev), ss);
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/* Enable pclk to access registers and clock the fifo ip */
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ret = clk_prepare_enable(fifo->pclk);
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if (ret)
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return ret;
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/* Setup status2 so it reports the memory pointer */
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regmap_update_bits(fifo->map, FIFO_CTRL1,
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CTRL1_STATUS2_SEL_MASK,
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CTRL1_STATUS2_SEL(STATUS2_SEL_DDR_READ));
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/* Make sure the dma is initially disabled */
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__dma_enable(fifo, false);
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/* Disable irqs until params are ready */
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regmap_update_bits(fifo->map, FIFO_CTRL0,
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CTRL0_INT_EN(FIFO_INT_MASK), 0);
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/* Clear any pending interrupt */
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axg_fifo_ack_irq(fifo, FIFO_INT_MASK);
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/* Take memory arbitror out of reset */
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ret = reset_control_deassert(fifo->arb);
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if (ret)
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clk_disable_unprepare(fifo->pclk);
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return ret;
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}
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static int axg_fifo_pcm_close(struct snd_pcm_substream *ss)
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{
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struct axg_fifo *fifo = axg_fifo_data(ss);
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int ret;
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/* Put the memory arbitror back in reset */
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ret = reset_control_assert(fifo->arb);
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/* Disable fifo ip and register access */
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clk_disable_unprepare(fifo->pclk);
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/* remove IRQ */
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free_irq(fifo->irq, ss);
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return ret;
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}
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const struct snd_pcm_ops axg_fifo_pcm_ops = {
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.open = axg_fifo_pcm_open,
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.close = axg_fifo_pcm_close,
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.ioctl = snd_pcm_lib_ioctl,
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.hw_params = axg_fifo_pcm_hw_params,
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.hw_free = axg_fifo_pcm_hw_free,
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.pointer = axg_fifo_pcm_pointer,
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.trigger = axg_fifo_pcm_trigger,
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};
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EXPORT_SYMBOL_GPL(axg_fifo_pcm_ops);
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int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type)
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{
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struct snd_card *card = rtd->card->snd_card;
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size_t size = axg_fifo_hw.buffer_bytes_max;
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return snd_pcm_lib_preallocate_pages(rtd->pcm->streams[type].substream,
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SNDRV_DMA_TYPE_DEV, card->dev,
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size, size);
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}
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EXPORT_SYMBOL_GPL(axg_fifo_pcm_new);
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static const struct regmap_config axg_fifo_regmap_cfg = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = FIFO_STATUS2,
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};
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int axg_fifo_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct axg_fifo_match_data *data;
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struct axg_fifo *fifo;
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struct resource *res;
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void __iomem *regs;
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data = of_device_get_match_data(dev);
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if (!data) {
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dev_err(dev, "failed to match device\n");
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return -ENODEV;
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}
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fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
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if (!fifo)
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return -ENOMEM;
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platform_set_drvdata(pdev, fifo);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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fifo->map = devm_regmap_init_mmio(dev, regs, &axg_fifo_regmap_cfg);
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if (IS_ERR(fifo->map)) {
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dev_err(dev, "failed to init regmap: %ld\n",
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PTR_ERR(fifo->map));
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return PTR_ERR(fifo->map);
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}
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fifo->pclk = devm_clk_get(dev, NULL);
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if (IS_ERR(fifo->pclk)) {
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if (PTR_ERR(fifo->pclk) != -EPROBE_DEFER)
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dev_err(dev, "failed to get pclk: %ld\n",
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PTR_ERR(fifo->pclk));
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return PTR_ERR(fifo->pclk);
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}
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fifo->arb = devm_reset_control_get_exclusive(dev, NULL);
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if (IS_ERR(fifo->arb)) {
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if (PTR_ERR(fifo->arb) != -EPROBE_DEFER)
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dev_err(dev, "failed to get arb reset: %ld\n",
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PTR_ERR(fifo->arb));
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return PTR_ERR(fifo->arb);
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}
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fifo->irq = of_irq_get(dev->of_node, 0);
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if (fifo->irq <= 0) {
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dev_err(dev, "failed to get irq: %d\n", fifo->irq);
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return fifo->irq;
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}
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return devm_snd_soc_register_component(dev, data->component_drv,
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data->dai_drv, 1);
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}
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EXPORT_SYMBOL_GPL(axg_fifo_probe);
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MODULE_DESCRIPTION("Amlogic AXG fifo driver");
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MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,80 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (c) 2018 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef _MESON_AXG_FIFO_H
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#define _MESON_AXG_FIFO_H
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struct clk;
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struct platform_device;
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struct regmap;
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struct reset_control;
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struct snd_soc_component_driver;
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struct snd_soc_dai;
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struct snd_soc_dai_driver;
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struct snd_pcm_ops;
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struct snd_soc_pcm_runtime;
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#define AXG_FIFO_CH_MAX 128
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#define AXG_FIFO_RATES (SNDRV_PCM_RATE_5512 | \
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SNDRV_PCM_RATE_8000_192000)
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#define AXG_FIFO_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S20_LE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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#define AXG_FIFO_BURST 8
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#define AXG_FIFO_MIN_CNT 64
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#define AXG_FIFO_MIN_DEPTH (AXG_FIFO_BURST * AXG_FIFO_MIN_CNT)
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#define FIFO_INT_ADDR_FINISH BIT(0)
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#define FIFO_INT_ADDR_INT BIT(1)
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#define FIFO_INT_COUNT_REPEAT BIT(2)
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#define FIFO_INT_COUNT_ONCE BIT(3)
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#define FIFO_INT_FIFO_ZERO BIT(4)
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#define FIFO_INT_FIFO_DEPTH BIT(5)
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#define FIFO_INT_MASK GENMASK(7, 0)
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#define FIFO_CTRL0 0x00
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#define CTRL0_DMA_EN BIT(31)
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#define CTRL0_INT_EN(x) ((x) << 16)
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#define CTRL0_SEL_MASK GENMASK(2, 0)
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#define CTRL0_SEL_SHIFT 0
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#define FIFO_CTRL1 0x04
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#define CTRL1_INT_CLR(x) ((x) << 0)
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#define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8)
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#define CTRL1_STATUS2_SEL(x) ((x) << 8)
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#define STATUS2_SEL_DDR_READ 0
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#define CTRL1_THRESHOLD_MASK GENMASK(23, 16)
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#define CTRL1_THRESHOLD(x) ((x) << 16)
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#define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24)
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#define CTRL1_FRDDR_DEPTH(x) ((x) << 24)
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#define FIFO_START_ADDR 0x08
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#define FIFO_FINISH_ADDR 0x0c
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#define FIFO_INT_ADDR 0x10
|
||||
#define FIFO_STATUS1 0x14
|
||||
#define STATUS1_INT_STS(x) ((x) << 0)
|
||||
#define FIFO_STATUS2 0x18
|
||||
|
||||
struct axg_fifo {
|
||||
struct regmap *map;
|
||||
struct clk *pclk;
|
||||
struct reset_control *arb;
|
||||
int irq;
|
||||
};
|
||||
|
||||
struct axg_fifo_match_data {
|
||||
const struct snd_soc_component_driver *component_drv;
|
||||
struct snd_soc_dai_driver *dai_drv;
|
||||
};
|
||||
|
||||
extern const struct snd_pcm_ops axg_fifo_pcm_ops;
|
||||
|
||||
int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type);
|
||||
int axg_fifo_probe(struct platform_device *pdev);
|
||||
|
||||
#endif /* _MESON_AXG_FIFO_H */
|
||||
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