irqchip/stm32: Add multi-bank management
-Prepare to manage multi-bank of external interrupts (N banks of 32 inputs). -Prepare to manage registers offsets by compatible (registers offsets could be different follow per stm32 platform). Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Ludovic Barre
Marc Zyngier
Родитель
0e7d780721
Коммит
6dd64ee17e
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@ -14,27 +14,66 @@
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define EXTI_IMR 0x0
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#define EXTI_EMR 0x4
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#define EXTI_RTSR 0x8
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#define EXTI_FTSR 0xc
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#define EXTI_SWIER 0x10
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#define EXTI_PR 0x14
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#define IRQS_PER_BANK 32
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struct stm32_exti_bank {
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u32 imr_ofst;
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u32 emr_ofst;
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u32 rtsr_ofst;
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u32 ftsr_ofst;
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u32 swier_ofst;
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u32 pr_ofst;
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};
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static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
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.imr_ofst = 0x00,
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.emr_ofst = 0x04,
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.rtsr_ofst = 0x08,
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.ftsr_ofst = 0x0C,
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.swier_ofst = 0x10,
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.pr_ofst = 0x14,
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};
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static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
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&stm32f4xx_exti_b1,
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};
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static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
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{
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const struct stm32_exti_bank *stm32_bank = gc->private;
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return irq_reg_readl(gc, stm32_bank->pr_ofst);
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}
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static void stm32_exti_irq_ack(struct irq_chip_generic *gc, u32 mask)
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{
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const struct stm32_exti_bank *stm32_bank = gc->private;
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irq_reg_writel(gc, mask, stm32_bank->pr_ofst);
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}
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static void stm32_irq_handler(struct irq_desc *desc)
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{
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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struct irq_chip_generic *gc = domain->gc->gc[0];
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int virq, nbanks = domain->gc->num_chips;
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struct irq_chip_generic *gc;
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const struct stm32_exti_bank *stm32_bank;
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unsigned long pending;
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int n;
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int n, i, irq_base = 0;
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chained_irq_enter(chip, desc);
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while ((pending = irq_reg_readl(gc, EXTI_PR))) {
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for_each_set_bit(n, &pending, BITS_PER_LONG) {
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generic_handle_irq(irq_find_mapping(domain, n));
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irq_reg_writel(gc, BIT(n), EXTI_PR);
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for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
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gc = irq_get_domain_generic_chip(domain, irq_base);
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stm32_bank = gc->private;
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while ((pending = stm32_exti_pending(gc))) {
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for_each_set_bit(n, &pending, IRQS_PER_BANK) {
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virq = irq_find_mapping(domain, irq_base + n);
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generic_handle_irq(virq);
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stm32_exti_irq_ack(gc, BIT(n));
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}
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}
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}
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@ -44,13 +83,14 @@ static void stm32_irq_handler(struct irq_desc *desc)
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static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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int pin = data->hwirq;
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const struct stm32_exti_bank *stm32_bank = gc->private;
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int pin = data->hwirq % IRQS_PER_BANK;
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u32 rtsr, ftsr;
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irq_gc_lock(gc);
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rtsr = irq_reg_readl(gc, EXTI_RTSR);
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ftsr = irq_reg_readl(gc, EXTI_FTSR);
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rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
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ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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@ -70,8 +110,8 @@ static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
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return -EINVAL;
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}
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irq_reg_writel(gc, rtsr, EXTI_RTSR);
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irq_reg_writel(gc, ftsr, EXTI_FTSR);
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irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
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irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
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irq_gc_unlock(gc);
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@ -81,17 +121,18 @@ static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
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static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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int pin = data->hwirq;
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const struct stm32_exti_bank *stm32_bank = gc->private;
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int pin = data->hwirq % IRQS_PER_BANK;
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u32 emr;
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irq_gc_lock(gc);
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emr = irq_reg_readl(gc, EXTI_EMR);
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emr = irq_reg_readl(gc, stm32_bank->emr_ofst);
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if (on)
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emr |= BIT(pin);
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else
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emr &= ~BIT(pin);
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irq_reg_writel(gc, emr, EXTI_EMR);
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irq_reg_writel(gc, emr, stm32_bank->emr_ofst);
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irq_gc_unlock(gc);
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@ -101,11 +142,12 @@ static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
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static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_chip_generic *gc = d->gc->gc[0];
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struct irq_chip_generic *gc;
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struct irq_fwspec *fwspec = data;
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irq_hw_number_t hwirq;
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hwirq = fwspec->param[0];
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gc = irq_get_domain_generic_chip(d, hwirq);
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irq_map_generic_chip(d, virq, hwirq);
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irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
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@ -129,8 +171,9 @@ struct irq_domain_ops irq_exti_domain_ops = {
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.free = stm32_exti_free,
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};
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static int __init stm32_exti_init(struct device_node *node,
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struct device_node *parent)
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static int
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__init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
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int bank_nr, struct device_node *node)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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int nr_irqs, nr_exti, ret, i;
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@ -144,14 +187,7 @@ static int __init stm32_exti_init(struct device_node *node,
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return -ENOMEM;
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}
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/* Determine number of irqs supported */
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writel_relaxed(~0UL, base + EXTI_RTSR);
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nr_exti = fls(readl_relaxed(base + EXTI_RTSR));
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writel_relaxed(0, base + EXTI_RTSR);
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pr_info("%pOF: %d External IRQs detected\n", node, nr_exti);
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domain = irq_domain_add_linear(node, nr_exti,
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domain = irq_domain_add_linear(node, bank_nr * IRQS_PER_BANK,
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&irq_exti_domain_ops, NULL);
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if (!domain) {
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pr_err("%s: Could not register interrupt domain.\n",
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@ -160,7 +196,7 @@ static int __init stm32_exti_init(struct device_node *node,
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goto out_unmap;
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}
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ret = irq_alloc_domain_generic_chips(domain, nr_exti, 1, "exti",
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ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
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handle_edge_irq, clr, 0, 0);
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if (ret) {
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pr_err("%pOF: Could not allocate generic interrupt chip.\n",
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@ -168,18 +204,32 @@ static int __init stm32_exti_init(struct device_node *node,
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goto out_free_domain;
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}
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gc = domain->gc->gc[0];
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for (i = 0; i < bank_nr; i++) {
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const struct stm32_exti_bank *stm32_bank = stm32_exti_banks[i];
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u32 irqs_mask;
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gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
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gc->reg_base = base;
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gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
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gc->chip_types->chip.name = gc->chip_types[0].chip.name;
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gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit;
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gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
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gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
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gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
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gc->chip_types->regs.ack = EXTI_PR;
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gc->chip_types->regs.mask = EXTI_IMR;
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gc->chip_types->handler = handle_edge_irq;
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gc->chip_types->regs.ack = stm32_bank->pr_ofst;
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gc->chip_types->regs.mask = stm32_bank->imr_ofst;
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gc->private = (void *)stm32_bank;
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/* Determine number of irqs supported */
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writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
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irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
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nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst));
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writel_relaxed(0, base + stm32_bank->rtsr_ofst);
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pr_info("%s: bank%d, External IRQs available:%#x\n",
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node->full_name, i, irqs_mask);
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}
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nr_irqs = of_irq_count(node);
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for (i = 0; i < nr_irqs; i++) {
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@ -198,4 +248,11 @@ out_unmap:
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return ret;
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}
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IRQCHIP_DECLARE(stm32_exti, "st,stm32-exti", stm32_exti_init);
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static int __init stm32f4_exti_of_init(struct device_node *np,
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struct device_node *parent)
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{
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return stm32_exti_init(stm32f4xx_exti_banks,
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ARRAY_SIZE(stm32f4xx_exti_banks), np);
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}
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IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
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