Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/i915: i915 cannot provide switcher services. drm/radeon/kms: fix vram base calculation on rs780/rs880 drm/radeon/kms: fix formatting of vram and gtt info drm/radeon/kms: forbid big bo allocation (fdo 31708) v3 drm: Don't try and disable an encoder that was never enabled drm: Add missing drm_vblank_put() along queue vblank error path drm/i915/dp: Only apply the workaround if the select is still active drm/i915: Emit a request to clear a flushed and idle ring for unbusy bo drm/i915/lvds: Always restore panel-fitter when enabling the LVDS drm/i915/ringbuffer: Only print an error on the second attempt to reset head drm/i915: announce to userspace that the bsd ring is coherent agp/intel: Fix wrong kunmap in i830_cleanup() drm/i915: Factor in pixel-repeat in FDI M/N calculation drm/i915: Death to the unnecessary 64bit divide drm/i915: Clean conflicting modesetting registers upon init drm/i915: Apply a workaround for transitioning from DP on pipe B to HDMI. drm/i915: Always set the DP transcoder config to 8BPC.
This commit is contained in:
Linus Torvalds
Коммит
6dde39be39
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|
@ -812,8 +812,10 @@ static int intel_fake_agp_fetch_size(void)
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static void i830_cleanup(void)
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{
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kunmap(intel_private.i8xx_page);
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intel_private.i8xx_flush_page = NULL;
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if (intel_private.i8xx_flush_page) {
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kunmap(intel_private.i8xx_flush_page);
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intel_private.i8xx_flush_page = NULL;
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}
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__free_page(intel_private.i8xx_page);
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intel_private.i8xx_page = NULL;
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@ -241,7 +241,7 @@ void drm_helper_disable_unused_functions(struct drm_device *dev)
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}
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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if (!drm_helper_encoder_in_use(encoder)) {
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if (encoder->crtc && !drm_helper_encoder_in_use(encoder)) {
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drm_encoder_disable(encoder);
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/* disconnector encoder from any connector */
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encoder->crtc = NULL;
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@ -585,10 +585,13 @@ static int drm_queue_vblank_event(struct drm_device *dev, int pipe,
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struct timeval now;
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unsigned long flags;
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unsigned int seq;
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int ret;
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e = kzalloc(sizeof *e, GFP_KERNEL);
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if (e == NULL)
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return -ENOMEM;
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if (e == NULL) {
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ret = -ENOMEM;
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goto err_put;
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}
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e->pipe = pipe;
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e->base.pid = current->pid;
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@ -603,9 +606,8 @@ static int drm_queue_vblank_event(struct drm_device *dev, int pipe,
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spin_lock_irqsave(&dev->event_lock, flags);
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if (file_priv->event_space < sizeof e->event) {
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spin_unlock_irqrestore(&dev->event_lock, flags);
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kfree(e);
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return -ENOMEM;
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ret = -EBUSY;
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goto err_unlock;
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}
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file_priv->event_space -= sizeof e->event;
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@ -638,6 +640,13 @@ static int drm_queue_vblank_event(struct drm_device *dev, int pipe,
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spin_unlock_irqrestore(&dev->event_lock, flags);
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return 0;
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err_unlock:
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spin_unlock_irqrestore(&dev->event_lock, flags);
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kfree(e);
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err_put:
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drm_vblank_put(dev, e->pipe);
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return ret;
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}
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/**
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@ -767,6 +767,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
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case I915_PARAM_HAS_BLT:
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value = HAS_BLT(dev);
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break;
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case I915_PARAM_HAS_COHERENT_RINGS:
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value = 1;
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break;
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default:
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DRM_DEBUG_DRIVER("Unknown parameter %d\n",
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param->param);
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@ -4374,10 +4374,20 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
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* use this buffer rather sooner than later, so issuing the required
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* flush earlier is beneficial.
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*/
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if (obj->write_domain & I915_GEM_GPU_DOMAINS)
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if (obj->write_domain & I915_GEM_GPU_DOMAINS) {
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i915_gem_flush_ring(dev, file_priv,
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obj_priv->ring,
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0, obj->write_domain);
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} else if (obj_priv->ring->outstanding_lazy_request) {
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/* This ring is not being cleared by active usage,
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* so emit a request to do so.
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*/
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u32 seqno = i915_add_request(dev,
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NULL, NULL,
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obj_priv->ring);
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if (seqno == 0)
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ret = -ENOMEM;
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}
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/* Update the active list for the hardware's current position.
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* Otherwise this only updates on a delayed timer or when irqs
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@ -3033,6 +3033,7 @@
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#define TRANS_DP_10BPC (1<<9)
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#define TRANS_DP_6BPC (2<<9)
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#define TRANS_DP_12BPC (3<<9)
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#define TRANS_DP_BPC_MASK (3<<9)
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#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
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#define TRANS_DP_VSYNC_ACTIVE_LOW 0
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#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
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@ -190,37 +190,6 @@ out:
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kfree(output.pointer);
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}
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static int intel_dsm_switchto(enum vga_switcheroo_client_id id)
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{
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return 0;
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}
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static int intel_dsm_power_state(enum vga_switcheroo_client_id id,
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enum vga_switcheroo_state state)
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{
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return 0;
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}
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static int intel_dsm_init(void)
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{
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return 0;
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}
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static int intel_dsm_get_client_id(struct pci_dev *pdev)
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{
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if (intel_dsm_priv.dhandle == DEVICE_ACPI_HANDLE(&pdev->dev))
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return VGA_SWITCHEROO_IGD;
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else
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return VGA_SWITCHEROO_DIS;
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}
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static struct vga_switcheroo_handler intel_dsm_handler = {
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.switchto = intel_dsm_switchto,
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.power_state = intel_dsm_power_state,
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.init = intel_dsm_init,
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.get_client_id = intel_dsm_get_client_id,
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};
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static bool intel_dsm_pci_probe(struct pci_dev *pdev)
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{
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acpi_handle dhandle, intel_handle;
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@ -276,11 +245,8 @@ void intel_register_dsm_handler(void)
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{
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if (!intel_dsm_detect())
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return;
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vga_switcheroo_register_handler(&intel_dsm_handler);
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}
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void intel_unregister_dsm_handler(void)
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{
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vga_switcheroo_unregister_handler();
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}
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@ -2120,9 +2120,11 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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reg = TRANS_DP_CTL(pipe);
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temp = I915_READ(reg);
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temp &= ~(TRANS_DP_PORT_SEL_MASK |
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TRANS_DP_SYNC_MASK);
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TRANS_DP_SYNC_MASK |
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TRANS_DP_BPC_MASK);
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temp |= (TRANS_DP_OUTPUT_ENABLE |
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TRANS_DP_ENH_FRAMING);
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temp |= TRANS_DP_8BPC;
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if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
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temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
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@ -2712,27 +2714,19 @@ fdi_reduce_ratio(u32 *num, u32 *den)
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}
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}
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#define DATA_N 0x800000
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#define LINK_N 0x80000
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static void
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ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
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int link_clock, struct fdi_m_n *m_n)
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{
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u64 temp;
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m_n->tu = 64; /* default size */
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temp = (u64) DATA_N * pixel_clock;
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temp = div_u64(temp, link_clock);
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m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
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m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
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m_n->gmch_n = DATA_N;
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/* BUG_ON(pixel_clock > INT_MAX / 36); */
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m_n->gmch_m = bits_per_pixel * pixel_clock;
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m_n->gmch_n = link_clock * nlanes * 8;
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fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
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temp = (u64) LINK_N * pixel_clock;
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m_n->link_m = div_u64(temp, link_clock);
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m_n->link_n = LINK_N;
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m_n->link_m = pixel_clock;
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m_n->link_n = link_clock;
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fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
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}
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@ -3716,6 +3710,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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/* FDI link */
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if (HAS_PCH_SPLIT(dev)) {
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int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
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int lane = 0, link_bw, bpp;
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/* CPU eDP doesn't require FDI link, so just set DP M/N
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according to current link config */
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@ -3799,6 +3794,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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intel_crtc->fdi_lanes = lane;
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if (pixel_multiplier > 1)
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link_bw *= pixel_multiplier;
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ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
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}
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@ -5236,6 +5233,55 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
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.page_flip = intel_crtc_page_flip,
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};
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static void intel_sanitize_modesetting(struct drm_device *dev,
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int pipe, int plane)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 reg, val;
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if (HAS_PCH_SPLIT(dev))
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return;
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/* Who knows what state these registers were left in by the BIOS or
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* grub?
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*
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* If we leave the registers in a conflicting state (e.g. with the
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* display plane reading from the other pipe than the one we intend
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* to use) then when we attempt to teardown the active mode, we will
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* not disable the pipes and planes in the correct order -- leaving
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* a plane reading from a disabled pipe and possibly leading to
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* undefined behaviour.
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*/
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reg = DSPCNTR(plane);
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val = I915_READ(reg);
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if ((val & DISPLAY_PLANE_ENABLE) == 0)
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return;
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if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
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return;
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/* This display plane is active and attached to the other CPU pipe. */
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pipe = !pipe;
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/* Disable the plane and wait for it to stop reading from the pipe. */
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I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
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intel_flush_display_plane(dev, plane);
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if (IS_GEN2(dev))
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intel_wait_for_vblank(dev, pipe);
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|
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if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
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return;
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|
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/* Switch off the pipe. */
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reg = PIPECONF(pipe);
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val = I915_READ(reg);
|
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if (val & PIPECONF_ENABLE) {
|
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I915_WRITE(reg, val & ~PIPECONF_ENABLE);
|
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intel_wait_for_pipe_off(dev, pipe);
|
||||
}
|
||||
}
|
||||
|
||||
static void intel_crtc_init(struct drm_device *dev, int pipe)
|
||||
{
|
||||
|
|
@ -5287,6 +5333,8 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
|
|||
|
||||
setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
|
||||
(unsigned long)intel_crtc);
|
||||
|
||||
intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
|
||||
}
|
||||
|
||||
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
|
||||
|
|
|
|||
|
|
@ -1376,6 +1376,9 @@ intel_dp_link_down(struct intel_dp *intel_dp)
|
|||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
uint32_t DP = intel_dp->DP;
|
||||
|
||||
if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
|
||||
return;
|
||||
|
||||
DRM_DEBUG_KMS("\n");
|
||||
|
||||
if (is_edp(intel_dp)) {
|
||||
|
|
@ -1398,6 +1401,28 @@ intel_dp_link_down(struct intel_dp *intel_dp)
|
|||
|
||||
if (is_edp(intel_dp))
|
||||
DP |= DP_LINK_TRAIN_OFF;
|
||||
|
||||
if (!HAS_PCH_CPT(dev) &&
|
||||
I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
|
||||
/* Hardware workaround: leaving our transcoder select
|
||||
* set to transcoder B while it's off will prevent the
|
||||
* corresponding HDMI output on transcoder A.
|
||||
*
|
||||
* Combine this with another hardware workaround:
|
||||
* transcoder select bit can only be cleared while the
|
||||
* port is enabled.
|
||||
*/
|
||||
DP &= ~DP_PIPEB_SELECT;
|
||||
I915_WRITE(intel_dp->output_reg, DP);
|
||||
|
||||
/* Changes to enable or select take place the vblank
|
||||
* after being written.
|
||||
*/
|
||||
intel_wait_for_vblank(intel_dp->base.base.dev,
|
||||
intel_crtc->pipe);
|
||||
}
|
||||
|
||||
I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
|
||||
POSTING_READ(intel_dp->output_reg);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector)
|
|||
/**
|
||||
* Sets the power state for the panel.
|
||||
*/
|
||||
static void intel_lvds_set_power(struct intel_lvds *intel_lvds, bool on)
|
||||
static void intel_lvds_enable(struct intel_lvds *intel_lvds)
|
||||
{
|
||||
struct drm_device *dev = intel_lvds->base.base.dev;
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
|
@ -82,26 +82,61 @@ static void intel_lvds_set_power(struct intel_lvds *intel_lvds, bool on)
|
|||
lvds_reg = LVDS;
|
||||
}
|
||||
|
||||
if (on) {
|
||||
I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
|
||||
I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
|
||||
intel_panel_set_backlight(dev, dev_priv->backlight_level);
|
||||
} else {
|
||||
dev_priv->backlight_level = intel_panel_get_backlight(dev);
|
||||
I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
|
||||
|
||||
intel_panel_set_backlight(dev, 0);
|
||||
I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
|
||||
|
||||
if (intel_lvds->pfit_control) {
|
||||
if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000))
|
||||
DRM_ERROR("timed out waiting for panel to power off\n");
|
||||
I915_WRITE(PFIT_CONTROL, 0);
|
||||
intel_lvds->pfit_control = 0;
|
||||
if (intel_lvds->pfit_dirty) {
|
||||
/*
|
||||
* Enable automatic panel scaling so that non-native modes
|
||||
* fill the screen. The panel fitter should only be
|
||||
* adjusted whilst the pipe is disabled, according to
|
||||
* register description and PRM.
|
||||
*/
|
||||
DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
|
||||
intel_lvds->pfit_control,
|
||||
intel_lvds->pfit_pgm_ratios);
|
||||
if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) {
|
||||
DRM_ERROR("timed out waiting for panel to power off\n");
|
||||
} else {
|
||||
I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios);
|
||||
I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control);
|
||||
intel_lvds->pfit_dirty = false;
|
||||
}
|
||||
|
||||
I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
|
||||
}
|
||||
|
||||
I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
|
||||
POSTING_READ(lvds_reg);
|
||||
|
||||
intel_panel_set_backlight(dev, dev_priv->backlight_level);
|
||||
}
|
||||
|
||||
static void intel_lvds_disable(struct intel_lvds *intel_lvds)
|
||||
{
|
||||
struct drm_device *dev = intel_lvds->base.base.dev;
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
u32 ctl_reg, lvds_reg;
|
||||
|
||||
if (HAS_PCH_SPLIT(dev)) {
|
||||
ctl_reg = PCH_PP_CONTROL;
|
||||
lvds_reg = PCH_LVDS;
|
||||
} else {
|
||||
ctl_reg = PP_CONTROL;
|
||||
lvds_reg = LVDS;
|
||||
}
|
||||
|
||||
dev_priv->backlight_level = intel_panel_get_backlight(dev);
|
||||
intel_panel_set_backlight(dev, 0);
|
||||
|
||||
I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
|
||||
|
||||
if (intel_lvds->pfit_control) {
|
||||
if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000))
|
||||
DRM_ERROR("timed out waiting for panel to power off\n");
|
||||
|
||||
I915_WRITE(PFIT_CONTROL, 0);
|
||||
intel_lvds->pfit_dirty = true;
|
||||
}
|
||||
|
||||
I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
|
||||
POSTING_READ(lvds_reg);
|
||||
}
|
||||
|
||||
|
|
@ -110,9 +145,9 @@ static void intel_lvds_dpms(struct drm_encoder *encoder, int mode)
|
|||
struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
|
||||
|
||||
if (mode == DRM_MODE_DPMS_ON)
|
||||
intel_lvds_set_power(intel_lvds, true);
|
||||
intel_lvds_enable(intel_lvds);
|
||||
else
|
||||
intel_lvds_set_power(intel_lvds, false);
|
||||
intel_lvds_disable(intel_lvds);
|
||||
|
||||
/* XXX: We never power down the LVDS pairs. */
|
||||
}
|
||||
|
|
@ -411,43 +446,18 @@ static void intel_lvds_commit(struct drm_encoder *encoder)
|
|||
/* Always do a full power on as we do not know what state
|
||||
* we were left in.
|
||||
*/
|
||||
intel_lvds_set_power(intel_lvds, true);
|
||||
intel_lvds_enable(intel_lvds);
|
||||
}
|
||||
|
||||
static void intel_lvds_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
|
||||
|
||||
/*
|
||||
* The LVDS pin pair will already have been turned on in the
|
||||
* intel_crtc_mode_set since it has a large impact on the DPLL
|
||||
* settings.
|
||||
*/
|
||||
|
||||
if (HAS_PCH_SPLIT(dev))
|
||||
return;
|
||||
|
||||
if (!intel_lvds->pfit_dirty)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Enable automatic panel scaling so that non-native modes fill the
|
||||
* screen. Should be enabled before the pipe is enabled, according to
|
||||
* register description and PRM.
|
||||
*/
|
||||
DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
|
||||
intel_lvds->pfit_control,
|
||||
intel_lvds->pfit_pgm_ratios);
|
||||
if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000))
|
||||
DRM_ERROR("timed out waiting for panel to power off\n");
|
||||
|
||||
I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios);
|
||||
I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control);
|
||||
intel_lvds->pfit_dirty = false;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -156,23 +156,25 @@ static int init_ring_common(struct drm_device *dev,
|
|||
|
||||
/* G45 ring initialization fails to reset head to zero */
|
||||
if (head != 0) {
|
||||
DRM_ERROR("%s head not reset to zero "
|
||||
"ctl %08x head %08x tail %08x start %08x\n",
|
||||
ring->name,
|
||||
I915_READ_CTL(ring),
|
||||
I915_READ_HEAD(ring),
|
||||
I915_READ_TAIL(ring),
|
||||
I915_READ_START(ring));
|
||||
DRM_DEBUG_KMS("%s head not reset to zero "
|
||||
"ctl %08x head %08x tail %08x start %08x\n",
|
||||
ring->name,
|
||||
I915_READ_CTL(ring),
|
||||
I915_READ_HEAD(ring),
|
||||
I915_READ_TAIL(ring),
|
||||
I915_READ_START(ring));
|
||||
|
||||
I915_WRITE_HEAD(ring, 0);
|
||||
|
||||
DRM_ERROR("%s head forced to zero "
|
||||
"ctl %08x head %08x tail %08x start %08x\n",
|
||||
ring->name,
|
||||
I915_READ_CTL(ring),
|
||||
I915_READ_HEAD(ring),
|
||||
I915_READ_TAIL(ring),
|
||||
I915_READ_START(ring));
|
||||
if (I915_READ_HEAD(ring) & HEAD_ADDR) {
|
||||
DRM_ERROR("failed to set %s head to zero "
|
||||
"ctl %08x head %08x tail %08x start %08x\n",
|
||||
ring->name,
|
||||
I915_READ_CTL(ring),
|
||||
I915_READ_HEAD(ring),
|
||||
I915_READ_TAIL(ring),
|
||||
I915_READ_START(ring));
|
||||
}
|
||||
}
|
||||
|
||||
I915_WRITE_CTL(ring,
|
||||
|
|
|
|||
|
|
@ -1195,8 +1195,10 @@ void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
|
|||
mc->vram_end, mc->real_vram_size >> 20);
|
||||
} else {
|
||||
u64 base = 0;
|
||||
if (rdev->flags & RADEON_IS_IGP)
|
||||
base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
|
||||
if (rdev->flags & RADEON_IS_IGP) {
|
||||
base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
|
||||
base <<= 24;
|
||||
}
|
||||
radeon_vram_location(rdev, &rdev->mc, base);
|
||||
rdev->mc.gtt_base_align = 0;
|
||||
radeon_gtt_location(rdev, mc);
|
||||
|
|
|
|||
|
|
@ -286,7 +286,7 @@ void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64
|
|||
mc->mc_vram_size = mc->aper_size;
|
||||
}
|
||||
mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
|
||||
dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
|
||||
dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
|
||||
mc->mc_vram_size >> 20, mc->vram_start,
|
||||
mc->vram_end, mc->real_vram_size >> 20);
|
||||
}
|
||||
|
|
@ -323,7 +323,7 @@ void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
|
|||
mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
|
||||
}
|
||||
mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
|
||||
dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
|
||||
dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
|
||||
mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
|
|||
u32 c = 0;
|
||||
|
||||
rbo->placement.fpfn = 0;
|
||||
rbo->placement.lpfn = rbo->rdev->mc.active_vram_size >> PAGE_SHIFT;
|
||||
rbo->placement.lpfn = 0;
|
||||
rbo->placement.placement = rbo->placements;
|
||||
rbo->placement.busy_placement = rbo->placements;
|
||||
if (domain & RADEON_GEM_DOMAIN_VRAM)
|
||||
|
|
@ -91,7 +91,8 @@ int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
|
|||
{
|
||||
struct radeon_bo *bo;
|
||||
enum ttm_bo_type type;
|
||||
int page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
|
||||
unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
|
||||
unsigned long max_size = 0;
|
||||
int r;
|
||||
|
||||
if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
|
||||
|
|
@ -104,6 +105,14 @@ int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
|
|||
}
|
||||
*bo_ptr = NULL;
|
||||
|
||||
/* maximun bo size is the minimun btw visible vram and gtt size */
|
||||
max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
|
||||
if ((page_align << PAGE_SHIFT) >= max_size) {
|
||||
printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
|
||||
__func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
retry:
|
||||
bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
|
||||
if (bo == NULL)
|
||||
|
|
|
|||
|
|
@ -287,6 +287,8 @@ typedef struct drm_i915_irq_wait {
|
|||
#define I915_PARAM_HAS_EXECBUF2 9
|
||||
#define I915_PARAM_HAS_BSD 10
|
||||
#define I915_PARAM_HAS_BLT 11
|
||||
#define I915_PARAM_HAS_RELAXED_FENCING 12
|
||||
#define I915_PARAM_HAS_COHERENT_RINGS 13
|
||||
|
||||
typedef struct drm_i915_getparam {
|
||||
int param;
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче