drm/i915/guc: Provide mmio list to be saved/restored on engine reset
The driver must provide GuC with a list of mmio registers that should be saved/restored during a GuC-based engine reset. Unfortunately, the list must be dynamically allocated as its size is variable. That means the driver must generate the list twice - once to work out the size and a second time to actually save it. v2: (Alan / CI) - GEN7_GT_MODE -> GEN6_GT_MODE to fix WA selftest failure Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Signed-off-by: Fernando Pacheco <fernando.pacheco@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210727002348.97202-16-matthew.brost@intel.com
This commit is contained in:
John Harrison
Родитель
933864af11
Коммит
6de12da166
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@ -150,13 +150,14 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
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}
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static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
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u32 clear, u32 set, u32 read_mask)
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u32 clear, u32 set, u32 read_mask, bool masked_reg)
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{
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struct i915_wa wa = {
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.reg = reg,
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.clr = clear,
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.set = set,
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.read = read_mask,
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.masked_reg = masked_reg,
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};
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_wa_add(wal, &wa);
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@ -165,7 +166,7 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
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static void
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wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
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{
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wa_add(wal, reg, clear, set, clear);
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wa_add(wal, reg, clear, set, clear, false);
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}
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static void
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@ -200,20 +201,20 @@ wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
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static void
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wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
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{
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wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val);
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wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
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}
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static void
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wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
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{
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wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val);
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wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
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}
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static void
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wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
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u32 mask, u32 val)
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{
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wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask);
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wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
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}
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static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
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@ -533,10 +534,10 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
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wa_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
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/* WaEnableFloatBlendOptimization:icl */
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wa_write_clr_set(wal,
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GEN10_CACHE_MODE_SS,
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0, /* write-only, so skip validation */
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_MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
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wa_add(wal, GEN10_CACHE_MODE_SS, 0,
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_MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
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0 /* write-only, so skip validation */,
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true);
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/* WaDisableGPGPUMidThreadPreemption:icl */
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wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
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@ -581,7 +582,7 @@ static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
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FF_MODE2,
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FF_MODE2_TDS_TIMER_MASK,
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FF_MODE2_TDS_TIMER_128,
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0);
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0, false);
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}
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static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
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@ -619,7 +620,7 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
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FF_MODE2,
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FF_MODE2_GS_TIMER_MASK,
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FF_MODE2_GS_TIMER_224,
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0);
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0, false);
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/*
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* Wa_14012131227:dg1
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@ -795,7 +796,7 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
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wa_add(wal,
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HSW_ROW_CHICKEN3, 0,
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_MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
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0 /* XXX does this reg exist? */);
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0 /* XXX does this reg exist? */, true);
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/* WaVSRefCountFullforceMissDisable:hsw */
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wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
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@ -1824,10 +1825,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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* disable bit, which we don't touch here, but it's good
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* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
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*/
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wa_add(wal, GEN7_GT_MODE, 0,
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_MASKED_FIELD(GEN6_WIZ_HASHING_MASK,
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GEN6_WIZ_HASHING_16x4),
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GEN6_WIZ_HASHING_16x4);
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wa_masked_field_set(wal,
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GEN7_GT_MODE,
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GEN6_WIZ_HASHING_MASK,
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GEN6_WIZ_HASHING_16x4);
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}
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if (IS_GRAPHICS_VER(i915, 6, 7))
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@ -1877,10 +1878,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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* disable bit, which we don't touch here, but it's good
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* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
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*/
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wa_add(wal,
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GEN6_GT_MODE, 0,
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_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
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GEN6_WIZ_HASHING_16x4);
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wa_masked_field_set(wal,
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GEN6_GT_MODE,
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GEN6_WIZ_HASHING_MASK,
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GEN6_WIZ_HASHING_16x4);
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/* WaDisable_RenderCache_OperationalFlush:snb */
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wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
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@ -1901,7 +1902,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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wa_add(wal, MI_MODE,
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0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
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/* XXX bit doesn't stick on Broadwater */
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IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
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IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true);
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if (GRAPHICS_VER(i915) == 4)
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/*
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@ -1916,7 +1917,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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*/
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wa_add(wal, ECOSKPD,
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0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
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0 /* XXX bit doesn't stick on Broadwater */);
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0 /* XXX bit doesn't stick on Broadwater */,
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true);
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}
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static void
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@ -15,6 +15,7 @@ struct i915_wa {
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u32 clr;
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u32 set;
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u32 read;
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bool masked_reg;
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};
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struct i915_wa_list {
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@ -59,6 +59,7 @@ struct intel_guc {
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struct i915_vma *ads_vma;
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struct __guc_ads_blob *ads_blob;
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u32 ads_regset_size;
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struct i915_vma *lrc_desc_pool;
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void *lrc_desc_pool_vaddr;
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@ -3,6 +3,8 @@
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* Copyright © 2014-2019 Intel Corporation
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*/
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#include <linux/bsearch.h>
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#include "gt/intel_gt.h"
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#include "gt/intel_lrc.h"
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#include "intel_guc_ads.h"
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@ -23,7 +25,12 @@
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* | guc_policies |
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* +---------------------------------------+
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* | guc_gt_system_info |
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* +---------------------------------------+
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* +---------------------------------------+ <== static
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* | guc_mmio_reg[countA] (engine 0.0) |
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* | guc_mmio_reg[countB] (engine 0.1) |
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* | guc_mmio_reg[countC] (engine 1.0) |
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* | ... |
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* +---------------------------------------+ <== dynamic
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* | padding |
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* +---------------------------------------+ <== 4K aligned
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* | private data |
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@ -35,16 +42,33 @@ struct __guc_ads_blob {
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struct guc_ads ads;
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struct guc_policies policies;
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struct guc_gt_system_info system_info;
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/* From here on, location is dynamic! Refer to above diagram. */
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struct guc_mmio_reg regset[0];
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} __packed;
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static u32 guc_ads_regset_size(struct intel_guc *guc)
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{
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GEM_BUG_ON(!guc->ads_regset_size);
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return guc->ads_regset_size;
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}
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static u32 guc_ads_private_data_size(struct intel_guc *guc)
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{
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return PAGE_ALIGN(guc->fw.private_data_size);
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}
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static u32 guc_ads_regset_offset(struct intel_guc *guc)
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{
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return offsetof(struct __guc_ads_blob, regset);
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}
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static u32 guc_ads_private_data_offset(struct intel_guc *guc)
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{
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return PAGE_ALIGN(sizeof(struct __guc_ads_blob));
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u32 offset;
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offset = guc_ads_regset_offset(guc) +
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guc_ads_regset_size(guc);
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return PAGE_ALIGN(offset);
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}
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static u32 guc_ads_blob_size(struct intel_guc *guc)
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@ -83,6 +107,165 @@ static void guc_mapping_table_init(struct intel_gt *gt,
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}
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}
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/*
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* The save/restore register list must be pre-calculated to a temporary
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* buffer of driver defined size before it can be generated in place
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* inside the ADS.
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*/
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#define MAX_MMIO_REGS 128 /* Arbitrary size, increase as needed */
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struct temp_regset {
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struct guc_mmio_reg *registers;
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u32 used;
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u32 size;
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};
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static int guc_mmio_reg_cmp(const void *a, const void *b)
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{
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const struct guc_mmio_reg *ra = a;
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const struct guc_mmio_reg *rb = b;
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return (int)ra->offset - (int)rb->offset;
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}
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static void guc_mmio_reg_add(struct temp_regset *regset,
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u32 offset, u32 flags)
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{
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u32 count = regset->used;
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struct guc_mmio_reg reg = {
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.offset = offset,
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.flags = flags,
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};
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struct guc_mmio_reg *slot;
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GEM_BUG_ON(count >= regset->size);
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/*
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* The mmio list is built using separate lists within the driver.
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* It's possible that at some point we may attempt to add the same
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* register more than once. Do not consider this an error; silently
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* move on if the register is already in the list.
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*/
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if (bsearch(®, regset->registers, count,
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sizeof(reg), guc_mmio_reg_cmp))
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return;
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slot = ®set->registers[count];
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regset->used++;
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*slot = reg;
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while (slot-- > regset->registers) {
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GEM_BUG_ON(slot[0].offset == slot[1].offset);
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if (slot[1].offset > slot[0].offset)
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break;
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swap(slot[1], slot[0]);
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}
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}
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#define GUC_MMIO_REG_ADD(regset, reg, masked) \
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guc_mmio_reg_add(regset, \
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i915_mmio_reg_offset((reg)), \
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(masked) ? GUC_REGSET_MASKED : 0)
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static void guc_mmio_regset_init(struct temp_regset *regset,
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struct intel_engine_cs *engine)
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{
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const u32 base = engine->mmio_base;
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struct i915_wa_list *wal = &engine->wa_list;
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struct i915_wa *wa;
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unsigned int i;
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regset->used = 0;
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GUC_MMIO_REG_ADD(regset, RING_MODE_GEN7(base), true);
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GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false);
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GUC_MMIO_REG_ADD(regset, RING_IMR(base), false);
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for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
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GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg);
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/* Be extra paranoid and include all whitelist registers. */
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for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++)
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GUC_MMIO_REG_ADD(regset,
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RING_FORCE_TO_NONPRIV(base, i),
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false);
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/* add in local MOCS registers */
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for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++)
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GUC_MMIO_REG_ADD(regset, GEN9_LNCFCMOCS(i), false);
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}
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static int guc_mmio_reg_state_query(struct intel_guc *guc)
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{
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struct intel_gt *gt = guc_to_gt(guc);
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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struct temp_regset temp_set;
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u32 total;
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/*
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* Need to actually build the list in order to filter out
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* duplicates and other such data dependent constructions.
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*/
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temp_set.size = MAX_MMIO_REGS;
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temp_set.registers = kmalloc_array(temp_set.size,
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sizeof(*temp_set.registers),
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GFP_KERNEL);
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if (!temp_set.registers)
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return -ENOMEM;
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total = 0;
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for_each_engine(engine, gt, id) {
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guc_mmio_regset_init(&temp_set, engine);
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total += temp_set.used;
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}
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kfree(temp_set.registers);
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return total * sizeof(struct guc_mmio_reg);
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}
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static void guc_mmio_reg_state_init(struct intel_guc *guc,
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struct __guc_ads_blob *blob)
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{
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struct intel_gt *gt = guc_to_gt(guc);
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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struct temp_regset temp_set;
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struct guc_mmio_reg_set *ads_reg_set;
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u32 addr_ggtt, offset;
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u8 guc_class;
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offset = guc_ads_regset_offset(guc);
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addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
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temp_set.registers = (struct guc_mmio_reg *)(((u8 *)blob) + offset);
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temp_set.size = guc->ads_regset_size / sizeof(temp_set.registers[0]);
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for_each_engine(engine, gt, id) {
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/* Class index is checked in class converter */
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GEM_BUG_ON(engine->instance >= GUC_MAX_INSTANCES_PER_CLASS);
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guc_class = engine_class_to_guc_class(engine->class);
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ads_reg_set = &blob->ads.reg_state_list[guc_class][engine->instance];
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guc_mmio_regset_init(&temp_set, engine);
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if (!temp_set.used) {
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ads_reg_set->address = 0;
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ads_reg_set->count = 0;
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continue;
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}
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ads_reg_set->address = addr_ggtt;
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ads_reg_set->count = temp_set.used;
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temp_set.size -= temp_set.used;
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temp_set.registers += temp_set.used;
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addr_ggtt += temp_set.used * sizeof(struct guc_mmio_reg);
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}
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GEM_BUG_ON(temp_set.size);
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}
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/*
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* The first 80 dwords of the register state context, containing the
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* execlists and ppgtt registers.
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@ -121,8 +304,7 @@ static void __guc_ads_init(struct intel_guc *guc)
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*/
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blob->ads.golden_context_lrca[guc_class] = 0;
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blob->ads.eng_state_size[guc_class] =
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intel_engine_context_size(guc_to_gt(guc),
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engine_class) -
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intel_engine_context_size(gt, engine_class) -
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skipped_size;
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}
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@ -153,6 +335,9 @@ static void __guc_ads_init(struct intel_guc *guc)
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blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
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blob->ads.gt_system_info = base + ptr_offset(blob, system_info);
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/* MMIO save/restore list */
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guc_mmio_reg_state_init(guc, blob);
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/* Private Data */
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blob->ads.private_data = base + guc_ads_private_data_offset(guc);
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@ -173,6 +358,12 @@ int intel_guc_ads_create(struct intel_guc *guc)
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|||
|
||||
GEM_BUG_ON(guc->ads_vma);
|
||||
|
||||
/* Need to calculate the reg state size dynamically: */
|
||||
ret = guc_mmio_reg_state_query(guc);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
guc->ads_regset_size = ret;
|
||||
|
||||
size = guc_ads_blob_size(guc);
|
||||
|
||||
ret = intel_guc_allocate_and_map_vma(guc, size, &guc->ads_vma,
|
||||
|
|
|
|||
|
|
@ -12316,6 +12316,7 @@ enum skl_power_gate {
|
|||
|
||||
/* MOCS (Memory Object Control State) registers */
|
||||
#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
|
||||
#define GEN9_LNCFCMOCS_REG_COUNT 32
|
||||
|
||||
#define __GEN9_RCS0_MOCS0 0xc800
|
||||
#define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
|
||||
|
|
|
|||
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