[media] smiapp-pll: Try other pre-pll divisors
The smiapp pll calculator assumed that the minimum pre-pll divisor was perfect. That may not always be the case, so let's try the others, too. Typically there are just a few alternatives. Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Sakari Ailus
Mauro Carvalho Chehab
Родитель
c2ebca0032
Коммит
6de1b143a4
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@ -58,7 +58,7 @@ static int bounds_check(struct device *dev, uint32_t val,
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if (val >= min && val <= max)
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return 0;
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dev_warn(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max);
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dev_dbg(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max);
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return -EINVAL;
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}
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@ -87,14 +87,14 @@ static void print_pll(struct device *dev, struct smiapp_pll *pll)
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dev_dbg(dev, "vt_pix_clk_freq_hz \t%d\n", pll->vt_pix_clk_freq_hz);
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}
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int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits,
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struct smiapp_pll *pll)
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static int __smiapp_pll_calculate(struct device *dev,
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struct smiapp_pll_limits *limits,
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struct smiapp_pll *pll, uint32_t mul,
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uint32_t div, uint32_t lane_op_clock_ratio)
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{
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uint32_t sys_div;
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uint32_t best_pix_div = INT_MAX >> 1;
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uint32_t vt_op_binning_div;
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uint32_t lane_op_clock_ratio;
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uint32_t mul, div;
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uint32_t more_mul_min, more_mul_max;
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uint32_t more_mul_factor;
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uint32_t min_vt_div, max_vt_div, vt_div;
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@ -102,54 +102,6 @@ int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits,
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unsigned int i;
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int rval;
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if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
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lane_op_clock_ratio = pll->lanes;
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else
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lane_op_clock_ratio = 1;
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dev_dbg(dev, "lane_op_clock_ratio: %d\n", lane_op_clock_ratio);
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dev_dbg(dev, "binning: %dx%d\n", pll->binning_horizontal,
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pll->binning_vertical);
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/* CSI transfers 2 bits per clock per lane; thus times 2 */
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pll->pll_op_clk_freq_hz = pll->link_freq * 2
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* (pll->lanes / lane_op_clock_ratio);
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/* Figure out limits for pre-pll divider based on extclk */
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dev_dbg(dev, "min / max pre_pll_clk_div: %d / %d\n",
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limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
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limits->max_pre_pll_clk_div =
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min_t(uint16_t, limits->max_pre_pll_clk_div,
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clk_div_even(pll->ext_clk_freq_hz /
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limits->min_pll_ip_freq_hz));
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limits->min_pre_pll_clk_div =
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max_t(uint16_t, limits->min_pre_pll_clk_div,
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clk_div_even_up(
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DIV_ROUND_UP(pll->ext_clk_freq_hz,
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limits->max_pll_ip_freq_hz)));
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dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %d / %d\n",
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limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
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i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
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mul = div_u64(pll->pll_op_clk_freq_hz, i);
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div = pll->ext_clk_freq_hz / i;
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dev_dbg(dev, "mul %d / div %d\n", mul, div);
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limits->min_pre_pll_clk_div =
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max_t(uint16_t, limits->min_pre_pll_clk_div,
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clk_div_even_up(
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DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
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limits->max_pll_op_freq_hz)));
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dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %d / %d\n",
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limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
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if (limits->min_pre_pll_clk_div > limits->max_pre_pll_clk_div) {
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dev_err(dev, "unable to compute pre_pll divisor\n");
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return -EINVAL;
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}
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pll->pre_pll_clk_div = limits->min_pre_pll_clk_div;
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/*
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* Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
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* too high.
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@ -193,8 +145,8 @@ int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits,
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more_mul_min);
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if (more_mul_min > more_mul_max) {
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dev_warn(dev,
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"unable to compute more_mul_min and more_mul_max\n");
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dev_dbg(dev,
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"unable to compute more_mul_min and more_mul_max\n");
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return -EINVAL;
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}
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@ -209,7 +161,7 @@ int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits,
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dev_dbg(dev, "final more_mul: %d\n", i);
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if (i > more_mul_max) {
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dev_warn(dev, "final more_mul is bad, max %d\n", more_mul_max);
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dev_dbg(dev, "final more_mul is bad, max %d\n", more_mul_max);
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return -EINVAL;
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}
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@ -354,8 +306,6 @@ int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits,
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pll->pixel_rate_csi =
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pll->op_pix_clk_freq_hz * lane_op_clock_ratio;
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print_pll(dev, pll);
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rval = bounds_check(dev, pll->pre_pll_clk_div,
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limits->min_pre_pll_clk_div,
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limits->max_pre_pll_clk_div, "pre_pll_clk_div");
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@ -411,6 +361,71 @@ int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits,
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return rval;
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}
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int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits,
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struct smiapp_pll *pll)
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{
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uint32_t lane_op_clock_ratio;
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uint32_t mul, div;
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unsigned int i;
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int rval = -EINVAL;
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if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
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lane_op_clock_ratio = pll->lanes;
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else
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lane_op_clock_ratio = 1;
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dev_dbg(dev, "lane_op_clock_ratio: %d\n", lane_op_clock_ratio);
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dev_dbg(dev, "binning: %dx%d\n", pll->binning_horizontal,
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pll->binning_vertical);
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/* CSI transfers 2 bits per clock per lane; thus times 2 */
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pll->pll_op_clk_freq_hz = pll->link_freq * 2
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* (pll->lanes / lane_op_clock_ratio);
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/* Figure out limits for pre-pll divider based on extclk */
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dev_dbg(dev, "min / max pre_pll_clk_div: %d / %d\n",
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limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
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limits->max_pre_pll_clk_div =
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min_t(uint16_t, limits->max_pre_pll_clk_div,
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clk_div_even(pll->ext_clk_freq_hz /
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limits->min_pll_ip_freq_hz));
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limits->min_pre_pll_clk_div =
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max_t(uint16_t, limits->min_pre_pll_clk_div,
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clk_div_even_up(
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DIV_ROUND_UP(pll->ext_clk_freq_hz,
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limits->max_pll_ip_freq_hz)));
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dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %d / %d\n",
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limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
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i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
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mul = div_u64(pll->pll_op_clk_freq_hz, i);
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div = pll->ext_clk_freq_hz / i;
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dev_dbg(dev, "mul %d / div %d\n", mul, div);
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limits->min_pre_pll_clk_div =
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max_t(uint16_t, limits->min_pre_pll_clk_div,
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clk_div_even_up(
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DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
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limits->max_pll_op_freq_hz)));
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dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %d / %d\n",
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limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
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for (pll->pre_pll_clk_div = limits->min_pre_pll_clk_div;
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pll->pre_pll_clk_div <= limits->max_pre_pll_clk_div;
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pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) {
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rval = __smiapp_pll_calculate(dev, limits, pll, mul, div,
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lane_op_clock_ratio);
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if (rval)
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continue;
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print_pll(dev, pll);
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return 0;
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}
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dev_info(dev, "unable to compute pre_pll divisor\n");
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return rval;
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}
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EXPORT_SYMBOL_GPL(smiapp_pll_calculate);
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MODULE_AUTHOR("Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>");
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