arm64: Remove Spectre-related CONFIG_* options
The spectre mitigations are too configurable for their own good, leading to confusing logic trying to figure out when we should mitigate and when we shouldn't. Although the plethora of command-line options need to stick around for backwards compatibility, the default-on CONFIG options that depend on EXPERT can be dropped, as the mitigations only do anything if the system is vulnerable, a mitigation is available and the command-line hasn't disabled it. Remove CONFIG_HARDEN_BRANCH_PREDICTOR and CONFIG_ARM64_SSBD in favour of enabling this code unconditionally. Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Will Deacon
Родитель
39533e1206
Коммит
6e5f092784
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@ -1165,32 +1165,6 @@ config UNMAP_KERNEL_AT_EL0
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If unsure, say Y.
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config HARDEN_BRANCH_PREDICTOR
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bool "Harden the branch predictor against aliasing attacks" if EXPERT
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default y
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help
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Speculation attacks against some high-performance processors rely on
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being able to manipulate the branch predictor for a victim context by
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executing aliasing branches in the attacker context. Such attacks
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can be partially mitigated against by clearing internal branch
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predictor state and limiting the prediction logic in some situations.
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This config option will take CPU-specific actions to harden the
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branch predictor against aliasing attacks and may rely on specific
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instruction sequences or control bits being set by the system
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firmware.
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If unsure, say Y.
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config ARM64_SSBD
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bool "Speculative Store Bypass Disable" if EXPERT
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default y
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help
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This enables mitigation of the bypassing of previous stores
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by speculative loads.
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If unsure, say Y.
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config RODATA_FULL_DEFAULT_ENABLED
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bool "Apply r/o permissions of VM areas also to their linear aliases"
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default y
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@ -712,12 +712,8 @@ int get_spectre_v2_workaround_state(void);
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static inline int arm64_get_ssbd_state(void)
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{
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#ifdef CONFIG_ARM64_SSBD
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extern int ssbd_state;
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return ssbd_state;
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#else
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return ARM64_SSBD_UNKNOWN;
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#endif
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}
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void arm64_set_ssbd_mitigation(bool state);
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@ -527,7 +527,6 @@ static inline int kvm_map_vectors(void)
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}
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#endif
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#ifdef CONFIG_ARM64_SSBD
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DECLARE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
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static inline int hyp_map_aux_data(void)
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@ -544,12 +543,6 @@ static inline int hyp_map_aux_data(void)
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}
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return 0;
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}
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#else
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static inline int hyp_map_aux_data(void)
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{
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return 0;
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}
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#endif
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#define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr)
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@ -45,7 +45,6 @@ struct bp_hardening_data {
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bp_hardening_cb_t fn;
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};
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
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static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void)
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@ -64,14 +63,6 @@ static inline void arm64_apply_bp_hardening(void)
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if (d->fn)
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d->fn();
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}
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#else
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static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void)
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{
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return NULL;
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}
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static inline void arm64_apply_bp_hardening(void) { }
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#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
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extern void arm64_memblock_init(void);
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extern void paging_init(void);
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@ -19,7 +19,7 @@ obj-y := debug-monitors.o entry.o irq.o fpsimd.o \
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return_address.o cpuinfo.o cpu_errata.o \
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cpufeature.o alternative.o cacheinfo.o \
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smp.o smp_spin_table.o topology.o smccc-call.o \
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syscall.o
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ssbd.o syscall.o
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targets += efi-entry.o
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@ -59,7 +59,6 @@ arm64-reloc-test-y := reloc_test_core.o reloc_test_syms.o
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obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
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obj-$(CONFIG_CRASH_CORE) += crash_core.o
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obj-$(CONFIG_ARM_SDE_INTERFACE) += sdei.o
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obj-$(CONFIG_ARM64_SSBD) += ssbd.o
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obj-$(CONFIG_ARM64_PTR_AUTH) += pointer_auth.o
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obj-$(CONFIG_SHADOW_CALL_STACK) += scs.o
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@ -254,9 +254,7 @@ static int detect_harden_bp_fw(void)
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((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
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cb = qcom_link_stack_sanitization;
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if (IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR))
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install_bp_hardening_cb(cb, smccc_start, smccc_end);
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install_bp_hardening_cb(cb, smccc_start, smccc_end);
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return 1;
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}
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@ -335,11 +333,6 @@ void arm64_set_ssbd_mitigation(bool state)
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{
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int conduit;
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if (!IS_ENABLED(CONFIG_ARM64_SSBD)) {
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pr_info_once("SSBD disabled by kernel configuration\n");
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return;
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}
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if (this_cpu_has_cap(ARM64_SSBS)) {
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if (state)
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asm volatile(SET_PSTATE_SSBS(0));
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@ -584,12 +577,6 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope)
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__spectrev2_safe = false;
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if (!IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) {
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pr_warn_once("spectrev2 mitigation disabled by kernel configuration\n");
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__hardenbp_enab = false;
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return false;
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}
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/* forced off */
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if (__nospectre_v2 || cpu_mitigations_off()) {
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pr_info_once("spectrev2 mitigation disabled by command line option\n");
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@ -1004,9 +991,7 @@ ssize_t cpu_show_spec_store_bypass(struct device *dev,
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switch (ssbd_state) {
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case ARM64_SSBD_KERNEL:
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case ARM64_SSBD_FORCE_ENABLE:
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if (IS_ENABLED(CONFIG_ARM64_SSBD))
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return sprintf(buf,
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"Mitigation: Speculative Store Bypass disabled via prctl\n");
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return sprintf(buf, "Mitigation: Speculative Store Bypass disabled via prctl\n");
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}
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return sprintf(buf, "Vulnerable\n");
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@ -1583,7 +1583,6 @@ static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
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WARN_ON(val & (7 << 27 | 7 << 21));
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}
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#ifdef CONFIG_ARM64_SSBD
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static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
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{
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if (user_mode(regs))
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@ -1623,7 +1622,6 @@ static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
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arm64_set_ssbd_mitigation(true);
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}
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}
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#endif /* CONFIG_ARM64_SSBD */
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#ifdef CONFIG_ARM64_PAN
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static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
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@ -1976,7 +1974,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.field_pos = ID_AA64ISAR0_CRC32_SHIFT,
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.min_field_value = 1,
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},
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#ifdef CONFIG_ARM64_SSBD
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{
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.desc = "Speculative Store Bypassing Safe (SSBS)",
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.capability = ARM64_SSBS,
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@ -1988,7 +1985,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
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.cpu_enable = cpu_enable_ssbs,
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},
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#endif
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#ifdef CONFIG_ARM64_CNP
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{
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.desc = "Common not Private translations",
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@ -132,7 +132,6 @@ alternative_else_nop_endif
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* them if required.
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*/
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.macro apply_ssbd, state, tmp1, tmp2
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#ifdef CONFIG_ARM64_SSBD
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alternative_cb arm64_enable_wa2_handling
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b .L__asm_ssbd_skip\@
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alternative_cb_end
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@ -146,7 +145,6 @@ alternative_cb arm64_update_smccc_conduit
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nop // Patched to SMC/HVC #0
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alternative_cb_end
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.L__asm_ssbd_skip\@:
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#endif
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.endm
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.macro kernel_entry, el, regsize = 64
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@ -697,11 +695,9 @@ el0_irq_naked:
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bl trace_hardirqs_off
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#endif
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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tbz x22, #55, 1f
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bl do_el0_irq_bp_hardening
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1:
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#endif
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irq_handler
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#ifdef CONFIG_TRACE_IRQFLAGS
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@ -58,7 +58,7 @@ config KVM_ARM_PMU
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virtual machines.
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config KVM_INDIRECT_VECTORS
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def_bool HARDEN_BRANCH_PREDICTOR || RANDOMIZE_BASE
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def_bool RANDOMIZE_BASE
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endif # KVM
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@ -116,7 +116,6 @@ el1_hvc_guest:
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ARM_SMCCC_ARCH_WORKAROUND_2)
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cbnz w1, el1_trap
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#ifdef CONFIG_ARM64_SSBD
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alternative_cb arm64_enable_wa2_handling
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b wa2_end
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alternative_cb_end
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@ -143,7 +142,6 @@ alternative_cb_end
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wa2_end:
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mov x2, xzr
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mov x1, xzr
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#endif
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wa_epilogue:
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mov x0, xzr
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@ -489,7 +489,6 @@ static inline bool __needs_ssbd_off(struct kvm_vcpu *vcpu)
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static inline void __set_guest_arch_workaround_state(struct kvm_vcpu *vcpu)
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{
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#ifdef CONFIG_ARM64_SSBD
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/*
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* The host runs with the workaround always present. If the
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* guest wants it disabled, so be it...
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@ -497,19 +496,16 @@ static inline void __set_guest_arch_workaround_state(struct kvm_vcpu *vcpu)
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if (__needs_ssbd_off(vcpu) &&
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__hyp_this_cpu_read(arm64_ssbd_callback_required))
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 0, NULL);
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#endif
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}
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static inline void __set_host_arch_workaround_state(struct kvm_vcpu *vcpu)
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{
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#ifdef CONFIG_ARM64_SSBD
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/*
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* If the guest has disabled the workaround, bring it back on.
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*/
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if (__needs_ssbd_off(vcpu) &&
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__hyp_this_cpu_read(arm64_ssbd_callback_required))
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 1, NULL);
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#endif
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}
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static inline void __kvm_unexpected_el2_exception(void)
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