Revert "parisc: Use ldcw instruction for SMP spinlock release barrier"
This reverts commit 9e5c602186.
No need to use the ldcw instruction as SMP spinlock release barrier.
Revert it to gain back speed again.
Signed-off-by: Helge Deller <deller@gmx.de>
Cc: <stable@vger.kernel.org> # v5.2+
This commit is contained in:
Helge Deller
Родитель
462fb756c7
Коммит
6e9f06ee6c
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@ -37,11 +37,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *x)
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volatile unsigned int *a;
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a = __ldcw_align(x);
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#ifdef CONFIG_SMP
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(void) __ldcw(a);
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#else
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mb();
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#endif
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*a = 1;
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}
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@ -454,9 +454,8 @@
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nop
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LDREG 0(\ptp),\pte
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bb,<,n \pte,_PAGE_PRESENT_BIT,3f
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LDCW 0(\tmp),\tmp1
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b \fault
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stw \spc,0(\tmp)
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stw,ma \spc,0(\tmp)
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99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
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#endif
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2: LDREG 0(\ptp),\pte
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@ -465,22 +464,20 @@
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.endm
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/* Release pa_tlb_lock lock without reloading lock address. */
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.macro tlb_unlock0 spc,tmp,tmp1
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.macro tlb_unlock0 spc,tmp
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#ifdef CONFIG_SMP
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98: or,COND(=) %r0,\spc,%r0
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LDCW 0(\tmp),\tmp1
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or,COND(=) %r0,\spc,%r0
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stw \spc,0(\tmp)
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stw,ma \spc,0(\tmp)
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99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
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#endif
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.endm
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/* Release pa_tlb_lock lock. */
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.macro tlb_unlock1 spc,tmp,tmp1
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.macro tlb_unlock1 spc,tmp
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#ifdef CONFIG_SMP
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98: load_pa_tlb_lock \tmp
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99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
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tlb_unlock0 \spc,\tmp,\tmp1
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tlb_unlock0 \spc,\tmp
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#endif
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.endm
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@ -1163,7 +1160,7 @@ dtlb_miss_20w:
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idtlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1189,7 +1186,7 @@ nadtlb_miss_20w:
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idtlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1223,7 +1220,7 @@ dtlb_miss_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1256,7 +1253,7 @@ nadtlb_miss_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1285,7 +1282,7 @@ dtlb_miss_20:
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idtlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1313,7 +1310,7 @@ nadtlb_miss_20:
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idtlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1420,7 +1417,7 @@ itlb_miss_20w:
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iitlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1444,7 +1441,7 @@ naitlb_miss_20w:
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iitlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1478,7 +1475,7 @@ itlb_miss_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1502,7 +1499,7 @@ naitlb_miss_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1532,7 +1529,7 @@ itlb_miss_20:
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iitlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1552,7 +1549,7 @@ naitlb_miss_20:
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iitlbt pte,prot
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tlb_unlock1 spc,t0,t1
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tlb_unlock1 spc,t0
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rfir
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nop
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@ -1582,7 +1579,7 @@ dbit_trap_20w:
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idtlbt pte,prot
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tlb_unlock0 spc,t0,t1
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tlb_unlock0 spc,t0
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rfir
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nop
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#else
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@ -1608,7 +1605,7 @@ dbit_trap_11:
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mtsp t1, %sr1 /* Restore sr1 */
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tlb_unlock0 spc,t0,t1
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tlb_unlock0 spc,t0
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rfir
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nop
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@ -1628,7 +1625,7 @@ dbit_trap_20:
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idtlbt pte,prot
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tlb_unlock0 spc,t0,t1
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tlb_unlock0 spc,t0
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rfir
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nop
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#endif
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@ -640,9 +640,7 @@ cas_action:
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sub,<> %r28, %r25, %r0
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2: stw %r24, 0(%r26)
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/* Free lock */
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#ifdef CONFIG_SMP
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LDCW 0(%sr2,%r20), %r1 /* Barrier */
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#endif
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sync
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stw %r20, 0(%sr2,%r20)
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#if ENABLE_LWS_DEBUG
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/* Clear thread register indicator */
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@ -657,9 +655,7 @@ cas_action:
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3:
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/* Error occurred on load or store */
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/* Free lock */
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#ifdef CONFIG_SMP
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LDCW 0(%sr2,%r20), %r1 /* Barrier */
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#endif
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sync
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stw %r20, 0(%sr2,%r20)
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#if ENABLE_LWS_DEBUG
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stw %r0, 4(%sr2,%r20)
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@ -861,9 +857,7 @@ cas2_action:
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cas2_end:
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/* Free lock */
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#ifdef CONFIG_SMP
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LDCW 0(%sr2,%r20), %r1 /* Barrier */
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#endif
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sync
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stw %r20, 0(%sr2,%r20)
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/* Enable interrupts */
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ssm PSW_SM_I, %r0
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@ -874,9 +868,7 @@ cas2_end:
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22:
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/* Error occurred on load or store */
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/* Free lock */
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#ifdef CONFIG_SMP
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LDCW 0(%sr2,%r20), %r1 /* Barrier */
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#endif
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sync
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stw %r20, 0(%sr2,%r20)
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ssm PSW_SM_I, %r0
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ldo 1(%r0),%r28
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