From 97ad20758159b129e5462842688642518e4e82bb Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 19 Dec 2013 04:00:15 +0900 Subject: [PATCH 01/13] ARM: EXYNOS: cleanup Remove useless definitions in the regs-pmu.h file. Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/include/mach/regs-pmu.h | 51 -------------------- 1 file changed, 51 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index 2cdb63e8ce5c..2c15a8fbcb5a 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -24,11 +24,7 @@ #define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208) #define S5P_USE_STANDBY_WFI0 (1 << 16) -#define S5P_USE_STANDBY_WFI1 (1 << 17) -#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18) #define S5P_USE_STANDBY_WFE0 (1 << 24) -#define S5P_USE_STANDBY_WFE1 (1 << 25) -#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26) #define S5P_SWRESET S5P_PMUREG(0x0400) #define EXYNOS_SWRESET S5P_PMUREG(0x0400) @@ -38,17 +34,8 @@ #define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) #define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) -#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700) -#define S5P_HDMI_PHY_ENABLE (1 << 0) - -#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C) -#define S5P_DAC_PHY_ENABLE (1 << 0) - #define S5P_INFORM0 S5P_PMUREG(0x0800) #define S5P_INFORM1 S5P_PMUREG(0x0804) -#define S5P_INFORM2 S5P_PMUREG(0x0808) -#define S5P_INFORM3 S5P_PMUREG(0x080C) -#define S5P_INFORM4 S5P_PMUREG(0x0810) #define S5P_INFORM5 S5P_PMUREG(0x0814) #define S5P_INFORM6 S5P_PMUREG(0x0818) #define S5P_INFORM7 S5P_PMUREG(0x081C) @@ -119,23 +106,8 @@ #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) -#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) -#define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008) #define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) #define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084) -#define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088) - -#define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408) -#define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48) -#define S5P_CAM_OPTION S5P_PMUREG(0x3C08) -#define S5P_TV_OPTION S5P_PMUREG(0x3C28) -#define S5P_MFC_OPTION S5P_PMUREG(0x3C48) -#define S5P_G3D_OPTION S5P_PMUREG(0x3C68) -#define S5P_LCD0_OPTION S5P_PMUREG(0x3C88) -#define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8) -#define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8) -#define S5P_GPS_OPTION S5P_PMUREG(0x3CE8) -#define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08) #define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) #define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108) @@ -145,28 +117,12 @@ #define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188) #define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) -#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) -#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) -#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) -#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) -#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) -#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) - -#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 #define S5P_CORE_LOCAL_PWR_EN 0x3 #define S5P_INT_LOCAL_PWR_EN 0x7 #define S5P_CHECK_SLEEP 0x00000BAD /* Only for EXYNOS4210 */ -#define S5P_USBDEVICE_PHY_CONTROL S5P_PMUREG(0x0704) -#define S5P_USBDEVICE_PHY_ENABLE (1 << 0) - -#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708) -#define S5P_USBHOST_PHY_ENABLE (1 << 0) - -#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720) - #define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) #define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) #define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) @@ -174,8 +130,6 @@ #define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) #define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) -#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) - /* Only for EXYNOS4x12 */ #define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) @@ -343,13 +297,9 @@ #define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48) #define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8) #define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48) -#define EXYNOS5_GSCL_STATUS S5P_PMUREG(0x4004) -#define EXYNOS5_ISP_STATUS S5P_PMUREG(0x4024) #define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008) #define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028) #define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048) -#define EXYNOS5_G3D_CONFIGURATION S5P_PMUREG(0x4060) -#define EXYNOS5_G3D_STATUS S5P_PMUREG(0x4064) #define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068) #define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8) #define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8) @@ -357,7 +307,6 @@ #define EXYNOS5_USE_SC_FEEDBACK (1 << 1) #define EXYNOS5_USE_SC_COUNTER (1 << 0) -#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL (1 << 2) #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) #define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24) From e44de221d3ddb99387b04cfd49483bcd05daa6fb Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 19 Dec 2013 04:01:24 +0900 Subject: [PATCH 02/13] ARM: EXYNOS: remove inclusion into another headers This is needed to remove dependency of headers. Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/include/mach/pm-core.h | 5 ++++- arch/arm/mach-exynos/include/mach/regs-clock.h | 2 -- arch/arm/mach-exynos/pmu.c | 1 + arch/arm/mach-exynos/{include/mach => }/regs-pmu.h | 2 -- 4 files changed, 5 insertions(+), 5 deletions(-) rename arch/arm/mach-exynos/{include/mach => }/regs-pmu.h (99%) diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h index 2b00833b6641..dc0697c2fa92 100644 --- a/arch/arm/mach-exynos/include/mach/pm-core.h +++ b/arch/arm/mach-exynos/include/mach/pm-core.h @@ -19,7 +19,10 @@ #define __ASM_ARCH_PM_CORE_H __FILE__ #include -#include +#include + +#define S5P_EINT_WAKEUP_MASK (S5P_VA_PMU + 0x0604) +#define S5P_WAKEUP_MASK (S5P_VA_PMU + 0x0608) #ifdef CONFIG_PINCTRL_EXYNOS extern u32 exynos_get_eint_wake_mask(void); diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index d36ad76ad6a4..93dcf7fb293d 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -365,8 +365,6 @@ /* Compatibility defines and inclusion */ -#include - #define S5P_EPLL_CON EXYNOS4_EPLL_CON0 #endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index 6609145312ac..e9f7370111f8 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -14,6 +14,7 @@ #include #include +#include #include "common.h" diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h similarity index 99% rename from arch/arm/mach-exynos/include/mach/regs-pmu.h rename to arch/arm/mach-exynos/regs-pmu.h index 2c15a8fbcb5a..7c029ce27711 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -31,8 +31,6 @@ #define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4) #define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) -#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) -#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) #define S5P_INFORM0 S5P_PMUREG(0x0800) #define S5P_INFORM1 S5P_PMUREG(0x0804) From 65c9a8530bec45cea1137635b7992bbb417de9de Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 19 Dec 2013 04:06:56 +0900 Subject: [PATCH 03/13] ARM: EXYNOS: local regs-pmu.h header file This moves regs-pmu.h file into mach-exynos directory. Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/common.c | 3 ++- arch/arm/mach-exynos/cpuidle.c | 2 +- arch/arm/mach-exynos/hotplug.c | 2 +- arch/arm/mach-exynos/mach-exynos5-dt.c | 2 +- arch/arm/mach-exynos/platsmp.c | 2 +- arch/arm/mach-exynos/pm.c | 2 +- arch/arm/mach-exynos/pm_domains.c | 3 ++- arch/arm/mach-exynos/pmu.c | 2 +- 8 files changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 61d2906ccefb..1fc042481c5b 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -38,13 +38,14 @@ #include #include -#include #include #include #include #include "common.h" +#include "regs-pmu.h" + #define L2_AUX_VAL 0x7C470001 #define L2_AUX_MASK 0xC200ffff diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index ddbfe8709fe7..6ba13ea61ad2 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -23,12 +23,12 @@ #include #include #include -#include #include #include #include "common.h" +#include "regs-pmu.h" #define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c index af90cfa2f826..5eead530c6f8 100644 --- a/arch/arm/mach-exynos/hotplug.c +++ b/arch/arm/mach-exynos/hotplug.c @@ -19,10 +19,10 @@ #include #include -#include #include #include "common.h" +#include "regs-pmu.h" static inline void cpu_enter_lowpower_a9(void) { diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 1fe075a70c1e..65a46465ac5e 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -14,10 +14,10 @@ #include #include -#include #include #include "common.h" +#include "regs-pmu.h" static void __init exynos5_dt_machine_init(void) { diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 58b43e6f9262..b5b34f863327 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -28,11 +28,11 @@ #include #include -#include #include #include "common.h" +#include "regs-pmu.h" extern void exynos4_secondary_startup(void); diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 7fb0f13d600d..a577eb929bee 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -31,10 +31,10 @@ #include #include -#include #include #include "common.h" +#include "regs-pmu.h" static const struct sleep_save exynos4_set_clksrc[] = { { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 1703593e366c..ff508360d27c 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -22,9 +22,10 @@ #include #include -#include #include +#include "regs-pmu.h" + /* * Exynos specific wrapper around the generic power domain */ diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index e9f7370111f8..176077c58f86 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -14,9 +14,9 @@ #include #include -#include #include "common.h" +#include "regs-pmu.h" static const struct exynos_pmu_conf *exynos_pmu_config; From 05a6380cef5ec2e832871a8bd591f6af4555c335 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 19 Dec 2013 04:07:32 +0900 Subject: [PATCH 04/13] ARM: EXYNOS: cleanup Remove useless inclusion for exynos. Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/common.c | 2 -- arch/arm/mach-exynos/include/mach/regs-irq.h | 19 ------------------- arch/arm/mach-exynos/pm.c | 1 - arch/arm/plat-samsung/pm.c | 2 ++ arch/arm/plat-samsung/s5p-irq-pm.c | 3 +++ 5 files changed, 5 insertions(+), 22 deletions(-) delete mode 100644 arch/arm/mach-exynos/include/mach/regs-irq.h diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 1fc042481c5b..52cef6a2a825 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -37,8 +37,6 @@ #include #include -#include - #include #include #include diff --git a/arch/arm/mach-exynos/include/mach/regs-irq.h b/arch/arm/mach-exynos/include/mach/regs-irq.h deleted file mode 100644 index f2b50506b9f6..000000000000 --- a/arch/arm/mach-exynos/include/mach/regs-irq.h +++ /dev/null @@ -1,19 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - IRQ register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_IRQ_H -#define __ASM_ARCH_REGS_IRQ_H __FILE__ - -#include -#include - -#endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index a577eb929bee..11c37c4f04fb 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -29,7 +29,6 @@ #include #include -#include #include #include diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 416e5bea54f9..001d6fc6899c 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -29,7 +29,9 @@ #include #include #include +#ifndef CONFIG_ARCH_EXYNOS #include +#endif #include #endif diff --git a/arch/arm/plat-samsung/s5p-irq-pm.c b/arch/arm/plat-samsung/s5p-irq-pm.c index 7c1e3b7072fc..591498035916 100644 --- a/arch/arm/plat-samsung/s5p-irq-pm.c +++ b/arch/arm/plat-samsung/s5p-irq-pm.c @@ -22,7 +22,10 @@ #include #include + +#ifndef CONFIG_ARCH_EXYNOS #include +#endif /* state for IRQs over sleep */ From 728599439fd01a6302270171f5c4e42b14fac6d0 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 19 Dec 2013 04:13:57 +0900 Subject: [PATCH 05/13] ARM: EXYNOS: cleanup Remove useless definitions in the regs-clock.h file. Signed-off-by: Kukjin Kim --- .../arm/mach-exynos/include/mach/regs-clock.h | 189 ------------------ 1 file changed, 189 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index 93dcf7fb293d..d36a6a283b84 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -20,11 +20,9 @@ #define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500) #define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600) -#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800) #define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500) #define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600) -#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800) #define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010) #define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020) @@ -34,19 +32,6 @@ #define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120) #define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124) -#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210) -#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214) -#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220) -#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224) -#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228) -#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C) -#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230) -#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234) -#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C) -#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240) -#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250) -#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254) - #define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310) #define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320) #define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324) @@ -58,72 +43,23 @@ #define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510) #define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520) -#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524) #define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528) -#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C) -#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530) -#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534) -#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C) -#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540) -#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544) -#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548) -#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C) -#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550) -#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554) -#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558) -#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C) -#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560) -#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564) -#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580) #define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610) #define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628) -#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820) -#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920) -#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924) -#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928) -#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C) -#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x0C930) : \ - EXYNOS_CLKREG(0x04930)) #define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930) #define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930) -#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934) -#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940) -#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C) -#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950) -#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x0C960) : \ - EXYNOS_CLKREG(0x08960)) -#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960) -#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960) -#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970) #define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300) -#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200) #define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500) #define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504) #define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600) #define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604) -#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900) #define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094) #define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0) -#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000) -#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x14004) : \ - EXYNOS_CLKREG(0x10008)) -#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100) -#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104) -#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x14108) : \ - EXYNOS_CLKREG(0x10108)) -#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x1410C) : \ - EXYNOS_CLKREG(0x1010C)) - #define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200) #define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400) @@ -132,52 +68,12 @@ #define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600) #define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604) -#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800) -#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900) - -#define EXYNOS4_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x18800) -#define EXYNOS4_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x18804) - -#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */ - -#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31) -#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29) -#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) -#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) - -#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31) #define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) - -#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31) #define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0) -#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4) -#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8) -#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12) -#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16) -#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20) -#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24) -#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28 -#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT) - -#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0 -#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) -#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4 -#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) -#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8 -#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT) - #define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) #define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) #define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4) @@ -242,10 +138,7 @@ /* Only for EXYNOS4210 */ -#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238) #define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338) -#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538) -#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938) /* Only for EXYNOS4212 */ @@ -260,7 +153,6 @@ #define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000) #define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100) -#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200) #define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400) #define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500) #define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504) @@ -270,83 +162,6 @@ #define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020) #define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024) -#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100) -#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204) - -#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900) - -#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500) - -#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130) -#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134) -#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138) -#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140) -#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144) -#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148) -#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120) - -#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210) -#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214) -#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218) -#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C) -#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220) -#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C) -#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240) -#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244) -#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250) -#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254) -#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270) - -#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310) -#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320) -#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C) -#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334) -#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340) -#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350) -#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354) - -#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510) -#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514) -#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520) -#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C) -#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C) -#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544) -#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548) -#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C) -#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550) -#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554) -#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558) -#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C) -#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560) -#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564) -#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568) -#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C) -#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580) - -#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800) -#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800) -#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804) -#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920) -#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928) -#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C) -#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930) -#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934) -#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944) -#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C) -#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950) -#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960) -#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980) - -#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110) -#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) -#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) - -#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24) - -#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030) - -#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) - #define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) #define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) @@ -363,8 +178,4 @@ #define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) #define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) -/* Compatibility defines and inclusion */ - -#define S5P_EPLL_CON EXYNOS4_EPLL_CON0 - #endif /* __ASM_ARCH_REGS_CLOCK_H */ From 7d8f159188410557630a7270efe3e14a1a305c2e Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 19 Dec 2013 04:17:06 +0900 Subject: [PATCH 06/13] PM / devfreq: move definitions for exynos4_bus into drivers/devfreq We don't need to keep the definitions for exynos4_bus into mach-exynos/ so this moves them into drviers/devfreq with adding header file. Acked-by: MyungJoo Ham Signed-off-by: Kukjin Kim --- .../arm/mach-exynos/include/mach/regs-clock.h | 94 --------------- drivers/devfreq/exynos/exynos4_bus.c | 4 +- drivers/devfreq/exynos/exynos4_bus.h | 110 ++++++++++++++++++ 3 files changed, 112 insertions(+), 96 deletions(-) create mode 100644 drivers/devfreq/exynos/exynos4_bus.h diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index d36a6a283b84..855f1b2c1fdc 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -18,12 +18,6 @@ #define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x)) -#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500) -#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600) - -#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500) -#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600) - #define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010) #define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020) @@ -41,24 +35,7 @@ #define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350) #define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354) -#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510) -#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520) -#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528) - -#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610) -#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628) - -#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930) -#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930) - #define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300) -#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500) -#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504) -#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600) -#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604) - -#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094) -#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0) #define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200) #define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400) @@ -74,81 +51,10 @@ #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) -#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4) -#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8) -#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12) -#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16) -#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20) -#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24) -#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28) -#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT) - -#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0) -#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4) -#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8) -#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12) -#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16) -#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24) -#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT) - -#define EXYNOS4_CLKDIV_MFC_SHIFT (0) -#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT) - -#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0) -#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4) -#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8) -#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12) -#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16) -#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20) -#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24) -#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT) - -#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0) -#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) -#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4) -#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT) - -#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0) -#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) -#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4) -#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) -#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8) -#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) -#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12) -#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT) - /* Only for EXYNOS4210 */ #define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338) -/* Only for EXYNOS4212 */ - -#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568) - -#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668) - -#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) -#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) - /* For EXYNOS5250 */ #define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000) diff --git a/drivers/devfreq/exynos/exynos4_bus.c b/drivers/devfreq/exynos/exynos4_bus.c index cede6f71cd63..16eb406cadb6 100644 --- a/drivers/devfreq/exynos/exynos4_bus.c +++ b/drivers/devfreq/exynos/exynos4_bus.c @@ -30,10 +30,10 @@ extern unsigned int exynos_result_of_asv; #endif -#include - #include +#include "exynos4_bus.h" + #define MAX_SAFEVOLT 1200000 /* 1.2V */ enum exynos4_busf_type { diff --git a/drivers/devfreq/exynos/exynos4_bus.h b/drivers/devfreq/exynos/exynos4_bus.h new file mode 100644 index 000000000000..94c73c18d28c --- /dev/null +++ b/drivers/devfreq/exynos/exynos4_bus.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS4 BUS header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __DEVFREQ_EXYNOS4_BUS_H +#define __DEVFREQ_EXYNOS4_BUS_H __FILE__ + +#include + +#define EXYNOS4_CLKDIV_LEFTBUS (S5P_VA_CMU + 0x04500) +#define EXYNOS4_CLKDIV_STAT_LEFTBUS (S5P_VA_CMU + 0x04600) + +#define EXYNOS4_CLKDIV_RIGHTBUS (S5P_VA_CMU + 0x08500) +#define EXYNOS4_CLKDIV_STAT_RIGHTBUS (S5P_VA_CMU + 0x08600) + +#define EXYNOS4_CLKDIV_TOP (S5P_VA_CMU + 0x0C510) +#define EXYNOS4_CLKDIV_CAM (S5P_VA_CMU + 0x0C520) +#define EXYNOS4_CLKDIV_MFC (S5P_VA_CMU + 0x0C528) + +#define EXYNOS4_CLKDIV_STAT_TOP (S5P_VA_CMU + 0x0C610) +#define EXYNOS4_CLKDIV_STAT_MFC (S5P_VA_CMU + 0x0C628) + +#define EXYNOS4210_CLKGATE_IP_IMAGE (S5P_VA_CMU + 0x0C930) +#define EXYNOS4212_CLKGATE_IP_IMAGE (S5P_VA_CMU + 0x04930) + +#define EXYNOS4_CLKDIV_DMC0 (S5P_VA_CMU + 0x10500) +#define EXYNOS4_CLKDIV_DMC1 (S5P_VA_CMU + 0x10504) +#define EXYNOS4_CLKDIV_STAT_DMC0 (S5P_VA_CMU + 0x10600) +#define EXYNOS4_CLKDIV_STAT_DMC1 (S5P_VA_CMU + 0x10604) + +#define EXYNOS4_DMC_PAUSE_CTRL (S5P_VA_CMU + 0x11094) +#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0) + +#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) +#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4) +#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8) +#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12) +#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16) +#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20) +#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24) +#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) +#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28) +#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT) + +#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0) +#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) +#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4) +#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) +#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8) +#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT) +#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12) +#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT) +#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16) +#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT) +#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24) +#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT) + +#define EXYNOS4_CLKDIV_MFC_SHIFT (0) +#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT) + +#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0) +#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) +#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4) +#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) +#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8) +#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) +#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12) +#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) +#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16) +#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT) +#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20) +#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) +#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24) +#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT) + +#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0) +#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) +#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4) +#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT) + +#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0) +#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) +#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4) +#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) +#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8) +#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) +#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12) +#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT) + +#define EXYNOS4_CLKDIV_CAM1 (S5P_VA_CMU + 0x0C568) + +#define EXYNOS4_CLKDIV_STAT_CAM1 (S5P_VA_CMU + 0x0C668) + +#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) +#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) + +#endif /* __DEVFREQ_EXYNOS4_BUS_H */ From 9c9239afe31f67d137ba6c45b244b509c2090567 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 19 Dec 2013 04:19:59 +0900 Subject: [PATCH 07/13] ARM: EXYNOS: local definitions for pm.c into mach-exynos dir Some of definitions in the regs-clock.h are used only for pm.c, so this moves them into the file. Signed-off-by: Kukjin Kim --- .../arm/mach-exynos/include/mach/regs-clock.h | 26 ------------------- arch/arm/mach-exynos/pm.c | 26 ++++++++++++++++++- 2 files changed, 25 insertions(+), 27 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index 855f1b2c1fdc..5acc06e4bca8 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -18,25 +18,6 @@ #define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x)) -#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010) -#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020) - -#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110) -#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114) -#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120) -#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124) - -#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310) -#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320) -#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324) -#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334) -#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C) -#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340) -#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350) -#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354) - -#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300) - #define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200) #define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400) @@ -45,16 +26,9 @@ #define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600) #define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604) -#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) -#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) - #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) -/* Only for EXYNOS4210 */ - -#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338) - /* For EXYNOS5250 */ #define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 11c37c4f04fb..e00025bbbe89 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -29,12 +29,36 @@ #include #include -#include +#include #include #include "common.h" #include "regs-pmu.h" +#define EXYNOS4_EPLL_LOCK (S5P_VA_CMU + 0x0C010) +#define EXYNOS4_VPLL_LOCK (S5P_VA_CMU + 0x0C020) + +#define EXYNOS4_EPLL_CON0 (S5P_VA_CMU + 0x0C110) +#define EXYNOS4_EPLL_CON1 (S5P_VA_CMU + 0x0C114) +#define EXYNOS4_VPLL_CON0 (S5P_VA_CMU + 0x0C120) +#define EXYNOS4_VPLL_CON1 (S5P_VA_CMU + 0x0C124) + +#define EXYNOS4_CLKSRC_MASK_TOP (S5P_VA_CMU + 0x0C310) +#define EXYNOS4_CLKSRC_MASK_CAM (S5P_VA_CMU + 0x0C320) +#define EXYNOS4_CLKSRC_MASK_TV (S5P_VA_CMU + 0x0C324) +#define EXYNOS4_CLKSRC_MASK_LCD0 (S5P_VA_CMU + 0x0C334) +#define EXYNOS4_CLKSRC_MASK_MAUDIO (S5P_VA_CMU + 0x0C33C) +#define EXYNOS4_CLKSRC_MASK_FSYS (S5P_VA_CMU + 0x0C340) +#define EXYNOS4_CLKSRC_MASK_PERIL0 (S5P_VA_CMU + 0x0C350) +#define EXYNOS4_CLKSRC_MASK_PERIL1 (S5P_VA_CMU + 0x0C354) + +#define EXYNOS4_CLKSRC_MASK_DMC (S5P_VA_CMU + 0x10300) + +#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) +#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) + +#define EXYNOS4210_CLKSRC_MASK_LCD1 (S5P_VA_CMU + 0x0C338) + static const struct sleep_save exynos4_set_clksrc[] = { { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, }, From df3e9c057e502c0d46ba37cbb67d52904e97b4c4 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 19 Dec 2013 04:21:34 +0900 Subject: [PATCH 08/13] cpufreq: exynos: move definitions for exynos-cpufreq into drivers/cpufreq/ This moves regarding exynos-cpufreq definitions into drivers/cpufreq/ exynos-cpufreq.h because they are used only for the cpufreq driver. Cc: Rafael J. Wysocki Acked-by: Viresh Kumar Signed-off-by: Kukjin Kim --- .../arm/mach-exynos/include/mach/regs-clock.h | 21 ------------------ drivers/cpufreq/exynos-cpufreq.h | 22 +++++++++++++++++++ drivers/cpufreq/exynos4210-cpufreq.c | 2 -- drivers/cpufreq/exynos4x12-cpufreq.c | 2 -- drivers/cpufreq/exynos5250-cpufreq.c | 1 - 5 files changed, 22 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index 5acc06e4bca8..22afe63e8c30 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -18,27 +18,6 @@ #define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x)) -#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200) -#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400) - -#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500) -#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504) -#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600) -#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604) - -#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) -#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) - -/* For EXYNOS5250 */ - -#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000) -#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100) -#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400) -#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500) -#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504) -#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600) -#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604) - #define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020) #define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024) diff --git a/drivers/cpufreq/exynos-cpufreq.h b/drivers/cpufreq/exynos-cpufreq.h index 7f25cee8cec2..3ddade8a5125 100644 --- a/drivers/cpufreq/exynos-cpufreq.h +++ b/drivers/cpufreq/exynos-cpufreq.h @@ -67,3 +67,25 @@ static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) return -EOPNOTSUPP; } #endif + +#include +#include + +#define EXYNOS4_CLKSRC_CPU (S5P_VA_CMU + 0x14200) +#define EXYNOS4_CLKMUX_STATCPU (S5P_VA_CMU + 0x14400) + +#define EXYNOS4_CLKDIV_CPU (S5P_VA_CMU + 0x14500) +#define EXYNOS4_CLKDIV_CPU1 (S5P_VA_CMU + 0x14504) +#define EXYNOS4_CLKDIV_STATCPU (S5P_VA_CMU + 0x14600) +#define EXYNOS4_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x14604) + +#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) +#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) + +#define EXYNOS5_APLL_LOCK (S5P_VA_CMU + 0x00000) +#define EXYNOS5_APLL_CON0 (S5P_VA_CMU + 0x00100) +#define EXYNOS5_CLKMUX_STATCPU (S5P_VA_CMU + 0x00400) +#define EXYNOS5_CLKDIV_CPU0 (S5P_VA_CMU + 0x00500) +#define EXYNOS5_CLKDIV_CPU1 (S5P_VA_CMU + 0x00504) +#define EXYNOS5_CLKDIV_STATCPU0 (S5P_VA_CMU + 0x00600) +#define EXYNOS5_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x00604) diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c index f2c75065ce19..05d166d837cf 100644 --- a/drivers/cpufreq/exynos4210-cpufreq.c +++ b/drivers/cpufreq/exynos4210-cpufreq.c @@ -17,8 +17,6 @@ #include #include -#include - #include "exynos-cpufreq.h" static struct clk *cpu_clk; diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c index 8683304ce62c..bd795b0d25e1 100644 --- a/drivers/cpufreq/exynos4x12-cpufreq.c +++ b/drivers/cpufreq/exynos4x12-cpufreq.c @@ -17,8 +17,6 @@ #include #include -#include - #include "exynos-cpufreq.h" static struct clk *cpu_clk; diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c index 9fae466d7746..ec99432a62f5 100644 --- a/drivers/cpufreq/exynos5250-cpufreq.c +++ b/drivers/cpufreq/exynos5250-cpufreq.c @@ -18,7 +18,6 @@ #include #include -#include #include "exynos-cpufreq.h" From b5fd13008e26e10481f2ae65a2a5ed47959a9343 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 19 Dec 2013 04:22:09 +0900 Subject: [PATCH 09/13] ARM: EXYNOS: local definitions for cpuidle.c into mach-exynos dir This moves definitions for cpuidle into mach-exynos/cpuidle.c, because we don't need to keep them in the . Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/cpuidle.c | 23 ++++++++++++++++++- .../arm/mach-exynos/include/mach/regs-clock.h | 21 ----------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index 6ba13ea61ad2..da65b036af2b 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -22,11 +22,13 @@ #include #include #include -#include #include #include +#include +#include + #include "common.h" #include "regs-pmu.h" @@ -39,6 +41,25 @@ #define S5P_CHECK_AFTR 0xFCBA0D10 +#define EXYNOS5_PWR_CTRL1 (S5P_VA_CMU + 0x01020) +#define EXYNOS5_PWR_CTRL2 (S5P_VA_CMU + 0x01024) + +#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) +#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) +#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) +#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) +#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) +#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) +#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) +#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) + +#define PWR_CTRL2_DIV2_UP_EN (1 << 25) +#define PWR_CTRL2_DIV1_UP_EN (1 << 24) +#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) +#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) +#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) +#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) + static int exynos4_enter_lowpower(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index 22afe63e8c30..cc121a582d2f 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -16,25 +16,4 @@ #include #include -#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x)) - -#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020) -#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024) - -#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) -#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) -#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) -#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) -#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) -#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) -#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) -#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) - -#define PWR_CTRL2_DIV2_UP_EN (1 << 25) -#define PWR_CTRL2_DIV1_UP_EN (1 << 24) -#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) -#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) -#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) -#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) - #endif /* __ASM_ARCH_REGS_CLOCK_H */ From 2857f650d5fa57bcd56a4efd4161e51ce1508255 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 19 Dec 2013 04:22:40 +0900 Subject: [PATCH 10/13] ARM: EXYNOS: remove for exynos Signed-off-by: Kukjin Kim --- .../arm/mach-exynos/include/mach/regs-clock.h | 19 ------------------- arch/arm/mach-exynos/platsmp.c | 1 - arch/arm/mach-exynos/pmu.c | 2 +- arch/arm/plat-samsung/pm.c | 2 +- 4 files changed, 2 insertions(+), 22 deletions(-) delete mode 100644 arch/arm/mach-exynos/include/mach/regs-clock.h diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h deleted file mode 100644 index cc121a582d2f..000000000000 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ /dev/null @@ -1,19 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - Clock register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_CLOCK_H -#define __ASM_ARCH_REGS_CLOCK_H __FILE__ - -#include -#include - -#endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index b5b34f863327..474432f29f89 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -27,7 +27,6 @@ #include #include -#include #include diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index 176077c58f86..05c7ce15322a 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -13,7 +13,7 @@ #include #include -#include +#include #include "common.h" #include "regs-pmu.h" diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 001d6fc6899c..e5b0f2c2d884 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -28,8 +28,8 @@ #ifdef CONFIG_SAMSUNG_ATAGS #include #include -#include #ifndef CONFIG_ARCH_EXYNOS +#include #include #endif #include From 118ce5b97840542ed7b4c1b4cb31fd566dbe2057 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 19 Dec 2013 04:23:13 +0900 Subject: [PATCH 11/13] PM / devfreq: use inclusion instead of This fixes follwoing warning: In file included from drivers/devfreq/exynos/exynos4_bus.h:15:0, from drivers/devfreq/exynos/exynos4_bus.c:35: arch/arm/mach-exynos/include/mach/map.h:22:0: warning: "S3C_UART_OFFSET" redefined [enabled by default] In file included from drivers/devfreq/exynos/exynos4_bus.c:33:0: arch/arm/plat-samsung/include/plat/map-s5p.h:57:0: note: this is the location of the previous definition Acked-by: MyungJoo Ham Signed-off-by: Kukjin Kim --- drivers/devfreq/exynos/exynos4_bus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/devfreq/exynos/exynos4_bus.c b/drivers/devfreq/exynos/exynos4_bus.c index 16eb406cadb6..1ab8cdd48c17 100644 --- a/drivers/devfreq/exynos/exynos4_bus.c +++ b/drivers/devfreq/exynos/exynos4_bus.c @@ -30,7 +30,7 @@ extern unsigned int exynos_result_of_asv; #endif -#include +#include #include "exynos4_bus.h" From 26282884035bab3286b03da19006dab9684d7242 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Sat, 21 Dec 2013 06:33:26 +0900 Subject: [PATCH 12/13] ARM: EXYNOS: Consolidate selection of PM_GENERIC_DOMAINS for Exynos4 Instead of repeating "select PM_GENERIC_DOMAINS" for all Exynos4 variants add relevant entry in the Kconfig section common to the SoC series. Signed-off-by: Sylwester Nawrocki Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/Kconfig | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index f9d67a0acb2a..4c414af75ef0 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -24,6 +24,7 @@ config ARCH_EXYNOS4 select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL + select PM_GENERIC_DOMAINS if PM select S5P_DEV_MFC help Samsung EXYNOS4 SoCs based systems @@ -48,7 +49,6 @@ config CPU_EXYNOS4210 select ARCH_HAS_BANDGAP select ARM_CPU_SUSPEND if PM select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM select S5P_PM if PM select S5P_SLEEP if PM select SAMSUNG_DMADEV @@ -61,7 +61,6 @@ config SOC_EXYNOS4212 depends on ARCH_EXYNOS4 select ARCH_HAS_BANDGAP select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM select S5P_PM if PM select S5P_SLEEP if PM select SAMSUNG_DMADEV @@ -74,7 +73,6 @@ config SOC_EXYNOS4412 depends on ARCH_EXYNOS4 select ARCH_HAS_BANDGAP select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM select SAMSUNG_DMADEV help Enable EXYNOS4412 SoC support From 1fd3cbccaf47aefbe3bfb026d310cd2f5d0685c6 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Sat, 21 Dec 2013 06:33:30 +0900 Subject: [PATCH 13/13] ARM: EXYNOS: Kill exynos_pm_late_initcall() The only thing exynos_pm_late_initcall() does is calling pm_genpd_poweroff_unused(), which is already stubbed when CONFIG_PM_GENERIC_DOMAINS is not enabled. So replace exynos_pm_late_initcall() with a direct call to pm_genpd_poweroff_unused(). Signed-off-by: Sylwester Nawrocki Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/common.c | 3 ++- arch/arm/mach-exynos/common.h | 6 ------ arch/arm/mach-exynos/pm_domains.c | 6 ------ 3 files changed, 2 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 52cef6a2a825..72ae5d3a87d2 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -308,7 +309,7 @@ void __init exynos_init_late(void) /* to be supported later */ return; - exynos_pm_late_initcall(); + pm_genpd_poweroff_unused(); } static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index ff9b6a9419b0..0c31b34f0de5 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -26,12 +26,6 @@ void exynos_init_late(void); void exynos_firmware_init(void); -#ifdef CONFIG_PM_GENERIC_DOMAINS -int exynos_pm_late_initcall(void); -#else -static inline int exynos_pm_late_initcall(void) { return 0; } -#endif - extern struct smp_operations exynos_smp_ops; extern void exynos_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index ff508360d27c..8fd24882f0b1 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -184,9 +184,3 @@ static __init int exynos4_pm_init_power_domain(void) return 0; } arch_initcall(exynos4_pm_init_power_domain); - -int __init exynos_pm_late_initcall(void) -{ - pm_genpd_poweroff_unused(); - return 0; -}