phy: phy-mtk-tphy: add support efuse setting
Due to some SoCs have a bit shift issue that will drop a bit for usb3 phy or pcie phy, fix it by adding software efuse reading and setting, but only support it optionally for version 2/3. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20211218082802.5256-2-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Chunfeng Yun
Vinod Koul
Родитель
c6d92a287a
Коммит
6f2b033cb8
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@ -12,6 +12,7 @@
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#include <linux/iopoll.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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@ -41,6 +42,9 @@
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#define SSUSB_SIFSLV_V2_U3PHYD 0x200
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#define SSUSB_SIFSLV_V2_U3PHYA 0x400
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#define U3P_MISC_REG1 0x04
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#define MR1_EFUSE_AUTO_LOAD_DIS BIT(6)
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#define U3P_USBPHYACR0 0x000
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#define PA0_RG_U2PLL_FORCE_ON BIT(15)
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#define PA0_USB20_PLL_PREDIV GENMASK(7, 6)
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@ -133,6 +137,8 @@
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#define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24)
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#define U3P_U3_PHYA_REG0 0x000
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#define P3A_RG_IEXT_INTR GENMASK(15, 10)
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#define P3A_RG_IEXT_INTR_VAL(x) ((0x3f & (x)) << 10)
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#define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
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#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
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@ -187,6 +193,19 @@
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#define P3D_RG_FWAKE_TH GENMASK(21, 16)
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#define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
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#define U3P_U3_PHYD_IMPCAL0 0x010
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#define P3D_RG_FORCE_TX_IMPEL BIT(31)
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#define P3D_RG_TX_IMPEL GENMASK(28, 24)
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#define P3D_RG_TX_IMPEL_VAL(x) ((0x1f & (x)) << 24)
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#define U3P_U3_PHYD_IMPCAL1 0x014
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#define P3D_RG_FORCE_RX_IMPEL BIT(31)
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#define P3D_RG_RX_IMPEL GENMASK(28, 24)
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#define P3D_RG_RX_IMPEL_VAL(x) ((0x1f & (x)) << 24)
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#define U3P_U3_PHYD_RSV 0x054
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#define P3D_RG_EFUSE_AUTO_LOAD_DIS BIT(12)
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#define U3P_U3_PHYD_CDR1 0x05c
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#define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
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#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
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@ -307,6 +326,11 @@ struct mtk_phy_pdata {
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* 48M PLL, fix it by switching PLL to 26M from default 48M
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*/
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bool sw_pll_48m_to_26m;
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/*
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* Some SoCs (e.g. mt8195) drop a bit when use auto load efuse,
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* support sw way, also support it for v2/v3 optionally.
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*/
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bool sw_efuse_supported;
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enum mtk_phy_version version;
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};
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@ -336,6 +360,10 @@ struct mtk_phy_instance {
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struct regmap *type_sw;
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u32 type_sw_reg;
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u32 type_sw_index;
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u32 efuse_sw_en;
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u32 efuse_intr;
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u32 efuse_tx_imp;
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u32 efuse_rx_imp;
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int eye_src;
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int eye_vrt;
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int eye_term;
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@ -1040,6 +1068,130 @@ static int phy_type_set(struct mtk_phy_instance *instance)
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return 0;
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}
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static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instance)
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{
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struct device *dev = &instance->phy->dev;
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int ret = 0;
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/* tphy v1 doesn't support sw efuse, skip it */
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if (!tphy->pdata->sw_efuse_supported) {
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instance->efuse_sw_en = 0;
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return 0;
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}
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/* software efuse is optional */
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instance->efuse_sw_en = device_property_read_bool(dev, "nvmem-cells");
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if (!instance->efuse_sw_en)
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return 0;
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switch (instance->type) {
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case PHY_TYPE_USB2:
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ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
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if (ret) {
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dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
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break;
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}
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/* no efuse, ignore it */
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if (!instance->efuse_intr) {
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dev_warn(dev, "no u2 intr efuse, but dts enable it\n");
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instance->efuse_sw_en = 0;
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break;
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}
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dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr);
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break;
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case PHY_TYPE_USB3:
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case PHY_TYPE_PCIE:
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ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
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if (ret) {
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dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
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break;
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}
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ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp);
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if (ret) {
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dev_err(dev, "fail to get u3 rx_imp efuse, %d\n", ret);
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break;
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}
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ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp);
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if (ret) {
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dev_err(dev, "fail to get u3 tx_imp efuse, %d\n", ret);
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break;
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}
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/* no efuse, ignore it */
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if (!instance->efuse_intr &&
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!instance->efuse_rx_imp &&
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!instance->efuse_rx_imp) {
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dev_warn(dev, "no u3 intr efuse, but dts enable it\n");
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instance->efuse_sw_en = 0;
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break;
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}
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dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",
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instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);
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break;
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default:
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dev_err(dev, "no sw efuse for type %d\n", instance->type);
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ret = -EINVAL;
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}
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return ret;
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}
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static void phy_efuse_set(struct mtk_phy_instance *instance)
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{
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struct device *dev = &instance->phy->dev;
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struct u2phy_banks *u2_banks = &instance->u2_banks;
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struct u3phy_banks *u3_banks = &instance->u3_banks;
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u32 tmp;
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if (!instance->efuse_sw_en)
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return;
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switch (instance->type) {
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case PHY_TYPE_USB2:
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tmp = readl(u2_banks->misc + U3P_MISC_REG1);
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tmp |= MR1_EFUSE_AUTO_LOAD_DIS;
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writel(tmp, u2_banks->misc + U3P_MISC_REG1);
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tmp = readl(u2_banks->com + U3P_USBPHYACR1);
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tmp &= ~PA1_RG_INTR_CAL;
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tmp |= PA1_RG_INTR_CAL_VAL(instance->efuse_intr);
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writel(tmp, u2_banks->com + U3P_USBPHYACR1);
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break;
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case PHY_TYPE_USB3:
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case PHY_TYPE_PCIE:
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tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
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tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
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writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
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tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
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tmp &= ~P3D_RG_TX_IMPEL;
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tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp);
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tmp |= P3D_RG_FORCE_TX_IMPEL;
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writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
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tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
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tmp &= ~P3D_RG_RX_IMPEL;
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tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp);
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tmp |= P3D_RG_FORCE_RX_IMPEL;
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writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
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tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
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tmp &= ~P3A_RG_IEXT_INTR;
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tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
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writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
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break;
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default:
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dev_warn(dev, "no sw efuse for type %d\n", instance->type);
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break;
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}
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}
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static int mtk_phy_init(struct phy *phy)
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{
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struct mtk_phy_instance *instance = phy_get_drvdata(phy);
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@ -1050,6 +1202,8 @@ static int mtk_phy_init(struct phy *phy)
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if (ret)
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return ret;
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phy_efuse_set(instance);
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switch (instance->type) {
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case PHY_TYPE_USB2:
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u2_phy_instance_init(tphy, instance);
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@ -1134,6 +1288,7 @@ static struct phy *mtk_phy_xlate(struct device *dev,
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struct mtk_phy_instance *instance = NULL;
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struct device_node *phy_np = args->np;
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int index;
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int ret;
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if (args->args_count != 1) {
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dev_err(dev, "invalid number of cells in 'phy' property\n");
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@ -1174,6 +1329,10 @@ static struct phy *mtk_phy_xlate(struct device *dev,
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return ERR_PTR(-EINVAL);
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}
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ret = phy_efuse_get(tphy, instance);
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if (ret)
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return ERR_PTR(ret);
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phy_parse_property(tphy, instance);
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phy_type_set(instance);
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@ -1196,10 +1355,12 @@ static const struct mtk_phy_pdata tphy_v1_pdata = {
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static const struct mtk_phy_pdata tphy_v2_pdata = {
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.avoid_rx_sen_degradation = false,
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.sw_efuse_supported = true,
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.version = MTK_PHY_V2,
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};
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static const struct mtk_phy_pdata tphy_v3_pdata = {
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.sw_efuse_supported = true,
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.version = MTK_PHY_V3,
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};
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@ -1210,6 +1371,7 @@ static const struct mtk_phy_pdata mt8173_pdata = {
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static const struct mtk_phy_pdata mt8195_pdata = {
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.sw_pll_48m_to_26m = true,
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.sw_efuse_supported = true,
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.version = MTK_PHY_V3,
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};
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