ARM: clk: imx31: properly init clocks for machines with DT
Clock initialization for i.MX31 powered machines with DT support should be done by a call of an init function registered with CLK_OF_DECLARE() in common clock framework. The change converts exported mx31_clocks_init_dt() into a static initialization function registered by CLK_OF_DECLARE(). Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -43,7 +43,6 @@ int mx21_clocks_init(unsigned long lref, unsigned long fref);
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int mx27_clocks_init(unsigned long fref);
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int mx27_clocks_init(unsigned long fref);
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int mx31_clocks_init(unsigned long fref);
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int mx31_clocks_init(unsigned long fref);
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int mx35_clocks_init(void);
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int mx35_clocks_init(void);
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int mx31_clocks_init_dt(void);
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struct platform_device *mxc_register_gpio(char *name, int id,
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struct platform_device *mxc_register_gpio(char *name, int id,
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resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
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resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
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void mxc_set_cpu_type(unsigned int type);
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void mxc_set_cpu_type(unsigned int type);
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@ -23,11 +23,6 @@ static const char * const imx31_dt_board_compat[] __initconst = {
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NULL
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NULL
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};
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};
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static void __init imx31_dt_timer_init(void)
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{
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mx31_clocks_init_dt();
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}
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/* FIXME: replace with DT binding */
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/* FIXME: replace with DT binding */
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static const struct resource imx31_rnga_res[] __initconst = {
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static const struct resource imx31_rnga_res[] __initconst = {
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DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K),
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DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K),
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@ -43,7 +38,6 @@ DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
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.map_io = mx31_map_io,
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.map_io = mx31_map_io,
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.init_early = imx31_init_early,
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.init_early = imx31_init_early,
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.init_irq = mx31_init_irq,
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.init_irq = mx31_init_irq,
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.init_time = imx31_dt_timer_init,
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.init_machine = imx31_dt_mach_init,
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.init_machine = imx31_dt_mach_init,
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.dt_compat = imx31_dt_board_compat,
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.dt_compat = imx31_dt_board_compat,
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MACHINE_END
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MACHINE_END
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@ -21,6 +21,7 @@
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <soc/imx/revision.h>
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#include <soc/imx/revision.h>
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#include <soc/imx/timer.h>
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#include <soc/imx/timer.h>
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#include <asm/irq.h>
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#include <asm/irq.h>
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@ -72,14 +73,8 @@ static struct clk ** const uart_clks[] __initconst = {
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NULL
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NULL
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};
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};
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static void __init _mx31_clocks_init(unsigned long fref)
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static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref)
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{
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{
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void __iomem *base;
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struct device_node *np;
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base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K);
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BUG_ON(!base);
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clk[dummy] = imx_clk_fixed("dummy", 0);
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clk[dummy] = imx_clk_fixed("dummy", 0);
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clk[ckih] = imx_clk_fixed("ckih", fref);
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clk[ckih] = imx_clk_fixed("ckih", fref);
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clk[ckil] = imx_clk_fixed("ckil", 32768);
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clk[ckil] = imx_clk_fixed("ckil", 32768);
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@ -147,19 +142,17 @@ static void __init _mx31_clocks_init(unsigned long fref)
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clk_prepare_enable(clk[iim_gate]);
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clk_prepare_enable(clk[iim_gate]);
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mx31_revision();
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mx31_revision();
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clk_disable_unprepare(clk[iim_gate]);
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clk_disable_unprepare(clk[iim_gate]);
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np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
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if (np) {
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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}
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}
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}
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int __init mx31_clocks_init(unsigned long fref)
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int __init mx31_clocks_init(unsigned long fref)
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{
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{
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_mx31_clocks_init(fref);
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void __iomem *base;
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base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K);
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if (!base)
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panic("%s: failed to map registers\n", __func__);
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_mx31_clocks_init(base, fref);
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clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
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clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
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clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
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clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
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@ -222,22 +215,31 @@ int __init mx31_clocks_init(unsigned long fref)
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return 0;
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return 0;
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}
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}
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int __init mx31_clocks_init_dt(void)
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static void __init mx31_clocks_init_dt(struct device_node *np)
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{
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{
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struct device_node *np;
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struct device_node *osc_np;
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u32 fref = 26000000; /* default */
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u32 fref = 26000000; /* default */
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void __iomem *ccm;
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for_each_compatible_node(np, NULL, "fixed-clock") {
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for_each_compatible_node(osc_np, NULL, "fixed-clock") {
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if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
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if (!of_device_is_compatible(osc_np, "fsl,imx-osc26m"))
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continue;
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continue;
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if (!of_property_read_u32(np, "clock-frequency", &fref)) {
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if (!of_property_read_u32(osc_np, "clock-frequency", &fref)) {
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of_node_put(np);
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of_node_put(osc_np);
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break;
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break;
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}
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}
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}
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}
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_mx31_clocks_init(fref);
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ccm = of_iomap(np, 0);
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if (!ccm)
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panic("%s: failed to map registers\n", __func__);
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return 0;
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_mx31_clocks_init(ccm, fref);
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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}
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}
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CLK_OF_DECLARE(imx31_ccm, "fsl,imx31-ccm", mx31_clocks_init_dt);
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