DaVinci: move AEMIF #define's to the proper headers
Currently each DaVinci board file #define's its own version of the EMIFA base addresses (all named DAVINCI_ASYNC_EMIF_*_BASE), which leads to duplication. Move these #define's to the SoC specific headers, changing their prefixes from 'DAVINCI' to the 'DM355', 'DM644X', and 'DM646X' since all these base addresses are SoC specific... And while at it, rename DM646X_ASYNC_EMIF_DATA_CE0_BASE to DM646X_ASYNC_EMIF_CS2_SPACE_BASE in order to match the DM646x datasheet. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Sergei Shtylyov
Kevin Hilman
Родитель
ef03592a1a
Коммит
7034217467
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@ -33,9 +33,6 @@
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#include <mach/mmc.h>
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#include <mach/usb.h>
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#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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/* NOTE: this is geared for the standard config, with a socketed
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* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
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* swap chips, maybe with a different block size, partitioning may
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@ -86,12 +83,12 @@ static struct davinci_nand_pdata davinci_nand_data = {
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static struct resource davinci_nand_resources[] = {
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{
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.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
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.start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
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.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.start = DM355_ASYNC_EMIF_CONTROL_BASE,
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.end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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@ -30,9 +30,6 @@
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#include <mach/mmc.h>
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#include <mach/usb.h>
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#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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/* NOTE: this is geared for the standard config, with a socketed
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* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
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* swap chips, maybe with a different block size, partitioning may
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@ -82,12 +79,12 @@ static struct davinci_nand_pdata davinci_nand_data = {
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static struct resource davinci_nand_resources[] = {
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{
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.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
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.start = DM355_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
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.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.start = DM355_ASYNC_EMIF_CONTROL_BASE,
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.end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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@ -54,11 +54,6 @@ static inline int have_tvp7002(void)
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return 0;
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}
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#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
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#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
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#define DM365_EVM_PHY_MASK (0x2)
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#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
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@ -43,12 +43,6 @@
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#define DAVINCI_CFC_ATA_BASE 0x01C66000
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#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
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#define LXT971_PHY_ID (0x001378e2)
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#define LXT971_PHY_MASK (0xfffffff0)
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@ -92,8 +86,8 @@ static struct physmap_flash_data davinci_evm_norflash_data = {
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/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
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* limits addresses to 16M, so using addresses past 16M will wrap */
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static struct resource davinci_evm_norflash_resource = {
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.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
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.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
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.flags = IORESOURCE_MEM,
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};
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@ -154,12 +148,12 @@ static struct davinci_nand_pdata davinci_evm_nandflash_data = {
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static struct resource davinci_evm_nandflash_resource[] = {
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{
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.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
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.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
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.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.start = DM644X_ASYNC_EMIF_CONTROL_BASE,
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.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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@ -80,17 +80,14 @@ static struct davinci_nand_pdata davinci_nand_data = {
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.options = 0,
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};
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#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
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static struct resource davinci_nand_resources[] = {
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{
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.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
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.start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
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.end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
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.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.start = DM646X_ASYNC_EMIF_CONTROL_BASE,
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.end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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@ -43,9 +43,6 @@
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#define DAVINCI_CFC_ATA_BASE 0x01C66000
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#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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#define LXT971_PHY_ID 0x001378e2
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#define LXT971_PHY_MASK 0xfffffff0
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@ -98,12 +95,12 @@ static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
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static struct resource davinci_ntosd2_nandflash_resource[] = {
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{
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.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
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.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
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.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.start = DM644X_ASYNC_EMIF_CONTROL_BASE,
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.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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@ -45,9 +45,6 @@
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#define SFFSDR_PHY_MASK (0x2)
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#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
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#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
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/* U-Boot Environment: Block 0
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* UBL: Block 1
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@ -76,12 +73,12 @@ static struct flash_platform_data davinci_sffsdr_nandflash_data = {
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static struct resource davinci_sffsdr_nandflash_resource[] = {
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{
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.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
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.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
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.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.start = DM644X_ASYNC_EMIF_CONTROL_BASE,
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.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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@ -15,6 +15,9 @@
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#include <mach/asp.h>
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#include <media/davinci/vpfe_capture.h>
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#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01E10000
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#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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#define ASP1_TX_EVT_EN 1
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#define ASP1_RX_EVT_EN 2
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@ -36,6 +36,10 @@
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#define DAVINCI_DMA_VC_TX 2
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#define DAVINCI_DMA_VC_RX 3
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#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01D10000
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#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
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void __init dm365_init(void);
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void __init dm365_init_asp(struct snd_platform_data *pdata);
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void __init dm365_init_vc(struct snd_platform_data *pdata);
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@ -34,6 +34,12 @@
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#define DM644X_EMAC_MDIO_OFFSET (0x4000)
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#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
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#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01E00000
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#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
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#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
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#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
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void __init dm644x_init(void);
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void __init dm644x_init_asp(struct snd_platform_data *pdata);
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void dm644x_set_vpfe_config(struct vpfe_config *cfg);
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@ -27,6 +27,9 @@
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#define DM646X_ATA_REG_BASE (0x01C66000)
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#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
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#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
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void __init dm646x_init(void);
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void __init dm646x_init_ide(void);
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void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
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