Devicetree changes for TI K3 platforms for v5.14 merge window:
* New features:
- AM64 gains PCIe and USB3 for am64-sk board, R5 remote proc (includes
AM64 rproc bindings tag from Bjorn's tree)
- AM65, J721e gains ICSSG MDIO nodes
- AM65: UHS mode speed enabled on am65
* Fixes:
- Fixups on AM64 SRAM model thanks to a ROM bug for USB DFU mode
- Schema related cleanups across j7*, am65, 64
- Few misc Fixups on AM64 where MAC address could conflict; j7200 for
USB2 Rx sensitivity etc.
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Merge tag 'ti-k3-dt-for-v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt
Devicetree changes for TI K3 platforms for v5.14 merge window:
* New features:
- AM64 gains PCIe and USB3 for am64-sk board, R5 remote proc (includes
AM64 rproc bindings tag from Bjorn's tree)
- AM65, J721e gains ICSSG MDIO nodes
- AM65: UHS mode speed enabled on am65
* Fixes:
- Fixups on AM64 SRAM model thanks to a ROM bug for USB DFU mode
- Schema related cleanups across j7*, am65, 64
- Few misc Fixups on AM64 where MAC address could conflict; j7200 for
USB2 Rx sensitivity etc.
* tag 'ti-k3-dt-for-v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: (37 commits)
arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for R5Fs
arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs
arm64: dts: ti: k3-am64-main: Add MAIN domain R5F cluster nodes
arm64: dts: ti: k3-am64-main: Update TF-A load address to workaround USB DFU limitation
arm64: dts: ti: k3-am64-main: Reserve OCMRAM for DMSC-lite and secure proxy communication
arm64: dts: ti: k3-am64-main: Update TF-A's maximum size and node name
arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes
arm64: dts: ti: k3-am642-evm: align ti,pindir-d0-out-d1-in property with dt-shema
arm64: dts: ti: am65: align ti,pindir-d0-out-d1-in property with dt-shema
arm64: dts: ti: k3-am642-main: fix ports mac properties
arm64: dts: ti: iot2050: Configure r5f cluster on basic variant in split mode
arm64: dts: ti: k3-am642-sk: Disable PCIe
arm64: dts: ti: k3-am642-sk: Enable USB Super-Speed HOST port
arm64: dts: ti: k3-am642-evm: Enable PCIe and SERDES
arm64: dts: ti: k3-am64-main: Add PCIe DT node
arm64: dts: ti: k3-am64-main: Add SERDES DT node
arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy"
arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES
arm64: dts: ti: k3-j721e-main: Add #clock-cells property to serdes DT node
arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES
...
Link: https://lore.kernel.org/r/20210619000150.6ooqnxxsnsvncs5u@pushchair
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
707472acca
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|
@ -14,8 +14,12 @@ description: |
|
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processor subsystems/clusters (R5FSS). The dual core cluster can be used
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either in a LockStep mode providing safety/fault tolerance features or in a
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Split mode providing two individual compute cores for doubling the compute
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capacity. These are used together with other processors present on the SoC
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to achieve various system level goals.
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capacity on most SoCs. These are used together with other processors present
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on the SoC to achieve various system level goals.
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AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
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called "Single-CPU" mode, where only Core0 is used, but with ability to use
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Core1's TCMs as well.
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Each Dual-Core R5F sub-system is represented as a single DTS node
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representing the cluster, with a pair of child DT nodes representing
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|
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@ -33,6 +37,7 @@ properties:
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- ti,am654-r5fss
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- ti,j721e-r5fss
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- ti,j7200-r5fss
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- ti,am64-r5fss
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power-domains:
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description: |
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@ -56,11 +61,12 @@ properties:
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ti,cluster-mode:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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description: |
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Configuration Mode for the Dual R5F cores within the R5F cluster.
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Should be either a value of 1 (LockStep mode) or 0 (Split mode),
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default is LockStep mode if omitted.
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Should be either a value of 1 (LockStep mode) or 0 (Split mode) on
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most SoCs (AM65x, J721E, J7200), default is LockStep mode if omitted;
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and should be either a value of 0 (Split mode) or 2 (Single-CPU mode)
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on AM64x SoCs, default is Split mode if omitted.
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# R5F Processor Child Nodes:
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# ==========================
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@ -97,6 +103,7 @@ patternProperties:
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- ti,am654-r5f
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- ti,j721e-r5f
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- ti,j7200-r5f
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- ti,am64-r5f
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reg:
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items:
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@ -198,6 +205,20 @@ patternProperties:
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unevaluatedProperties: false
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if:
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properties:
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compatible:
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enum:
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- ti,am64-r5fss
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then:
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properties:
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ti,cluster-mode:
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enum: [0, 2]
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else:
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properties:
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ti,cluster-mode:
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enum: [0, 1]
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required:
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- compatible
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- power-domains
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|
|
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@ -5,6 +5,17 @@
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/phy/phy-cadence.h>
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#include <dt-bindings/phy/phy-ti.h>
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/ {
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serdes_refclk: clock-cmnrefclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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&cbass_main {
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oc_sram: sram@70000000 {
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compatible = "mmio-sram";
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@ -13,8 +24,30 @@
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#size-cells = <1>;
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ranges = <0x0 0x00 0x70000000 0x200000>;
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atf-sram@0 {
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reg = <0x0 0x1a000>;
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tfa-sram@1c0000 {
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reg = <0x1c0000 0x20000>;
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};
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dmsc-sram@1e0000 {
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reg = <0x1e0000 0x1c000>;
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};
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sproxy-sram@1fc000 {
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reg = <0x1fc000 0x4000>;
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};
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};
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main_conf: syscon@43000000 {
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compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
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reg = <0x0 0x43000000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x43000000 0x20000>;
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serdes_ln_ctrl: mux-controller {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
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};
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};
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@ -42,12 +75,12 @@
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};
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};
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dmss: dmss {
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dmss: bus@48000000 {
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-ranges;
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ranges;
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ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
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ti,sci-dev-id = <25>;
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@ -134,7 +167,7 @@
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};
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};
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dmsc: dmsc@44043000 {
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dmsc: system-controller@44043000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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@ -148,7 +181,7 @@
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#power-domain-cells = <2>;
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};
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k3_clks: clocks {
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k3_clks: clock-controller {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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@ -189,8 +222,6 @@
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main_uart0: serial@2800000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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@ -202,8 +233,6 @@
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main_uart1: serial@2810000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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@ -215,8 +244,6 @@
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main_uart2: serial@2820000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02820000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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@ -228,8 +255,6 @@
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main_uart3: serial@2830000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02830000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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@ -241,8 +266,6 @@
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main_uart4: serial@2840000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02840000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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|
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@ -254,8 +277,6 @@
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main_uart5: serial@2850000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02850000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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|
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@ -267,8 +288,6 @@
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main_uart6: serial@2860000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02860000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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|
|
@ -373,8 +392,9 @@
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clocks = <&k3_clks 145 0>;
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};
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main_gpio_intr: interrupt-controller0 {
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main_gpio_intr: interrupt-controller@a00000 {
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compatible = "ti,sci-intr";
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reg = <0x00 0x00a00000 0x00 0x800>;
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
|
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|
|
@ -488,7 +508,8 @@
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ti,mac-only;
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label = "port1";
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phys = <&phy_gmii_sel 1>;
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mac-address = [00 00 de ad be ef];
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mac-address = [00 00 00 00 00 00];
|
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ti,syscon-efuse = <&main_conf 0x200>;
|
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};
|
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|
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cpsw_port2: port@2 {
|
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|
|
@ -496,7 +517,7 @@
|
|||
ti,mac-only;
|
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label = "port2";
|
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phys = <&phy_gmii_sel 2>;
|
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mac-address = [00 01 de ad be ef];
|
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mac-address = [00 00 00 00 00 00];
|
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};
|
||||
};
|
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|
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|
|
@ -672,4 +693,170 @@
|
|||
ti,mbox-num-users = <4>;
|
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ti,mbox-num-fifos = <16>;
|
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};
|
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|
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main_r5fss0: r5fss@78000000 {
|
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compatible = "ti,am64-r5fss";
|
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ti,cluster-mode = <0>;
|
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#address-cells = <1>;
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#size-cells = <1>;
|
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ranges = <0x78000000 0x00 0x78000000 0x10000>,
|
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<0x78100000 0x00 0x78100000 0x10000>,
|
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<0x78200000 0x00 0x78200000 0x08000>,
|
||||
<0x78300000 0x00 0x78300000 0x08000>;
|
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power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
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main_r5fss0_core0: r5f@78000000 {
|
||||
compatible = "ti,am64-r5f";
|
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reg = <0x78000000 0x00010000>,
|
||||
<0x78100000 0x00010000>;
|
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reg-names = "atcm", "btcm";
|
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ti,sci = <&dmsc>;
|
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ti,sci-dev-id = <121>;
|
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ti,sci-proc-ids = <0x01 0xff>;
|
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resets = <&k3_reset 121 1>;
|
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firmware-name = "am64-main-r5f0_0-fw";
|
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ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
|
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main_r5fss0_core1: r5f@78200000 {
|
||||
compatible = "ti,am64-r5f";
|
||||
reg = <0x78200000 0x00008000>,
|
||||
<0x78300000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <122>;
|
||||
ti,sci-proc-ids = <0x02 0xff>;
|
||||
resets = <&k3_reset 122 1>;
|
||||
firmware-name = "am64-main-r5f0_1-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
main_r5fss1: r5fss@78400000 {
|
||||
compatible = "ti,am64-r5fss";
|
||||
ti,cluster-mode = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x78400000 0x00 0x78400000 0x10000>,
|
||||
<0x78500000 0x00 0x78500000 0x10000>,
|
||||
<0x78600000 0x00 0x78600000 0x08000>,
|
||||
<0x78700000 0x00 0x78700000 0x08000>;
|
||||
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
main_r5fss1_core0: r5f@78400000 {
|
||||
compatible = "ti,am64-r5f";
|
||||
reg = <0x78400000 0x00010000>,
|
||||
<0x78500000 0x00010000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <123>;
|
||||
ti,sci-proc-ids = <0x06 0xff>;
|
||||
resets = <&k3_reset 123 1>;
|
||||
firmware-name = "am64-main-r5f1_0-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
|
||||
main_r5fss1_core1: r5f@78600000 {
|
||||
compatible = "ti,am64-r5f";
|
||||
reg = <0x78600000 0x00008000>,
|
||||
<0x78700000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <124>;
|
||||
ti,sci-proc-ids = <0x07 0xff>;
|
||||
resets = <&k3_reset 124 1>;
|
||||
firmware-name = "am64-main-r5f1_1-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
serdes_wiz0: wiz@f000000 {
|
||||
compatible = "ti,am64-wiz-10g";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
num-lanes = <1>;
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
|
||||
|
||||
assigned-clocks = <&k3_clks 162 1>;
|
||||
assigned-clock-parents = <&k3_clks 162 5>;
|
||||
|
||||
serdes0: serdes@f000000 {
|
||||
compatible = "ti,j721e-serdes-10g";
|
||||
reg = <0x0f000000 0x00010000>;
|
||||
reg-names = "torrent_phy";
|
||||
resets = <&serdes_wiz0 0>;
|
||||
reset-names = "torrent_reset";
|
||||
clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
|
||||
<&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
|
||||
clock-names = "refclk", "phy_en_refclk";
|
||||
assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
|
||||
<&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
|
||||
<&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
|
||||
assigned-clock-parents = <&k3_clks 162 1>,
|
||||
<&k3_clks 162 1>,
|
||||
<&k3_clks 162 1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_rc: pcie@f102000 {
|
||||
compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
|
||||
reg = <0x00 0x0f102000 0x00 0x1000>,
|
||||
<0x00 0x0f100000 0x00 0x400>,
|
||||
<0x00 0x0d000000 0x00 0x00800000>,
|
||||
<0x00 0x68000000 0x00 0x00001000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
|
||||
max-link-speed = <2>;
|
||||
num-lanes = <1>;
|
||||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
|
||||
clock-names = "fck", "pcie_refclk";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
cdns,no-bar-match-nbits = <64>;
|
||||
vendor-id = <0x104c>;
|
||||
device-id = <0xb010>;
|
||||
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
||||
ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
|
||||
<0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
|
||||
};
|
||||
|
||||
pcie0_ep: pcie-ep@f102000 {
|
||||
compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
|
||||
reg = <0x00 0x0f102000 0x00 0x1000>,
|
||||
<0x00 0x0f100000 0x00 0x400>,
|
||||
<0x00 0x0d000000 0x00 0x00800000>,
|
||||
<0x00 0x68000000 0x00 0x08000000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
|
||||
max-link-speed = <2>;
|
||||
num-lanes = <1>;
|
||||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 114 0>;
|
||||
clock-names = "fck";
|
||||
max-functions = /bits/ 8 <1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,8 +9,6 @@
|
|||
mcu_uart0: serial@4a00000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a00000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -22,8 +20,6 @@
|
|||
mcu_uart1: serial@4a10000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a10000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -74,8 +70,9 @@
|
|||
clocks = <&k3_clks 148 0>;
|
||||
};
|
||||
|
||||
mcu_gpio_intr: interrupt-controller1 {
|
||||
mcu_gpio_intr: interrupt-controller@4210000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x04210000 0x00 0x200>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -86,7 +83,7 @@
|
|||
};
|
||||
|
||||
mcu_gpio0: gpio@4201000 {
|
||||
compatible = "ti,am64-gpio", "keystone-gpio";
|
||||
compatible = "ti,am64-gpio", "ti,keystone-gpio";
|
||||
reg = <0x0 0x4201000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/mux/ti-serdes.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
|
|
@ -36,6 +38,60 @@
|
|||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
evm_12v0: fixedregulator-evm12v0 {
|
||||
|
|
@ -334,7 +390,7 @@
|
|||
&main_spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_spi0_pins_default>;
|
||||
ti,pindir-d0-out-d1-in = <1>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
eeprom@0 {
|
||||
compatible = "microchip,93lc46b";
|
||||
reg = <0>;
|
||||
|
|
@ -466,3 +522,55 @@
|
|||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
serdes0_pcie_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
resets = <&serdes_wiz0 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <1>;
|
||||
};
|
||||
|
||||
&pcie0_ep {
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/mux/ti-serdes.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am642.dtsi"
|
||||
|
|
@ -35,6 +37,60 @@
|
|||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vusb_main: fixed-regulator-vusb-main5v0 {
|
||||
|
|
@ -85,6 +141,12 @@
|
|||
>;
|
||||
};
|
||||
|
||||
main_usb0_pins_default: main-usb0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
|
||||
|
|
@ -235,6 +297,33 @@
|
|||
disable-wp;
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <AM64_SERDES0_LANE0_USB>;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
serdes0_usb_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_USB3>;
|
||||
resets = <&serdes_wiz0 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dr_mode = "host";
|
||||
maximum-speed = "super-speed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb0_pins_default>;
|
||||
phys = <&serdes0_usb_link>;
|
||||
phy-names = "cdns3,usb3-phy";
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default
|
||||
|
|
@ -332,3 +421,35 @@
|
|||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie0_ep {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -555,6 +555,7 @@
|
|||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
|
|
@ -575,7 +576,7 @@
|
|||
|
||||
#address-cells = <1>;
|
||||
#size-cells= <0>;
|
||||
ti,pindir-d0-out-d1-in = <1>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
};
|
||||
|
||||
&tscadc0 {
|
||||
|
|
@ -653,3 +654,63 @@
|
|||
&pcie1_ep {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster8 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster9 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster10 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster11 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg0_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg1_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg2_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -84,8 +84,6 @@
|
|||
main_uart0: serial@2800000 {
|
||||
compatible = "ti,am654-uart";
|
||||
reg = <0x00 0x02800000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -95,8 +93,6 @@
|
|||
main_uart1: serial@2810000 {
|
||||
compatible = "ti,am654-uart";
|
||||
reg = <0x00 0x02810000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -105,8 +101,6 @@
|
|||
main_uart2: serial@2820000 {
|
||||
compatible = "ti,am654-uart";
|
||||
reg = <0x00 0x02820000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -301,7 +295,6 @@
|
|||
ti,otap-del-sel = <0x2>;
|
||||
ti,trm-icp = <0x8>;
|
||||
dma-coherent;
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
scm_conf: scm-conf@100000 {
|
||||
|
|
@ -433,8 +426,9 @@
|
|||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
intr_main_gpio: interrupt-controller0 {
|
||||
intr_main_gpio: interrupt-controller@a00000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x0 0x00a00000 0x0 0x400>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -444,18 +438,19 @@
|
|||
ti,interrupt-ranges = <0 392 32>;
|
||||
};
|
||||
|
||||
main-navss {
|
||||
main_navss: bus@30800000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
ti,sci-dev-id = <118>;
|
||||
|
||||
intr_main_navss: interrupt-controller1 {
|
||||
intr_main_navss: interrupt-controller@310e0000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x0 0x310e0000 0x0 0x2000>;
|
||||
ti,intr-trigger-type = <4>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -1051,6 +1046,16 @@
|
|||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-txpru0_1-fw";
|
||||
};
|
||||
|
||||
icssg0_mdio: mdio@32400 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
reg = <0x32400 0x100>;
|
||||
clocks = <&k3_clks 62 3>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
icssg1: icssg@b100000 {
|
||||
|
|
@ -1182,6 +1187,16 @@
|
|||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-txpru1_1-fw";
|
||||
};
|
||||
|
||||
icssg1_mdio: mdio@32400 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
reg = <0x32400 0x100>;
|
||||
clocks = <&k3_clks 63 3>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
icssg2: icssg@b200000 {
|
||||
|
|
@ -1313,5 +1328,15 @@
|
|||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-txpru2_1-fw";
|
||||
};
|
||||
|
||||
icssg2_mdio: mdio@32400 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
reg = <0x32400 0x100>;
|
||||
clocks = <&k3_clks 64 3>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -23,8 +23,6 @@
|
|||
mcu_uart0: serial@40a00000 {
|
||||
compatible = "ti,am654-uart";
|
||||
reg = <0x00 0x40a00000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <96000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -116,11 +114,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
mcu-navss {
|
||||
mcu_navss: bus@28380000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
|
|
|
|||
|
|
@ -6,24 +6,24 @@
|
|||
*/
|
||||
|
||||
&cbass_wakeup {
|
||||
dmsc: dmsc {
|
||||
dmsc: system-controller@44083000 {
|
||||
compatible = "ti,am654-sci";
|
||||
ti,host-id = <12>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mbox-names = "rx", "tx";
|
||||
|
||||
mboxes= <&secure_proxy_main 11>,
|
||||
<&secure_proxy_main 13>;
|
||||
|
||||
reg-names = "debug_messages";
|
||||
reg = <0x44083000 0x1000>;
|
||||
|
||||
k3_pds: power-controller {
|
||||
compatible = "ti,sci-pm-domain";
|
||||
#power-domain-cells = <2>;
|
||||
};
|
||||
|
||||
k3_clks: clocks {
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
|
@ -50,8 +50,6 @@
|
|||
wkup_uart0: serial@42300000 {
|
||||
compatible = "ti,am654-uart";
|
||||
reg = <0x42300000 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -69,8 +67,9 @@
|
|||
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
intr_wkup_gpio: interrupt-controller2 {
|
||||
intr_wkup_gpio: interrupt-controller@42200000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x42200000 0x200>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
|
|||
|
|
@ -59,3 +59,8 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
/* lock-step mode not supported on this board */
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -86,10 +86,36 @@
|
|||
};
|
||||
};
|
||||
|
||||
clk_ov5640_fixed: clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
evm_12v0: fixedregulator-evm12v0 {
|
||||
/* main supply */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_12v0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc3v3_io: fixedregulator-vcc3v3io {
|
||||
/* Output of TPS54334 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_io";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&evm_12v0>;
|
||||
};
|
||||
|
||||
vdd_mmc1_sd: fixedregulator-sd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vcc3v3_io>;
|
||||
gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -142,7 +168,7 @@
|
|||
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
|
||||
AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
|
||||
AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
|
||||
AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
|
||||
AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */
|
||||
AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
|
||||
>;
|
||||
};
|
||||
|
|
@ -287,23 +313,6 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
ov5640: camera@3c {
|
||||
compatible = "ovti,ov5640";
|
||||
reg = <0x3c>;
|
||||
|
||||
clocks = <&clk_ov5640_fixed>;
|
||||
clock-names = "xclk";
|
||||
|
||||
port {
|
||||
csi2_cam0: endpoint {
|
||||
remote-endpoint = <&csi2_phy0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&main_i2c2 {
|
||||
|
|
@ -322,7 +331,7 @@
|
|||
pinctrl-0 = <&main_spi0_pins_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells= <0>;
|
||||
ti,pindir-d0-out-d1-in = <1>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
|
||||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
@ -350,6 +359,7 @@
|
|||
* disable sdhci1
|
||||
*/
|
||||
&sdhci1 {
|
||||
vmmc-supply = <&vdd_mmc1_sd>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
|
|
@ -496,14 +506,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&csi2_0 {
|
||||
csi2_phy0: endpoint {
|
||||
remote-endpoint = <&csi2_cam0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
|
||||
|
|
@ -537,3 +539,15 @@
|
|||
&dss {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg0_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg1_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg2_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@
|
|||
J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
|
||||
J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
|
||||
J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
|
||||
J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
|
||||
J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
|
||||
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
|
||||
>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -68,8 +68,9 @@
|
|||
};
|
||||
};
|
||||
|
||||
main_gpio_intr: interrupt-controller0 {
|
||||
main_gpio_intr: interrupt-controller@a00000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x00a00000 0x00 0x800>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -85,9 +86,12 @@
|
|||
#size-cells = <2>;
|
||||
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
|
||||
ti,sci-dev-id = <199>;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
main_navss_intr: interrupt-controller1 {
|
||||
main_navss_intr: interrupt-controller@310e0000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x310e0000 0x00 0x4000>;
|
||||
ti,intr-trigger-type = <4>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -297,8 +301,6 @@
|
|||
main_uart0: serial@2800000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02800000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -310,8 +312,6 @@
|
|||
main_uart1: serial@2810000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02810000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -323,8 +323,6 @@
|
|||
main_uart2: serial@2820000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02820000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -336,8 +334,6 @@
|
|||
main_uart3: serial@2830000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02830000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -349,8 +345,6 @@
|
|||
main_uart4: serial@2840000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02840000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -362,8 +356,6 @@
|
|||
main_uart5: serial@2850000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02850000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -375,8 +367,6 @@
|
|||
main_uart6: serial@2860000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02860000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -388,8 +378,6 @@
|
|||
main_uart7: serial@2870000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02870000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -401,8 +389,6 @@
|
|||
main_uart8: serial@2880000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02880000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -414,8 +400,6 @@
|
|||
main_uart9: serial@2890000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02890000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -679,6 +663,7 @@
|
|||
"otg";
|
||||
maximum-speed = "super-speed";
|
||||
dr_mode = "otg";
|
||||
cdns,phyrst-a-enable;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -692,7 +677,6 @@
|
|||
<149>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -710,7 +694,6 @@
|
|||
<158>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -728,7 +711,6 @@
|
|||
<167>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -746,7 +728,6 @@
|
|||
<176>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
*/
|
||||
|
||||
&cbass_mcu_wakeup {
|
||||
dmsc: dmsc@44083000 {
|
||||
dmsc: system-controller@44083000 {
|
||||
compatible = "ti,k2g-sci";
|
||||
ti,host-id = <12>;
|
||||
|
||||
|
|
@ -23,7 +23,7 @@
|
|||
#power-domain-cells = <2>;
|
||||
};
|
||||
|
||||
k3_clks: clocks {
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
|
@ -73,8 +73,6 @@
|
|||
wkup_uart0: serial@42300000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x42300000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -86,8 +84,6 @@
|
|||
mcu_uart0: serial@40a00000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x40a00000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <96000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -96,8 +92,9 @@
|
|||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
wkup_gpio_intr: interrupt-controller2 {
|
||||
wkup_gpio_intr: interrupt-controller@42200000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x42200000 0x00 0x400>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -116,7 +113,6 @@
|
|||
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
ti,ngpio = <85>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -133,7 +129,6 @@
|
|||
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
ti,ngpio = <85>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include <dt-bindings/phy/phy-cadence.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
|
|
@ -237,7 +238,7 @@
|
|||
J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
|
||||
J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
|
||||
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
|
||||
J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
|
||||
J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
|
||||
J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
|
||||
>;
|
||||
};
|
||||
|
|
@ -358,7 +359,7 @@
|
|||
};
|
||||
|
||||
&serdes3 {
|
||||
serdes3_usb_link: link@0 {
|
||||
serdes3_usb_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
|
|
@ -635,8 +636,45 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&cmn_refclk1 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&wiz0_pll1_refclk {
|
||||
assigned-clocks = <&wiz0_pll1_refclk>;
|
||||
assigned-clock-parents = <&cmn_refclk1>;
|
||||
};
|
||||
|
||||
&wiz0_refclk_dig {
|
||||
assigned-clocks = <&wiz0_refclk_dig>;
|
||||
assigned-clock-parents = <&cmn_refclk1>;
|
||||
};
|
||||
|
||||
&wiz1_pll1_refclk {
|
||||
assigned-clocks = <&wiz1_pll1_refclk>;
|
||||
assigned-clock-parents = <&cmn_refclk1>;
|
||||
};
|
||||
|
||||
&wiz1_refclk_dig {
|
||||
assigned-clocks = <&wiz1_refclk_dig>;
|
||||
assigned-clock-parents = <&cmn_refclk1>;
|
||||
};
|
||||
|
||||
&wiz2_pll1_refclk {
|
||||
assigned-clocks = <&wiz2_pll1_refclk>;
|
||||
assigned-clock-parents = <&cmn_refclk1>;
|
||||
};
|
||||
|
||||
&wiz2_refclk_dig {
|
||||
assigned-clocks = <&wiz2_refclk_dig>;
|
||||
assigned-clock-parents = <&cmn_refclk1>;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
serdes0_pcie_link: link@0 {
|
||||
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
|
||||
assigned-clock-parents = <&wiz0_pll1_refclk>;
|
||||
|
||||
serdes0_pcie_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
|
@ -646,7 +684,10 @@
|
|||
};
|
||||
|
||||
&serdes1 {
|
||||
serdes1_pcie_link: link@0 {
|
||||
assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
|
||||
assigned-clock-parents = <&wiz1_pll1_refclk>;
|
||||
|
||||
serdes1_pcie_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
|
|
@ -656,7 +697,10 @@
|
|||
};
|
||||
|
||||
&serdes2 {
|
||||
serdes2_pcie_link: link@0 {
|
||||
assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
|
||||
assigned-clock-parents = <&wiz2_pll1_refclk>;
|
||||
|
||||
serdes2_pcie_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
|
|
@ -718,3 +762,11 @@
|
|||
&dss {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg0_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg1_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,6 +8,20 @@
|
|||
#include <dt-bindings/mux/mux.h>
|
||||
#include <dt-bindings/mux/ti-serdes.h>
|
||||
|
||||
/ {
|
||||
cmn_refclk: clock-cmnrefclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cmn_refclk1: clock-cmnrefclk1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
msmc_ram: sram@70000000 {
|
||||
compatible = "mmio-sram";
|
||||
|
|
@ -76,8 +90,9 @@
|
|||
};
|
||||
};
|
||||
|
||||
main_gpio_intr: interrupt-controller0 {
|
||||
main_gpio_intr: interrupt-controller@a00000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x00a00000 0x00 0x800>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -87,18 +102,19 @@
|
|||
ti,interrupt-ranges = <8 392 56>;
|
||||
};
|
||||
|
||||
main-navss {
|
||||
main_navss: bus@30000000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
ti,sci-dev-id = <199>;
|
||||
|
||||
main_navss_intr: interrupt-controller1 {
|
||||
main_navss_intr: interrupt-controller@310e0000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x0 0x310e0000 0x0 0x4000>;
|
||||
ti,intr-trigger-type = <4>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -336,24 +352,12 @@
|
|||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
dummy_cmn_refclk: dummy-cmn-refclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
dummy_cmn_refclk1: dummy-cmn-refclk1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
serdes_wiz0: wiz@5000000 {
|
||||
compatible = "ti,j721e-wiz-16g";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
|
||||
assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
|
||||
|
|
@ -362,21 +366,21 @@
|
|||
ranges = <0x5000000 0x0 0x5000000 0x10000>;
|
||||
|
||||
wiz0_pll0_refclk: pll0-refclk {
|
||||
clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 292 11>, <&cmn_refclk>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz0_pll0_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 292 11>;
|
||||
};
|
||||
|
||||
wiz0_pll1_refclk: pll1-refclk {
|
||||
clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz0_pll1_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 292 0>;
|
||||
};
|
||||
|
||||
wiz0_refclk_dig: refclk-dig {
|
||||
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz0_refclk_dig>;
|
||||
assigned-clock-parents = <&k3_clks 292 11>;
|
||||
|
|
@ -398,10 +402,13 @@
|
|||
reg = <0x5000000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
resets = <&serdes_wiz0 0>;
|
||||
reset-names = "sierra_reset";
|
||||
clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
|
||||
clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
|
||||
<&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
|
||||
"pll0_refclk", "pll1_refclk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -410,7 +417,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
|
||||
assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
|
||||
|
|
@ -419,21 +426,21 @@
|
|||
ranges = <0x5010000 0x0 0x5010000 0x10000>;
|
||||
|
||||
wiz1_pll0_refclk: pll0-refclk {
|
||||
clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 293 13>, <&cmn_refclk>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz1_pll0_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 293 13>;
|
||||
};
|
||||
|
||||
wiz1_pll1_refclk: pll1-refclk {
|
||||
clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz1_pll1_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 293 0>;
|
||||
};
|
||||
|
||||
wiz1_refclk_dig: refclk-dig {
|
||||
clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz1_refclk_dig>;
|
||||
assigned-clock-parents = <&k3_clks 293 13>;
|
||||
|
|
@ -455,10 +462,13 @@
|
|||
reg = <0x5010000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
resets = <&serdes_wiz1 0>;
|
||||
reset-names = "sierra_reset";
|
||||
clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
|
||||
clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
|
||||
<&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
|
||||
"pll0_refclk", "pll1_refclk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -467,7 +477,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
|
||||
assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
|
||||
|
|
@ -476,21 +486,21 @@
|
|||
ranges = <0x5020000 0x0 0x5020000 0x10000>;
|
||||
|
||||
wiz2_pll0_refclk: pll0-refclk {
|
||||
clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 294 11>, <&cmn_refclk>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz2_pll0_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 294 11>;
|
||||
};
|
||||
|
||||
wiz2_pll1_refclk: pll1-refclk {
|
||||
clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz2_pll1_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 294 0>;
|
||||
};
|
||||
|
||||
wiz2_refclk_dig: refclk-dig {
|
||||
clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz2_refclk_dig>;
|
||||
assigned-clock-parents = <&k3_clks 294 11>;
|
||||
|
|
@ -512,10 +522,13 @@
|
|||
reg = <0x5020000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
resets = <&serdes_wiz2 0>;
|
||||
reset-names = "sierra_reset";
|
||||
clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
|
||||
clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
|
||||
<&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
|
||||
"pll0_refclk", "pll1_refclk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -524,7 +537,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
|
||||
assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
|
||||
|
|
@ -533,21 +546,21 @@
|
|||
ranges = <0x5030000 0x0 0x5030000 0x10000>;
|
||||
|
||||
wiz3_pll0_refclk: pll0-refclk {
|
||||
clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 295 9>, <&cmn_refclk>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz3_pll0_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 295 9>;
|
||||
};
|
||||
|
||||
wiz3_pll1_refclk: pll1-refclk {
|
||||
clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz3_pll1_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 295 0>;
|
||||
};
|
||||
|
||||
wiz3_refclk_dig: refclk-dig {
|
||||
clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz3_refclk_dig>;
|
||||
assigned-clock-parents = <&k3_clks 295 9>;
|
||||
|
|
@ -569,10 +582,13 @@
|
|||
reg = <0x5030000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
resets = <&serdes_wiz3 0>;
|
||||
reset-names = "sierra_reset";
|
||||
clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
|
||||
clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
|
||||
<&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
|
||||
"pll0_refclk", "pll1_refclk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -773,8 +789,6 @@
|
|||
main_uart0: serial@2800000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02800000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -786,8 +800,6 @@
|
|||
main_uart1: serial@2810000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02810000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -799,8 +811,6 @@
|
|||
main_uart2: serial@2820000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02820000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -812,8 +822,6 @@
|
|||
main_uart3: serial@2830000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02830000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -825,8 +833,6 @@
|
|||
main_uart4: serial@2840000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02840000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -838,8 +844,6 @@
|
|||
main_uart5: serial@2850000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02850000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -851,8 +855,6 @@
|
|||
main_uart6: serial@2860000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02860000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -864,8 +866,6 @@
|
|||
main_uart7: serial@2870000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02870000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -877,8 +877,6 @@
|
|||
main_uart8: serial@2880000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02880000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -890,8 +888,6 @@
|
|||
main_uart9: serial@2890000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02890000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -1792,6 +1788,16 @@
|
|||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-txpru0_1-fw";
|
||||
};
|
||||
|
||||
icssg0_mdio: mdio@32400 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
reg = <0x32400 0x100>;
|
||||
clocks = <&k3_clks 119 1>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
icssg1: icssg@b100000 {
|
||||
|
|
@ -1923,5 +1929,15 @@
|
|||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-txpru1_1-fw";
|
||||
};
|
||||
|
||||
icssg1_mdio: mdio@32400 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
reg = <0x32400 0x100>;
|
||||
clocks = <&k3_clks 120 4>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
*/
|
||||
|
||||
&cbass_mcu_wakeup {
|
||||
dmsc: dmsc@44083000 {
|
||||
dmsc: system-controller@44083000 {
|
||||
compatible = "ti,k2g-sci";
|
||||
ti,host-id = <12>;
|
||||
|
||||
|
|
@ -23,7 +23,7 @@
|
|||
#power-domain-cells = <2>;
|
||||
};
|
||||
|
||||
k3_clks: clocks {
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
|
@ -73,8 +73,6 @@
|
|||
wkup_uart0: serial@42300000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x42300000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -86,8 +84,6 @@
|
|||
mcu_uart0: serial@40a00000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x40a00000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <96000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -96,8 +92,9 @@
|
|||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
wkup_gpio_intr: interrupt-controller2 {
|
||||
wkup_gpio_intr: interrupt-controller@42200000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x42200000 0x00 0x400>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -249,11 +246,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
mcu-navss {
|
||||
mcu_navss: bus@28380000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
|
|
|
|||
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