perf vendor events: Fix typos in power8 PMU events
This replaces the incorrectly spelled word "localtion" with "location"
in some power8 PMU event descriptions.
Fixes: 2a81fa3bb5 ("perf vendor events: Add power8 PMU events")
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-by: Kajol Jain <kjain@linux.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lore.kernel.org/lkml/20201012050205.328523-1-sandipan@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Sandipan Das
Arnaldo Carvalho de Melo
Родитель
bf7ef5ddb0
Коммит
70830f974e
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@ -32,8 +32,8 @@
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{
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"EventCode": "0x1c04e",
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"EventName": "PM_DATA_FROM_L2MISS_MOD",
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"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{
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"EventCode": "0x3c040",
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@ -74,8 +74,8 @@
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{
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"EventCode": "0x4c04e",
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"EventName": "PM_DATA_FROM_L3MISS_MOD",
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"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{
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"EventCode": "0x3c042",
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@ -134,7 +134,7 @@
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{
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"EventCode": "0x4e04e",
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"EventName": "PM_DPTEG_FROM_L3MISS",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request",
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"PublicDescription": ""
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},
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{
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@ -116,8 +116,8 @@
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{
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"EventCode": "0x1404e",
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"EventName": "PM_INST_FROM_L2MISS",
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"BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to an instruction fetch (not prefetch)",
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"PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
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"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)",
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"PublicDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
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},
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{
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"EventCode": "0x34040",
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@ -158,8 +158,8 @@
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{
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"EventCode": "0x4404e",
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"EventName": "PM_INST_FROM_L3MISS_MOD",
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"BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch",
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"PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
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"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch",
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"PublicDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
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},
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{
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"EventCode": "0x34042",
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@ -320,7 +320,7 @@
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{
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"EventCode": "0x1504e",
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"EventName": "PM_IPTEG_FROM_L2MISS",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request",
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"PublicDescription": ""
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},
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{
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@ -344,7 +344,7 @@
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{
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"EventCode": "0x4504e",
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"EventName": "PM_IPTEG_FROM_L3MISS",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request",
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"PublicDescription": ""
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},
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{
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@ -92,7 +92,7 @@
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{
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"EventCode": "0x4c12e",
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"EventName": "PM_MRK_DATA_FROM_L2MISS_CYC",
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"BriefDescription": "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load",
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"BriefDescription": "Duration in cycles to reload from a location other than the local core's L2 due to a marked load",
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"PublicDescription": ""
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},
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{
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@ -158,13 +158,13 @@
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{
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"EventCode": "0x201e4",
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"EventName": "PM_MRK_DATA_FROM_L3MISS",
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"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load",
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"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load",
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"PublicDescription": ""
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},
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{
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"EventCode": "0x2d12e",
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"EventName": "PM_MRK_DATA_FROM_L3MISS_CYC",
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"BriefDescription": "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load",
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"BriefDescription": "Duration in cycles to reload from a location other than the local core's L3 due to a marked load",
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"PublicDescription": ""
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},
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{
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@ -392,7 +392,7 @@
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{
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"EventCode": "0x1f14e",
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"EventName": "PM_MRK_DPTEG_FROM_L2MISS",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request",
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"PublicDescription": ""
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},
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{
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@ -416,7 +416,7 @@
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{
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"EventCode": "0x4f14e",
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"EventName": "PM_MRK_DPTEG_FROM_L3MISS",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request",
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"PublicDescription": ""
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},
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{
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@ -410,8 +410,8 @@
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{
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"EventCode": "0x61c04e",
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"EventName": "PM_DATA_ALL_FROM_L2MISS_MOD",
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"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either demand loads or data prefetch",
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"PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to either demand loads or data prefetch",
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"PublicDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{
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"EventCode": "0x63c040",
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@ -470,8 +470,8 @@
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{
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"EventCode": "0x64c04e",
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"EventName": "PM_DATA_ALL_FROM_L3MISS_MOD",
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"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either demand loads or data prefetch",
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"PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to either demand loads or data prefetch",
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"PublicDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{
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"EventCode": "0x63c042",
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@ -1280,8 +1280,8 @@
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{
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"EventCode": "0x51404e",
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"EventName": "PM_INST_ALL_FROM_L2MISS",
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"BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to instruction fetches and prefetches",
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"PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
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"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to instruction fetches and prefetches",
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"PublicDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
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},
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{
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"EventCode": "0x534040",
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@ -1340,8 +1340,8 @@
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{
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"EventCode": "0x54404e",
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"EventName": "PM_INST_ALL_FROM_L3MISS_MOD",
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"BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch",
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"PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
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"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch",
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"PublicDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
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},
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{
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"EventCode": "0x534042",
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@ -44,7 +44,7 @@
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{
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"EventCode": "0x1e04e",
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"EventName": "PM_DPTEG_FROM_L2MISS",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a data side request",
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"PublicDescription": ""
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},
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{
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