dmaengine fixes-2 for v5.11
Some late fixes for dmaengine: - Core: fix channel device_node deletion - Driver fixes for: - dw: revert of runtime pm enabling - idxd: device state fix, interrupt completion and list corruption - ti: resource leak -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+vs47OPLdNbVcHzyfBQHDyUjg0cFAmAjrkQACgkQfBQHDyUj g0foZA/+Iqpi6fU0Dth4bdoJa5HO63a62G5nrhofF/vH681GMaazNj46byol3vuA Gc0/EZ2UtIkEY29ix0XaHkksQrsqn/Q5E4QK+5u9x32DHf3jvtbOblOSIBCdr//3 i+uc/K90ot4ERtNvwiPxQGWjS7rF+6BvHItRDxOaiele0Uvf18/VGn2x7fH5vNeK GqtZK47E11y5UhqpJAiwcgNAhKXC6I6s/tP0pidyWuXWeqVm+usr6Pun9YExMJQm N+kiR8eJoh5F0N9KAg3rOppxf4iEblvgh2vfMgcNC63GdeWB2x1OMgizAXjE136K HAvcp/3rQf76tUhjZkr/YZaNB7wCqzCRRcgQ/xyhSJt24yswfv9NFGVHd2ltkfx9 Yp+rl8ZC0dSvdGR3ECF9z98MzRbBPgu+TCW/50/Hh42Va0FJZbXyY45hpfR9qPe2 hiXwQkJ8IKH7C8BpDKA8vMlJc4xhbNsYW0GaSyoAUzhaStwTHcKNB4+5Xeia55e3 RR2OPJXl+y3jywcO15fmFdNIRsSvRVGYioFH0NzneaVVIlbQk5hRqADNMWelnwiA DJc21v7yurHeCh3lefn5Aml10n986S1b7XNPA7Ls+2FMmJeIt2vrKqvmKLhHVANY bvSKEXda2pAvb3zw2fCcCuPq6KUdJAfDrB0oorIlRBM3IkY+B5Y= =j/zV -----END PGP SIGNATURE----- Merge tag 'dmaengine-fix2-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine Pull dmaengine fixes from Vinod Koul: "Some late fixes for dmaengine: Core: - fix channel device_node deletion Driver fixes: - dw: revert of runtime pm enabling - idxd: device state fix, interrupt completion and list corruption - ti: resource leak * tag 'dmaengine-fix2-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: dmaengine dw: Revert "dmaengine: dw: Enable runtime PM" dmaengine: idxd: check device state before issue command dmaengine: ti: k3-udma: Fix a resource leak in an error handling path dmaengine: move channel device_node deletion to driver dmaengine: idxd: fix misc interrupt completion dmaengine: idxd: Fix list corruption in description completion
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Коммит
708c2e4181
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@ -1110,7 +1110,6 @@ static void __dma_async_device_channel_unregister(struct dma_device *device,
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"%s called while %d clients hold a reference\n",
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__func__, chan->client_count);
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mutex_lock(&dma_list_mutex);
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list_del(&chan->device_node);
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device->chancnt--;
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chan->dev->chan = NULL;
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mutex_unlock(&dma_list_mutex);
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@ -982,11 +982,8 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
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dev_vdbg(chan2dev(chan), "%s\n", __func__);
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pm_runtime_get_sync(dw->dma.dev);
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/* ASSERT: channel is idle */
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if (dma_readl(dw, CH_EN) & dwc->mask) {
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pm_runtime_put_sync_suspend(dw->dma.dev);
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dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
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return -EIO;
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}
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@ -1003,7 +1000,6 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
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* We need controller-specific data to set up slave transfers.
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*/
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if (chan->private && !dw_dma_filter(chan, chan->private)) {
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pm_runtime_put_sync_suspend(dw->dma.dev);
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dev_warn(chan2dev(chan), "Wrong controller-specific data\n");
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return -EINVAL;
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}
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@ -1047,8 +1043,6 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
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if (!dw->in_use)
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do_dw_dma_off(dw);
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pm_runtime_put_sync_suspend(dw->dma.dev);
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dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
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}
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@ -398,17 +398,31 @@ static inline bool idxd_is_enabled(struct idxd_device *idxd)
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return false;
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}
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static inline bool idxd_device_is_halted(struct idxd_device *idxd)
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{
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union gensts_reg gensts;
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gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
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return (gensts.state == IDXD_DEVICE_STATE_HALT);
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}
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/*
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* This is function is only used for reset during probe and will
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* poll for completion. Once the device is setup with interrupts,
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* all commands will be done via interrupt completion.
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*/
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void idxd_device_init_reset(struct idxd_device *idxd)
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int idxd_device_init_reset(struct idxd_device *idxd)
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{
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struct device *dev = &idxd->pdev->dev;
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union idxd_command_reg cmd;
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unsigned long flags;
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if (idxd_device_is_halted(idxd)) {
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dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
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return -ENXIO;
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}
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memset(&cmd, 0, sizeof(cmd));
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cmd.cmd = IDXD_CMD_RESET_DEVICE;
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dev_dbg(dev, "%s: sending reset for init.\n", __func__);
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@ -419,6 +433,7 @@ void idxd_device_init_reset(struct idxd_device *idxd)
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IDXD_CMDSTS_ACTIVE)
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cpu_relax();
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spin_unlock_irqrestore(&idxd->dev_lock, flags);
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return 0;
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}
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static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
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@ -428,6 +443,12 @@ static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
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DECLARE_COMPLETION_ONSTACK(done);
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unsigned long flags;
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if (idxd_device_is_halted(idxd)) {
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dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
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*status = IDXD_CMDSTS_HW_ERR;
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return;
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}
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memset(&cmd, 0, sizeof(cmd));
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cmd.cmd = cmd_code;
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cmd.operand = operand;
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@ -205,5 +205,8 @@ int idxd_register_dma_channel(struct idxd_wq *wq)
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void idxd_unregister_dma_channel(struct idxd_wq *wq)
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{
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dma_async_device_channel_unregister(&wq->idxd->dma_dev, &wq->dma_chan);
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struct dma_chan *chan = &wq->dma_chan;
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dma_async_device_channel_unregister(&wq->idxd->dma_dev, chan);
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list_del(&chan->device_node);
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}
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@ -326,7 +326,7 @@ void idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id);
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void idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id);
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/* device control */
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void idxd_device_init_reset(struct idxd_device *idxd);
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int idxd_device_init_reset(struct idxd_device *idxd);
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int idxd_device_enable(struct idxd_device *idxd);
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int idxd_device_disable(struct idxd_device *idxd);
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void idxd_device_reset(struct idxd_device *idxd);
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@ -335,7 +335,10 @@ static int idxd_probe(struct idxd_device *idxd)
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int rc;
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dev_dbg(dev, "%s entered and resetting device\n", __func__);
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idxd_device_init_reset(idxd);
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rc = idxd_device_init_reset(idxd);
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if (rc < 0)
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return rc;
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dev_dbg(dev, "IDXD reset complete\n");
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if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM)) {
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@ -111,19 +111,14 @@ irqreturn_t idxd_irq_handler(int vec, void *data)
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return IRQ_WAKE_THREAD;
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}
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irqreturn_t idxd_misc_thread(int vec, void *data)
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static int process_misc_interrupts(struct idxd_device *idxd, u32 cause)
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{
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struct idxd_irq_entry *irq_entry = data;
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struct idxd_device *idxd = irq_entry->idxd;
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struct device *dev = &idxd->pdev->dev;
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union gensts_reg gensts;
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u32 cause, val = 0;
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u32 val = 0;
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int i;
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bool err = false;
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cause = ioread32(idxd->reg_base + IDXD_INTCAUSE_OFFSET);
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iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET);
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if (cause & IDXD_INTC_ERR) {
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spin_lock_bh(&idxd->dev_lock);
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for (i = 0; i < 4; i++)
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@ -181,7 +176,7 @@ irqreturn_t idxd_misc_thread(int vec, void *data)
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val);
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if (!err)
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goto out;
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return 0;
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/*
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* This case should rarely happen and typically is due to software
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@ -211,37 +206,58 @@ irqreturn_t idxd_misc_thread(int vec, void *data)
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gensts.reset_type == IDXD_DEVICE_RESET_FLR ?
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"FLR" : "system reset");
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spin_unlock_bh(&idxd->dev_lock);
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return -ENXIO;
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}
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}
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out:
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return 0;
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}
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irqreturn_t idxd_misc_thread(int vec, void *data)
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{
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struct idxd_irq_entry *irq_entry = data;
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struct idxd_device *idxd = irq_entry->idxd;
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int rc;
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u32 cause;
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cause = ioread32(idxd->reg_base + IDXD_INTCAUSE_OFFSET);
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if (cause)
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iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET);
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while (cause) {
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rc = process_misc_interrupts(idxd, cause);
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if (rc < 0)
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break;
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cause = ioread32(idxd->reg_base + IDXD_INTCAUSE_OFFSET);
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if (cause)
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iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET);
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}
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idxd_unmask_msix_vector(idxd, irq_entry->id);
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return IRQ_HANDLED;
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}
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static bool process_fault(struct idxd_desc *desc, u64 fault_addr)
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static inline bool match_fault(struct idxd_desc *desc, u64 fault_addr)
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{
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/*
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* Completion address can be bad as well. Check fault address match for descriptor
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* and completion address.
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*/
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if ((u64)desc->hw == fault_addr ||
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(u64)desc->completion == fault_addr) {
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idxd_dma_complete_txd(desc, IDXD_COMPLETE_DEV_FAIL);
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if ((u64)desc->hw == fault_addr || (u64)desc->completion == fault_addr) {
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struct idxd_device *idxd = desc->wq->idxd;
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struct device *dev = &idxd->pdev->dev;
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dev_warn(dev, "desc with fault address: %#llx\n", fault_addr);
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return true;
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}
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return false;
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}
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static bool complete_desc(struct idxd_desc *desc)
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static inline void complete_desc(struct idxd_desc *desc, enum idxd_complete_type reason)
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{
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if (desc->completion->status) {
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idxd_dma_complete_txd(desc, IDXD_COMPLETE_NORMAL);
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return true;
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}
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return false;
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idxd_dma_complete_txd(desc, reason);
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idxd_free_desc(desc->wq, desc);
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}
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static int irq_process_pending_llist(struct idxd_irq_entry *irq_entry,
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struct idxd_desc *desc, *t;
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struct llist_node *head;
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int queued = 0;
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bool completed = false;
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unsigned long flags;
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enum idxd_complete_type reason;
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*processed = 0;
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head = llist_del_all(&irq_entry->pending_llist);
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if (!head)
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goto out;
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llist_for_each_entry_safe(desc, t, head, llnode) {
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if (wtype == IRQ_WORK_NORMAL)
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completed = complete_desc(desc);
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else if (wtype == IRQ_WORK_PROCESS_FAULT)
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completed = process_fault(desc, data);
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if (wtype == IRQ_WORK_NORMAL)
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reason = IDXD_COMPLETE_NORMAL;
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else
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reason = IDXD_COMPLETE_DEV_FAIL;
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if (completed) {
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idxd_free_desc(desc->wq, desc);
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llist_for_each_entry_safe(desc, t, head, llnode) {
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if (desc->completion->status) {
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if ((desc->completion->status & DSA_COMP_STATUS_MASK) != DSA_COMP_SUCCESS)
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match_fault(desc, data);
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complete_desc(desc, reason);
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(*processed)++;
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if (wtype == IRQ_WORK_PROCESS_FAULT)
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break;
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} else {
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spin_lock_irqsave(&irq_entry->list_lock, flags);
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list_add_tail(&desc->list,
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enum irq_work_type wtype,
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int *processed, u64 data)
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{
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struct list_head *node, *next;
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int queued = 0;
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bool completed = false;
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unsigned long flags;
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LIST_HEAD(flist);
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struct idxd_desc *desc, *n;
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enum idxd_complete_type reason;
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*processed = 0;
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if (wtype == IRQ_WORK_NORMAL)
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reason = IDXD_COMPLETE_NORMAL;
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else
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reason = IDXD_COMPLETE_DEV_FAIL;
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/*
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* This lock protects list corruption from access of list outside of the irq handler
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* thread.
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*/
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spin_lock_irqsave(&irq_entry->list_lock, flags);
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if (list_empty(&irq_entry->work_list))
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goto out;
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list_for_each_safe(node, next, &irq_entry->work_list) {
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struct idxd_desc *desc =
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container_of(node, struct idxd_desc, list);
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if (list_empty(&irq_entry->work_list)) {
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spin_unlock_irqrestore(&irq_entry->list_lock, flags);
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if (wtype == IRQ_WORK_NORMAL)
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completed = complete_desc(desc);
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else if (wtype == IRQ_WORK_PROCESS_FAULT)
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completed = process_fault(desc, data);
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return 0;
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}
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if (completed) {
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spin_lock_irqsave(&irq_entry->list_lock, flags);
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list_for_each_entry_safe(desc, n, &irq_entry->work_list, list) {
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if (desc->completion->status) {
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list_del(&desc->list);
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spin_unlock_irqrestore(&irq_entry->list_lock, flags);
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idxd_free_desc(desc->wq, desc);
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(*processed)++;
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if (wtype == IRQ_WORK_PROCESS_FAULT)
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return queued;
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list_add_tail(&desc->list, &flist);
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} else {
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queued++;
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}
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spin_lock_irqsave(&irq_entry->list_lock, flags);
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}
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out:
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spin_unlock_irqrestore(&irq_entry->list_lock, flags);
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list_for_each_entry(desc, &flist, list) {
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if ((desc->completion->status & DSA_COMP_STATUS_MASK) != DSA_COMP_SUCCESS)
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match_fault(desc, data);
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complete_desc(desc, reason);
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}
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return queued;
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}
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@ -2401,7 +2401,8 @@ static int bcdma_alloc_chan_resources(struct dma_chan *chan)
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dev_err(ud->ddev.dev,
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"Descriptor pool allocation failed\n");
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uc->use_dma_pool = false;
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return -ENOMEM;
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ret = -ENOMEM;
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goto err_res_free;
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}
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uc->use_dma_pool = true;
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