drm/amdkfd: Support flat memory apertures for GFXv9
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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70a31d16cc
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@ -275,23 +275,35 @@
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* for FLAT_* / S_LOAD operations.
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*/
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#define MAKE_GPUVM_APP_BASE(gpu_num) \
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#define MAKE_GPUVM_APP_BASE_VI(gpu_num) \
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(((uint64_t)(gpu_num) << 61) + 0x1000000000000L)
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#define MAKE_GPUVM_APP_LIMIT(base, size) \
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(((uint64_t)(base) & 0xFFFFFF0000000000UL) + (size) - 1)
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#define MAKE_SCRATCH_APP_BASE() \
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#define MAKE_SCRATCH_APP_BASE_VI() \
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(((uint64_t)(0x1UL) << 61) + 0x100000000L)
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#define MAKE_SCRATCH_APP_LIMIT(base) \
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(((uint64_t)base & 0xFFFFFFFF00000000UL) | 0xFFFFFFFF)
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#define MAKE_LDS_APP_BASE() \
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#define MAKE_LDS_APP_BASE_VI() \
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(((uint64_t)(0x1UL) << 61) + 0x0)
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#define MAKE_LDS_APP_LIMIT(base) \
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(((uint64_t)(base) & 0xFFFFFFFF00000000UL) | 0xFFFFFFFF)
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/* On GFXv9 the LDS and scratch apertures are programmed independently
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* using the high 16 bits of the 64-bit virtual address. They must be
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* in the hole, which will be the case as long as the high 16 bits are
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* not 0.
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*
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* The aperture sizes are still 4GB implicitly.
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*
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* A GPUVM aperture is not applicable on GFXv9.
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*/
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#define MAKE_LDS_APP_BASE_V9() ((uint64_t)(0x1UL) << 48)
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#define MAKE_SCRATCH_APP_BASE_V9() ((uint64_t)(0x2UL) << 48)
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/* User mode manages most of the SVM aperture address space. The low
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* 16MB are reserved for kernel use (CWSR trap handler and kernel IB
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* for now).
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@ -300,6 +312,55 @@
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#define SVM_CWSR_BASE (SVM_USER_BASE - KFD_CWSR_TBA_TMA_SIZE)
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#define SVM_IB_BASE (SVM_CWSR_BASE - PAGE_SIZE)
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static void kfd_init_apertures_vi(struct kfd_process_device *pdd, uint8_t id)
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{
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/*
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* node id couldn't be 0 - the three MSB bits of
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* aperture shoudn't be 0
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*/
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pdd->lds_base = MAKE_LDS_APP_BASE_VI();
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pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base);
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if (!pdd->dev->device_info->needs_iommu_device) {
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/* dGPUs: SVM aperture starting at 0
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* with small reserved space for kernel.
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* Set them to CANONICAL addresses.
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*/
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pdd->gpuvm_base = SVM_USER_BASE;
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pdd->gpuvm_limit =
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pdd->dev->shared_resources.gpuvm_size - 1;
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} else {
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/* set them to non CANONICAL addresses, and no SVM is
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* allocated.
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*/
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pdd->gpuvm_base = MAKE_GPUVM_APP_BASE_VI(id + 1);
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pdd->gpuvm_limit = MAKE_GPUVM_APP_LIMIT(pdd->gpuvm_base,
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pdd->dev->shared_resources.gpuvm_size);
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}
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pdd->scratch_base = MAKE_SCRATCH_APP_BASE_VI();
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pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
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}
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static void kfd_init_apertures_v9(struct kfd_process_device *pdd, uint8_t id)
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{
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pdd->lds_base = MAKE_LDS_APP_BASE_V9();
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pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base);
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/* Raven needs SVM to support graphic handle, etc. Leave the small
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* reserved space before SVM on Raven as well, even though we don't
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* have to.
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* Set gpuvm_base and gpuvm_limit to CANONICAL addresses so that they
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* are used in Thunk to reserve SVM.
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*/
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pdd->gpuvm_base = SVM_USER_BASE;
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pdd->gpuvm_limit =
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pdd->dev->shared_resources.gpuvm_size - 1;
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pdd->scratch_base = MAKE_SCRATCH_APP_BASE_V9();
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pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
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}
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int kfd_init_apertures(struct kfd_process *process)
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{
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uint8_t id = 0;
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@ -316,7 +377,7 @@ int kfd_init_apertures(struct kfd_process *process)
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pdd = kfd_create_process_device_data(dev, process);
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if (!pdd) {
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pr_err("Failed to create process device data\n");
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return -1;
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return -ENOMEM;
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}
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/*
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* For 64 bit process apertures will be statically reserved in
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@ -328,32 +389,30 @@ int kfd_init_apertures(struct kfd_process *process)
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pdd->gpuvm_base = pdd->gpuvm_limit = 0;
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pdd->scratch_base = pdd->scratch_limit = 0;
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} else {
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/* Same LDS and scratch apertures can be used
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* on all GPUs. This allows using more dGPUs
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* than placement options for apertures.
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*/
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pdd->lds_base = MAKE_LDS_APP_BASE();
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pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base);
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switch (dev->device_info->asic_family) {
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case CHIP_KAVERI:
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case CHIP_HAWAII:
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case CHIP_CARRIZO:
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case CHIP_TONGA:
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case CHIP_FIJI:
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case CHIP_POLARIS10:
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case CHIP_POLARIS11:
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kfd_init_apertures_vi(pdd, id);
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break;
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case CHIP_VEGA10:
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case CHIP_RAVEN:
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kfd_init_apertures_v9(pdd, id);
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break;
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default:
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WARN(1, "Unexpected ASIC family %u",
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dev->device_info->asic_family);
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return -EINVAL;
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}
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pdd->scratch_base = MAKE_SCRATCH_APP_BASE();
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pdd->scratch_limit =
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MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
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if (dev->device_info->needs_iommu_device) {
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/* APUs: GPUVM aperture in
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* non-canonical address space
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if (!dev->device_info->needs_iommu_device) {
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/* dGPUs: the reserved space for kernel
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* before SVM
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*/
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pdd->gpuvm_base = MAKE_GPUVM_APP_BASE(id + 1);
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pdd->gpuvm_limit = MAKE_GPUVM_APP_LIMIT(
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pdd->gpuvm_base,
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dev->shared_resources.gpuvm_size);
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} else {
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/* dGPUs: SVM aperture starting at 0
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* with small reserved space for kernel
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*/
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pdd->gpuvm_base = SVM_USER_BASE;
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pdd->gpuvm_limit =
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dev->shared_resources.gpuvm_size - 1;
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pdd->qpd.cwsr_base = SVM_CWSR_BASE;
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pdd->qpd.ib_base = SVM_IB_BASE;
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}
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