Merge branch 'bnx2x-next'
Yuval Mintz says: ==================== bnx2x: update FW, rebrand and more This patch series does several things - it updates the bnx2x FW into 7.12.30 which both contains some small fixes as well as opening the door for several new features for the device - mainly vxlan/geneve offloads and vlan filtering offload. It then adds a new Multi-function mode [BD] which requires this FW in order to operate. In addition, this finally rebrands the driver from a 'broadcom' driver into a 'qlogic' driver [although it would still reside under Broadcom's tree in the kernel]. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Коммит
70c9bb8b92
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@ -1,6 +1,8 @@
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/* bnx2x.h: Broadcom Everest network driver.
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/* bnx2x.h: QLogic Everest network driver.
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*
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* Copyright (c) 2007-2013 Broadcom Corporation
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* Copyright (c) 2014 QLogic Corporation
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -30,7 +32,7 @@
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* (you will need to reboot afterwards) */
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/* #define BNX2X_STOP_ON_ERROR */
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#define DRV_MODULE_VERSION "1.710.51-0"
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#define DRV_MODULE_VERSION "1.712.30-0"
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#define DRV_MODULE_RELDATE "2014/02/10"
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#define BNX2X_BC_VER 0x040200
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@ -1422,6 +1424,7 @@ enum {
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SUB_MF_MODE_UNKNOWN = 0,
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SUB_MF_MODE_UFP,
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SUB_MF_MODE_NPAR1_DOT_5,
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SUB_MF_MODE_BD,
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};
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struct bnx2x {
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@ -1636,6 +1639,8 @@ struct bnx2x {
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u8 mf_sub_mode;
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#define IS_MF_UFP(bp) (IS_MF_SD(bp) && \
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bp->mf_sub_mode == SUB_MF_MODE_UFP)
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#define IS_MF_BD(bp) (IS_MF_SD(bp) && \
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bp->mf_sub_mode == SUB_MF_MODE_BD)
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u8 wol;
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@ -2577,6 +2582,8 @@ void bnx2x_set_local_cmng(struct bnx2x *bp);
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void bnx2x_update_mng_version(struct bnx2x *bp);
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void bnx2x_update_mfw_dump(struct bnx2x *bp);
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#define MCPR_SCRATCH_BASE(bp) \
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(CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
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@ -1,6 +1,8 @@
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/* bnx2x_cmn.c: Broadcom Everest network driver.
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/* bnx2x_cmn.c: QLogic Everest network driver.
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*
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* Copyright (c) 2007-2013 Broadcom Corporation
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* Copyright (c) 2014 QLogic Corporation
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -2103,9 +2105,14 @@ int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
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if (rss_obj->udp_rss_v6)
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__set_bit(BNX2X_RSS_IPV6_UDP, ¶ms.rss_flags);
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if (!CHIP_IS_E1x(bp))
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if (!CHIP_IS_E1x(bp)) {
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/* valid only for TUNN_MODE_VXLAN tunnel mode */
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__set_bit(BNX2X_RSS_IPV4_VXLAN, ¶ms.rss_flags);
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__set_bit(BNX2X_RSS_IPV6_VXLAN, ¶ms.rss_flags);
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/* valid only for TUNN_MODE_GRE tunnel mode */
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__set_bit(BNX2X_RSS_GRE_INNER_HDRS, ¶ms.rss_flags);
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__set_bit(BNX2X_RSS_TUNN_INNER_HDRS, ¶ms.rss_flags);
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}
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} else {
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__set_bit(BNX2X_RSS_MODE_DISABLED, ¶ms.rss_flags);
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}
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@ -2510,6 +2517,20 @@ static void bnx2x_bz_fp(struct bnx2x *bp, int index)
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fp->mode = TPA_MODE_DISABLED;
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}
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void bnx2x_set_os_driver_state(struct bnx2x *bp, u32 state)
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{
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u32 cur;
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if (!IS_MF_BD(bp) || !SHMEM2_HAS(bp, os_driver_state) || IS_VF(bp))
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return;
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cur = SHMEM2_RD(bp, os_driver_state[BP_FW_MB_IDX(bp)]);
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DP(NETIF_MSG_IFUP, "Driver state %08x-->%08x\n",
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cur, state);
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SHMEM2_WR(bp, os_driver_state[BP_FW_MB_IDX(bp)], state);
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}
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int bnx2x_load_cnic(struct bnx2x *bp)
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{
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int i, rc, port = BP_PORT(bp);
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@ -2873,6 +2894,8 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
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/* mark driver is loaded in shmem2 */
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u32 val;
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val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
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val &= ~DRV_FLAGS_MTU_MASK;
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val |= (bp->dev->mtu << DRV_FLAGS_MTU_SHIFT);
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SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
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val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
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DRV_FLAGS_CAPABILITIES_LOADED_L2);
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@ -2885,10 +2908,17 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
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return -EBUSY;
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}
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/* Update driver data for On-Chip MFW dump. */
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if (IS_PF(bp))
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bnx2x_update_mfw_dump(bp);
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/* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */
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if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG))
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bnx2x_dcbx_init(bp, false);
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if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
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bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_ACTIVE);
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DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n");
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return 0;
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@ -2956,6 +2986,9 @@ int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
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DP(NETIF_MSG_IFUP, "Starting NIC unload\n");
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if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
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bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
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/* mark driver is unloaded in shmem2 */
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if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
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u32 val;
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@ -3677,7 +3710,7 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
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pbd2->fw_ip_hdr_to_payload_w =
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hlen_w - ((sizeof(struct ipv6hdr)) >> 1);
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pbd_e2->data.tunnel_data.flags |=
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ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER;
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ETH_TUNNEL_DATA_IPV6_OUTER;
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}
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pbd2->tcp_send_seq = bswab32(inner_tcp_hdr(skb)->seq);
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@ -4184,6 +4217,41 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
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return NETDEV_TX_OK;
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}
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void bnx2x_get_c2s_mapping(struct bnx2x *bp, u8 *c2s_map, u8 *c2s_default)
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{
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int mfw_vn = BP_FW_MB_IDX(bp);
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u32 tmp;
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/* If the shmem shouldn't affect configuration, reflect */
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if (!IS_MF_BD(bp)) {
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int i;
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for (i = 0; i < BNX2X_MAX_PRIORITY; i++)
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c2s_map[i] = i;
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*c2s_default = 0;
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return;
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}
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tmp = SHMEM2_RD(bp, c2s_pcp_map_lower[mfw_vn]);
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tmp = (__force u32)be32_to_cpu((__force __be32)tmp);
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c2s_map[0] = tmp & 0xff;
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c2s_map[1] = (tmp >> 8) & 0xff;
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c2s_map[2] = (tmp >> 16) & 0xff;
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c2s_map[3] = (tmp >> 24) & 0xff;
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tmp = SHMEM2_RD(bp, c2s_pcp_map_upper[mfw_vn]);
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tmp = (__force u32)be32_to_cpu((__force __be32)tmp);
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c2s_map[4] = tmp & 0xff;
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c2s_map[5] = (tmp >> 8) & 0xff;
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c2s_map[6] = (tmp >> 16) & 0xff;
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c2s_map[7] = (tmp >> 24) & 0xff;
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tmp = SHMEM2_RD(bp, c2s_pcp_map_default[mfw_vn]);
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tmp = (__force u32)be32_to_cpu((__force __be32)tmp);
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*c2s_default = (tmp >> (8 * mfw_vn)) & 0xff;
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}
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/**
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* bnx2x_setup_tc - routine to configure net_device for multi tc
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*
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@ -4194,8 +4262,9 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
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*/
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int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)
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{
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int cos, prio, count, offset;
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struct bnx2x *bp = netdev_priv(dev);
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u8 c2s_map[BNX2X_MAX_PRIORITY], c2s_def;
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int cos, prio, count, offset;
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/* setup tc must be called under rtnl lock */
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ASSERT_RTNL();
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@ -4219,12 +4288,16 @@ int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)
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return -EINVAL;
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}
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bnx2x_get_c2s_mapping(bp, c2s_map, &c2s_def);
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/* configure priority to traffic class mapping */
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for (prio = 0; prio < BNX2X_MAX_PRIORITY; prio++) {
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netdev_set_prio_tc_map(dev, prio, bp->prio_to_cos[prio]);
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int outer_prio = c2s_map[prio];
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netdev_set_prio_tc_map(dev, prio, bp->prio_to_cos[outer_prio]);
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DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
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"mapping priority %d to tc %d\n",
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prio, bp->prio_to_cos[prio]);
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outer_prio, bp->prio_to_cos[outer_prio]);
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}
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/* Use this configuration to differentiate tc0 from other COSes
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@ -4278,6 +4351,9 @@ int bnx2x_change_mac_addr(struct net_device *dev, void *p)
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if (netif_running(dev))
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rc = bnx2x_set_eth_mac(bp, true);
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if (IS_PF(bp) && SHMEM2_HAS(bp, curr_cfg))
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SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
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return rc;
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}
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@ -4831,6 +4907,9 @@ int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
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*/
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dev->mtu = new_mtu;
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if (IS_PF(bp) && SHMEM2_HAS(bp, curr_cfg))
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SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
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return bnx2x_reload_if_running(dev);
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}
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@ -1,6 +1,8 @@
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/* bnx2x_cmn.h: Broadcom Everest network driver.
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/* bnx2x_cmn.h: QLogic Everest network driver.
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*
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* Copyright (c) 2007-2013 Broadcom Corporation
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* Copyright (c) 2014 QLogic Corporation
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* All rights reserved
|
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*
|
||||
* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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|
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@ -620,6 +622,14 @@ int bnx2x_set_features(struct net_device *dev, netdev_features_t features);
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*/
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void bnx2x_tx_timeout(struct net_device *dev);
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/** bnx2x_get_c2s_mapping - read inner-to-outer vlan configuration
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* c2s_map should have BNX2X_MAX_PRIORITY entries.
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* @bp: driver handle
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* @c2s_map: should have BNX2X_MAX_PRIORITY entries for mapping
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* @c2s_default: entry for non-tagged configuration
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*/
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void bnx2x_get_c2s_mapping(struct bnx2x *bp, u8 *c2s_map, u8 *c2s_default);
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/*********************** Inlines **********************************/
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/*********************** Fast path ********************************/
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static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
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@ -931,14 +941,33 @@ static inline int bnx2x_func_start(struct bnx2x *bp)
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start_params->mf_mode = bp->mf_mode;
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start_params->sd_vlan_tag = bp->mf_ov;
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/* Configure Ethertype for BD mode */
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if (IS_MF_BD(bp)) {
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DP(NETIF_MSG_IFUP, "Configuring ethertype 0x88a8 for BD\n");
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start_params->sd_vlan_eth_type = ETH_P_8021AD;
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REG_WR(bp, PRS_REG_VLAN_TYPE_0, ETH_P_8021AD);
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REG_WR(bp, PBF_REG_VLAN_TYPE_0, ETH_P_8021AD);
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REG_WR(bp, NIG_REG_LLH_E1HOV_TYPE_1, ETH_P_8021AD);
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|
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bnx2x_get_c2s_mapping(bp, start_params->c2s_pri,
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&start_params->c2s_pri_default);
|
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start_params->c2s_pri_valid = 1;
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|
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DP(NETIF_MSG_IFUP,
|
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"Inner-to-Outer priority: %02x %02x %02x %02x %02x %02x %02x %02x [Default %02x]\n",
|
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start_params->c2s_pri[0], start_params->c2s_pri[1],
|
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start_params->c2s_pri[2], start_params->c2s_pri[3],
|
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start_params->c2s_pri[4], start_params->c2s_pri[5],
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start_params->c2s_pri[6], start_params->c2s_pri[7],
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start_params->c2s_pri_default);
|
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}
|
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|
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if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
|
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start_params->network_cos_mode = STATIC_COS;
|
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else /* CHIP_IS_E1X */
|
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start_params->network_cos_mode = FW_WRR;
|
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|
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start_params->tunnel_mode = TUNN_MODE_GRE;
|
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start_params->gre_tunnel_type = IPGRE_TUNNEL;
|
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start_params->inner_gre_rss_en = 1;
|
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start_params->inner_rss = 1;
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|
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if (IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
|
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start_params->class_fail_ethtype = ETH_P_FIP;
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@ -1339,4 +1368,11 @@ void bnx2x_squeeze_objects(struct bnx2x *bp);
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void bnx2x_schedule_sp_rtnl(struct bnx2x*, enum sp_rtnl_flag,
|
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u32 verbose);
|
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|
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/**
|
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* bnx2x_set_os_driver_state - write driver state for management FW usage
|
||||
*
|
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* @bp: driver handle
|
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* @state: OS_DRIVER_STATE_* value reflecting current driver state
|
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*/
|
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void bnx2x_set_os_driver_state(struct bnx2x *bp, u32 state);
|
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#endif /* BNX2X_CMN_H */
|
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|
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@ -1,15 +1,17 @@
|
|||
/* bnx2x_dcb.c: Broadcom Everest network driver.
|
||||
/* bnx2x_dcb.c: QLogic Everest network driver.
|
||||
*
|
||||
* Copyright 2009-2013 Broadcom Corporation
|
||||
* Copyright 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* Unless you and QLogic execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available
|
||||
* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* software in any way with any other QLogic software provided under a
|
||||
* license other than the GPL, without QLogic's express prior written
|
||||
* consent.
|
||||
*
|
||||
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
|
||||
|
|
@ -1850,6 +1852,8 @@ static void bnx2x_dcbx_fw_struct(struct bnx2x *bp,
|
|||
if (bp->dcbx_port_params.ets.cos_params[cos].
|
||||
pri_bitmask & pri_bit)
|
||||
tt2cos[pri].cos = cos;
|
||||
|
||||
pfc_fw_cfg->dcb_outer_pri[pri] = ttp[pri];
|
||||
}
|
||||
|
||||
/* we never want the FW to add a 0 vlan tag */
|
||||
|
|
|
|||
|
|
@ -1,15 +1,17 @@
|
|||
/* bnx2x_dcb.h: Broadcom Everest network driver.
|
||||
/* bnx2x_dcb.h: QLogic Everest network driver.
|
||||
*
|
||||
* Copyright 2009-2013 Broadcom Corporation
|
||||
* Copyright 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* Unless you and QLogic execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available
|
||||
* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* software in any way with any other QLogic software provided under a
|
||||
* license other than the GPL, without QLogic's express prior written
|
||||
* consent.
|
||||
*
|
||||
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
|
||||
|
|
|
|||
|
|
@ -1,15 +1,17 @@
|
|||
/* bnx2x_dump.h: Broadcom Everest network driver.
|
||||
/* bnx2x_dump.h: QLogic Everest network driver.
|
||||
*
|
||||
* Copyright (c) 2012-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* Unless you and QLogic execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available
|
||||
* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* software in any way with any other QLogic software provided under a
|
||||
* license other than the GPL, without QLogic's express prior written
|
||||
* consent.
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/* bnx2x_ethtool.c: Broadcom Everest network driver.
|
||||
/* bnx2x_ethtool.c: QLogic Everest network driver.
|
||||
*
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -1129,6 +1131,9 @@ static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
|
|||
} else
|
||||
bp->wol = 0;
|
||||
|
||||
if (SHMEM2_HAS(bp, curr_cfg))
|
||||
SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/* bnx2x_fw_defs.h: Broadcom Everest network driver.
|
||||
/* bnx2x_fw_defs.h: Qlogic Everest network driver.
|
||||
*
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -372,7 +374,7 @@
|
|||
#define MAX_COS_NUMBER 4
|
||||
#define MAX_TRAFFIC_TYPES 8
|
||||
#define MAX_PFC_PRIORITIES 8
|
||||
|
||||
#define MAX_VLAN_PRIORITIES 8
|
||||
/* used by array traffic_type_to_priority[] to mark traffic type \
|
||||
that is not mapped to priority*/
|
||||
#define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/* bnx2x_fw_file_hdr.h: FW binary file header structure.
|
||||
*
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/* bnx2x_hsi.h: Broadcom Everest network driver.
|
||||
/* bnx2x_hsi.h: Qlogic Everest network driver.
|
||||
*
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -729,6 +731,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
|
|||
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
|
||||
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
|
||||
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100
|
||||
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84858 0x00001200
|
||||
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
|
||||
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
|
||||
|
||||
|
|
@ -786,6 +789,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
|
|||
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
|
||||
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
|
||||
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100
|
||||
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858 0x00001200
|
||||
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
|
||||
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
|
||||
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
|
||||
|
|
@ -864,6 +868,7 @@ struct shared_feat_cfg { /* NVRAM Offset */
|
|||
#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
|
||||
#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
|
||||
#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
|
||||
#define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500
|
||||
#define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600
|
||||
#define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700
|
||||
|
||||
|
|
@ -2064,6 +2069,26 @@ struct ncsi_oem_fcoe_features {
|
|||
#define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
|
||||
};
|
||||
|
||||
enum curr_cfg_method_e {
|
||||
CURR_CFG_MET_NONE = 0, /* default config */
|
||||
CURR_CFG_MET_OS = 1,
|
||||
CURR_CFG_MET_VENDOR_SPEC = 2,/* e.g. Option ROM, NPAR, O/S Cfg Utils */
|
||||
};
|
||||
|
||||
struct mdump_driver_info {
|
||||
u32 epoc;
|
||||
u32 drv_ver;
|
||||
u32 fw_ver;
|
||||
|
||||
u32 valid_dump;
|
||||
#define FIRST_DUMP_VALID (1 << 0)
|
||||
#define SECOND_DUMP_VALID (1 << 1)
|
||||
|
||||
u32 flags;
|
||||
#define ENABLE_ALL_TRIGGERS (0x7fffffff)
|
||||
#define TRIGGER_MDUMP_ONCE (1 << 31)
|
||||
};
|
||||
|
||||
struct ncsi_oem_data {
|
||||
u32 driver_version[4];
|
||||
struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
|
||||
|
|
@ -2187,6 +2212,8 @@ struct shmem2_region {
|
|||
#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
|
||||
#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
|
||||
#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
|
||||
#define DRV_FLAGS_MTU_MASK 0xffff0000
|
||||
#define DRV_FLAGS_MTU_SHIFT 16
|
||||
|
||||
u32 extended_dev_info_shared_cfg_size;
|
||||
|
||||
|
|
@ -2251,6 +2278,7 @@ struct shmem2_region {
|
|||
u32 reserved4; /* Offset 0x150 */
|
||||
u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */
|
||||
#define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
|
||||
#define LINK_ATTR_84858 0x00000002
|
||||
#define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
|
||||
#define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
|
||||
#define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000
|
||||
|
|
@ -2268,6 +2296,74 @@ struct shmem2_region {
|
|||
|
||||
/* We use indication for each PF (0..3) */
|
||||
#define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))
|
||||
union { /* For various OEMs */ /* Offset 0x1a0 */
|
||||
u8 storage_boot_prog[E2_FUNC_MAX];
|
||||
#define STORAGE_BOOT_PROG_MASK 0x000000FF
|
||||
#define STORAGE_BOOT_PROG_NONE 0x00000000
|
||||
#define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002
|
||||
#define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002
|
||||
#define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004
|
||||
#define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008
|
||||
#define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008
|
||||
#define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010
|
||||
#define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020
|
||||
#define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040
|
||||
#define STORAGE_BOOT_PROG_COMPLETED 0x00000080
|
||||
|
||||
u32 oem_i2c_data_addr;
|
||||
};
|
||||
|
||||
/* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
|
||||
/* For PCP values 0-3 use the map lower */
|
||||
/* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
|
||||
* 0x0000FF00 - PCP 2, 0x000000FF PCP 3
|
||||
*/
|
||||
u32 c2s_pcp_map_lower[E2_FUNC_MAX]; /* 0x1a4 */
|
||||
|
||||
/* For PCP values 4-7 use the map upper */
|
||||
/* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
|
||||
* 0x0000FF00 - PCP 6, 0x000000FF PCP 7
|
||||
*/
|
||||
u32 c2s_pcp_map_upper[E2_FUNC_MAX]; /* 0x1b4 */
|
||||
|
||||
/* For PCP default value get the MSB byte of the map default */
|
||||
u32 c2s_pcp_map_default[E2_FUNC_MAX]; /* 0x1c4 */
|
||||
|
||||
/* FC_NPIV table offset in NVRAM */
|
||||
u32 fc_npiv_nvram_tbl_addr[PORT_MAX]; /* 0x1d4 */
|
||||
|
||||
/* Shows last method that changed configuration of this device */
|
||||
enum curr_cfg_method_e curr_cfg; /* 0x1dc */
|
||||
|
||||
/* Storm FW version, shold be kept in the format 0xMMmmbbdd:
|
||||
* MM - Major, mm - Minor, bb - Build ,dd - Drop
|
||||
*/
|
||||
u32 netproc_fw_ver; /* 0x1e0 */
|
||||
|
||||
/* Option ROM SMASH CLP version */
|
||||
u32 clp_ver; /* 0x1e4 */
|
||||
|
||||
u32 pcie_bus_num; /* 0x1e8 */
|
||||
|
||||
u32 sriov_switch_mode; /* 0x1ec */
|
||||
#define SRIOV_SWITCH_MODE_NONE 0x0
|
||||
#define SRIOV_SWITCH_MODE_VEB 0x1
|
||||
#define SRIOV_SWITCH_MODE_VEPA 0x2
|
||||
|
||||
u8 rsrv2[E2_FUNC_MAX]; /* 0x1f0 */
|
||||
|
||||
u32 img_inv_table_addr; /* Address to INV_TABLE_P */ /* 0x1f4 */
|
||||
|
||||
u32 mtu_size[E2_FUNC_MAX]; /* 0x1f8 */
|
||||
|
||||
u32 os_driver_state[E2_FUNC_MAX]; /* 0x208 */
|
||||
#define OS_DRIVER_STATE_NOT_LOADED 0 /* not installed */
|
||||
#define OS_DRIVER_STATE_LOADING 1 /* transition state */
|
||||
#define OS_DRIVER_STATE_DISABLED 2 /* installed but disabled */
|
||||
#define OS_DRIVER_STATE_ACTIVE 3 /* installed and active */
|
||||
|
||||
/* mini dump driver info */
|
||||
struct mdump_driver_info drv_info; /* 0x218 */
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -2898,8 +2994,8 @@ struct afex_stats {
|
|||
};
|
||||
|
||||
#define BCM_5710_FW_MAJOR_VERSION 7
|
||||
#define BCM_5710_FW_MINOR_VERSION 10
|
||||
#define BCM_5710_FW_REVISION_VERSION 51
|
||||
#define BCM_5710_FW_MINOR_VERSION 12
|
||||
#define BCM_5710_FW_REVISION_VERSION 30
|
||||
#define BCM_5710_FW_ENGINEERING_VERSION 0
|
||||
#define BCM_5710_FW_COMPILE_FLAGS 1
|
||||
|
||||
|
|
@ -3901,7 +3997,11 @@ struct eth_fast_path_rx_cqe {
|
|||
__le16 len_on_bd;
|
||||
struct parsing_flags pars_flags;
|
||||
union eth_sgl_or_raw_data sgl_or_raw_data;
|
||||
__le32 reserved1[7];
|
||||
u8 tunn_type;
|
||||
u8 tunn_inner_hdrs_offset;
|
||||
__le16 reserved1;
|
||||
__le32 tunn_tenant_id;
|
||||
__le32 padding[5];
|
||||
u32 marker;
|
||||
};
|
||||
|
||||
|
|
@ -4012,8 +4112,8 @@ struct eth_tunnel_data {
|
|||
__le16 pseudo_csum;
|
||||
u8 ip_hdr_start_inner_w;
|
||||
u8 flags;
|
||||
#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0)
|
||||
#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
|
||||
#define ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0)
|
||||
#define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0
|
||||
#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)
|
||||
#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
|
||||
};
|
||||
|
|
@ -4120,16 +4220,12 @@ struct eth_rss_update_ramrod_data {
|
|||
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<8)
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 8
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY (0x1<<9)
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY_SHIFT 9
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY (0x1<<10)
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY_SHIFT 10
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<11)
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 11
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0xF<<12)
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 12
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8)
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9)
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10)
|
||||
#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10
|
||||
u8 rss_result_mask;
|
||||
u8 reserved3;
|
||||
__le16 reserved4;
|
||||
|
|
@ -4314,6 +4410,18 @@ enum eth_tunnel_non_lso_csum_location {
|
|||
MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION
|
||||
};
|
||||
|
||||
enum eth_tunn_type {
|
||||
TUNN_TYPE_NONE,
|
||||
TUNN_TYPE_VXLAN,
|
||||
TUNN_TYPE_L2_GRE,
|
||||
TUNN_TYPE_IPV4_GRE,
|
||||
TUNN_TYPE_IPV6_GRE,
|
||||
TUNN_TYPE_L2_GENEVE,
|
||||
TUNN_TYPE_IPV4_GENEVE,
|
||||
TUNN_TYPE_IPV6_GENEVE,
|
||||
MAX_ETH_TUNN_TYPE
|
||||
};
|
||||
|
||||
/*
|
||||
* Tx regular BD structure
|
||||
*/
|
||||
|
|
@ -4758,6 +4866,9 @@ struct afex_vif_list_ramrod_data {
|
|||
__le16 reserved1;
|
||||
};
|
||||
|
||||
struct c2s_pri_trans_table_entry {
|
||||
u8 val[MAX_VLAN_PRIORITIES];
|
||||
};
|
||||
|
||||
/*
|
||||
* cfc delete event data
|
||||
|
|
@ -5246,6 +5357,7 @@ struct flow_control_configuration {
|
|||
u8 dont_add_pri_0_en;
|
||||
u8 reserved1;
|
||||
__le32 reserved2;
|
||||
u8 dcb_outer_pri[MAX_TRAFFIC_TYPES];
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -5260,18 +5372,25 @@ struct function_start_data {
|
|||
u8 path_id;
|
||||
u8 network_cos_mode;
|
||||
u8 dmae_cmd_id;
|
||||
u8 tunnel_mode;
|
||||
u8 gre_tunnel_type;
|
||||
u8 tunn_clss_en;
|
||||
u8 inner_gre_rss_en;
|
||||
u8 sd_accept_mf_clss_fail;
|
||||
u8 no_added_tags;
|
||||
__le16 reserved0;
|
||||
__le32 reserved1;
|
||||
u8 inner_clss_vxlan;
|
||||
u8 inner_clss_l2gre;
|
||||
u8 inner_clss_l2geneve;
|
||||
u8 inner_rss;
|
||||
__le16 vxlan_dst_port;
|
||||
__le16 geneve_dst_port;
|
||||
u8 sd_accept_mf_clss_fail;
|
||||
u8 sd_accept_mf_clss_fail_match_ethtype;
|
||||
__le16 sd_accept_mf_clss_fail_ethtype;
|
||||
__le16 sd_vlan_eth_type;
|
||||
u8 sd_vlan_force_pri_flg;
|
||||
u8 sd_vlan_force_pri_val;
|
||||
u8 sd_accept_mf_clss_fail_match_ethtype;
|
||||
u8 no_added_tags;
|
||||
u8 c2s_pri_tt_valid;
|
||||
u8 c2s_pri_default;
|
||||
u8 reserved2[6];
|
||||
struct c2s_pri_trans_table_entry c2s_pri_trans_table;
|
||||
};
|
||||
|
||||
struct function_update_data {
|
||||
|
|
@ -5289,11 +5408,12 @@ struct function_update_data {
|
|||
u8 tx_switch_suspend;
|
||||
u8 echo;
|
||||
u8 update_tunn_cfg_flg;
|
||||
u8 tunnel_mode;
|
||||
u8 gre_tunnel_type;
|
||||
u8 tunn_clss_en;
|
||||
u8 inner_gre_rss_en;
|
||||
u8 inner_clss_vxlan;
|
||||
u8 inner_clss_l2gre;
|
||||
u8 inner_clss_l2geneve;
|
||||
u8 inner_rss;
|
||||
__le16 vxlan_dst_port;
|
||||
__le16 geneve_dst_port;
|
||||
u8 sd_vlan_force_pri_change_flg;
|
||||
u8 sd_vlan_force_pri_flg;
|
||||
u8 sd_vlan_force_pri_val;
|
||||
|
|
@ -5302,6 +5422,8 @@ struct function_update_data {
|
|||
u8 reserved1;
|
||||
__le16 sd_vlan_tag;
|
||||
__le16 sd_vlan_eth_type;
|
||||
__le16 reserved0;
|
||||
__le32 reserved2;
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -5330,15 +5452,6 @@ struct fw_version {
|
|||
#define __FW_VERSION_RESERVED_SHIFT 4
|
||||
};
|
||||
|
||||
|
||||
/* GRE Tunnel Mode */
|
||||
enum gre_tunnel_type {
|
||||
NVGRE_TUNNEL,
|
||||
L2GRE_TUNNEL,
|
||||
IPGRE_TUNNEL,
|
||||
MAX_GRE_TUNNEL_TYPE
|
||||
};
|
||||
|
||||
/*
|
||||
* Dynamic Host-Coalescing - Driver(host) counters
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
/* bnx2x_init.h: Broadcom Everest network driver.
|
||||
/* bnx2x_init.h: Qlogic Everest network driver.
|
||||
* Structures and macroes needed during the initialization.
|
||||
*
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
All rights reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
|
|||
|
|
@ -1,8 +1,10 @@
|
|||
/* bnx2x_init_ops.h: Broadcom Everest network driver.
|
||||
/* bnx2x_init_ops.h: Qlogic Everest network driver.
|
||||
* Static functions needed during the initialization.
|
||||
* This file is "included" in bnx2x_main.c.
|
||||
*
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
All rights reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
|
|||
|
|
@ -1,13 +1,15 @@
|
|||
/* Copyright 2008-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* Unless you and QLogic execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available
|
||||
* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
|
||||
* at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* software in any way with any other Qlogic software provided under a
|
||||
* license other than the GPL, without Qlogic's express prior written
|
||||
* consent.
|
||||
*
|
||||
* Written by Yaniv Rosner
|
||||
|
|
@ -9652,6 +9654,13 @@ static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
|
|||
/******************************************************************/
|
||||
/* BCM8481/BCM84823/BCM84833 PHY SECTION */
|
||||
/******************************************************************/
|
||||
static int bnx2x_is_8483x_8485x(struct bnx2x_phy *phy)
|
||||
{
|
||||
return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
|
||||
(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) ||
|
||||
(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858));
|
||||
}
|
||||
|
||||
static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
|
||||
struct bnx2x *bp,
|
||||
u8 port)
|
||||
|
|
@ -9666,8 +9675,7 @@ static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
|
|||
};
|
||||
u16 fw_ver1;
|
||||
|
||||
if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
|
||||
(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
|
||||
if (bnx2x_is_8483x_8485x(phy)) {
|
||||
bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
|
||||
bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
|
||||
phy->ver_addr);
|
||||
|
|
@ -9749,8 +9757,7 @@ static void bnx2x_848xx_set_led(struct bnx2x *bp,
|
|||
bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
|
||||
reg_set[i].val);
|
||||
|
||||
if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
|
||||
(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
|
||||
if (bnx2x_is_8483x_8485x(phy))
|
||||
offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
|
||||
else
|
||||
offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
|
||||
|
|
@ -9768,8 +9775,7 @@ static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
|
|||
struct bnx2x *bp = params->bp;
|
||||
switch (action) {
|
||||
case PHY_INIT:
|
||||
if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
|
||||
(phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
|
||||
if (!bnx2x_is_8483x_8485x(phy)) {
|
||||
/* Save spirom version */
|
||||
bnx2x_save_848xx_spirom_version(phy, bp, params->port);
|
||||
}
|
||||
|
|
@ -9901,8 +9907,7 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
|
|||
/* Always write this if this is not 84833/4.
|
||||
* For 84833/4, write it only when it's a forced speed.
|
||||
*/
|
||||
if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
|
||||
(phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
|
||||
if (!bnx2x_is_8483x_8485x(phy) ||
|
||||
((autoneg_val & (1<<12)) == 0))
|
||||
bnx2x_cl45_write(bp, phy,
|
||||
MDIO_AN_DEVAD,
|
||||
|
|
@ -9949,8 +9954,86 @@ static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
|
|||
return bnx2x_848xx_cmn_config_init(phy, params, vars);
|
||||
}
|
||||
|
||||
#define PHY84833_CMDHDLR_WAIT 300
|
||||
#define PHY84833_CMDHDLR_MAX_ARGS 5
|
||||
#define PHY848xx_CMDHDLR_WAIT 300
|
||||
#define PHY848xx_CMDHDLR_MAX_ARGS 5
|
||||
|
||||
static int bnx2x_84858_cmd_hdlr(struct bnx2x_phy *phy,
|
||||
struct link_params *params,
|
||||
u16 fw_cmd,
|
||||
u16 cmd_args[], int argc)
|
||||
{
|
||||
int idx;
|
||||
u16 val;
|
||||
struct bnx2x *bp = params->bp;
|
||||
|
||||
/* Step 1: Poll the STATUS register to see whether the previous command
|
||||
* is in progress or the system is busy (CMD_IN_PROGRESS or
|
||||
* SYSTEM_BUSY). If previous command is in progress or system is busy,
|
||||
* check again until the previous command finishes execution and the
|
||||
* system is available for taking command
|
||||
*/
|
||||
|
||||
for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
|
||||
bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
|
||||
MDIO_848xx_CMD_HDLR_STATUS, &val);
|
||||
if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) &&
|
||||
(val != PHY84858_STATUS_CMD_SYSTEM_BUSY))
|
||||
break;
|
||||
usleep_range(1000, 2000);
|
||||
}
|
||||
if (idx >= PHY848xx_CMDHDLR_WAIT) {
|
||||
DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Step2: If any parameters are required for the function, write them
|
||||
* to the required DATA registers
|
||||
*/
|
||||
|
||||
for (idx = 0; idx < argc; idx++) {
|
||||
bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
|
||||
MDIO_848xx_CMD_HDLR_DATA1 + idx,
|
||||
cmd_args[idx]);
|
||||
}
|
||||
|
||||
/* Step3: When the firmware is ready for commands, write the 'Command
|
||||
* code' to the CMD register
|
||||
*/
|
||||
bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
|
||||
MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
|
||||
|
||||
/* Step4: Once the command has been written, poll the STATUS register
|
||||
* to check whether the command has completed (CMD_COMPLETED_PASS/
|
||||
* CMD_FOR_CMDS or CMD_COMPLETED_ERROR).
|
||||
*/
|
||||
|
||||
for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
|
||||
bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
|
||||
MDIO_848xx_CMD_HDLR_STATUS, &val);
|
||||
if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) ||
|
||||
(val == PHY84858_STATUS_CMD_COMPLETE_ERROR))
|
||||
break;
|
||||
usleep_range(1000, 2000);
|
||||
}
|
||||
if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
|
||||
(val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) {
|
||||
DP(NETIF_MSG_LINK, "FW cmd failed.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
/* Step5: Once the command has completed, read the specficied DATA
|
||||
* registers for any saved results for the command, if applicable
|
||||
*/
|
||||
|
||||
/* Gather returning data */
|
||||
for (idx = 0; idx < argc; idx++) {
|
||||
bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
|
||||
MDIO_848xx_CMD_HDLR_DATA1 + idx,
|
||||
&cmd_args[idx]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
|
||||
struct link_params *params, u16 fw_cmd,
|
||||
u16 cmd_args[], int argc)
|
||||
|
|
@ -9960,16 +10043,16 @@ static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
|
|||
struct bnx2x *bp = params->bp;
|
||||
/* Write CMD_OPEN_OVERRIDE to STATUS reg */
|
||||
bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
|
||||
MDIO_84833_CMD_HDLR_STATUS,
|
||||
MDIO_848xx_CMD_HDLR_STATUS,
|
||||
PHY84833_STATUS_CMD_OPEN_OVERRIDE);
|
||||
for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
|
||||
for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
|
||||
bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
|
||||
MDIO_84833_CMD_HDLR_STATUS, &val);
|
||||
MDIO_848xx_CMD_HDLR_STATUS, &val);
|
||||
if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
|
||||
break;
|
||||
usleep_range(1000, 2000);
|
||||
}
|
||||
if (idx >= PHY84833_CMDHDLR_WAIT) {
|
||||
if (idx >= PHY848xx_CMDHDLR_WAIT) {
|
||||
DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -9977,20 +10060,20 @@ static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
|
|||
/* Prepare argument(s) and issue command */
|
||||
for (idx = 0; idx < argc; idx++) {
|
||||
bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
|
||||
MDIO_84833_CMD_HDLR_DATA1 + idx,
|
||||
MDIO_848xx_CMD_HDLR_DATA1 + idx,
|
||||
cmd_args[idx]);
|
||||
}
|
||||
bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
|
||||
MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
|
||||
for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
|
||||
MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
|
||||
for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
|
||||
bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
|
||||
MDIO_84833_CMD_HDLR_STATUS, &val);
|
||||
MDIO_848xx_CMD_HDLR_STATUS, &val);
|
||||
if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
|
||||
(val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
|
||||
break;
|
||||
usleep_range(1000, 2000);
|
||||
}
|
||||
if ((idx >= PHY84833_CMDHDLR_WAIT) ||
|
||||
if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
|
||||
(val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
|
||||
DP(NETIF_MSG_LINK, "FW cmd failed.\n");
|
||||
return -EINVAL;
|
||||
|
|
@ -9998,21 +10081,41 @@ static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
|
|||
/* Gather returning data */
|
||||
for (idx = 0; idx < argc; idx++) {
|
||||
bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
|
||||
MDIO_84833_CMD_HDLR_DATA1 + idx,
|
||||
MDIO_848xx_CMD_HDLR_DATA1 + idx,
|
||||
&cmd_args[idx]);
|
||||
}
|
||||
bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
|
||||
MDIO_84833_CMD_HDLR_STATUS,
|
||||
MDIO_848xx_CMD_HDLR_STATUS,
|
||||
PHY84833_STATUS_CMD_CLEAR_COMPLETE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
|
||||
static int bnx2x_848xx_cmd_hdlr(struct bnx2x_phy *phy,
|
||||
struct link_params *params,
|
||||
u16 fw_cmd,
|
||||
u16 cmd_args[], int argc)
|
||||
{
|
||||
struct bnx2x *bp = params->bp;
|
||||
|
||||
if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) ||
|
||||
(REG_RD(bp, params->shmem2_base +
|
||||
offsetof(struct shmem2_region,
|
||||
link_attr_sync[params->port])) &
|
||||
LINK_ATTR_84858)) {
|
||||
return bnx2x_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,
|
||||
argc);
|
||||
} else {
|
||||
return bnx2x_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,
|
||||
argc);
|
||||
}
|
||||
}
|
||||
|
||||
static int bnx2x_848xx_pair_swap_cfg(struct bnx2x_phy *phy,
|
||||
struct link_params *params,
|
||||
struct link_vars *vars)
|
||||
{
|
||||
u32 pair_swap;
|
||||
u16 data[PHY84833_CMDHDLR_MAX_ARGS];
|
||||
u16 data[PHY848xx_CMDHDLR_MAX_ARGS];
|
||||
int status;
|
||||
struct bnx2x *bp = params->bp;
|
||||
|
||||
|
|
@ -10028,8 +10131,9 @@ static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
|
|||
/* Only the second argument is used for this command */
|
||||
data[1] = (u16)pair_swap;
|
||||
|
||||
status = bnx2x_84833_cmd_hdlr(phy, params,
|
||||
PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
|
||||
status = bnx2x_848xx_cmd_hdlr(phy, params,
|
||||
PHY848xx_CMD_SET_PAIR_SWAP, data,
|
||||
PHY848xx_CMDHDLR_MAX_ARGS);
|
||||
if (status == 0)
|
||||
DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
|
||||
|
||||
|
|
@ -10118,8 +10222,8 @@ static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
|
|||
DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
|
||||
|
||||
/* Prevent Phy from working in EEE and advertising it */
|
||||
rc = bnx2x_84833_cmd_hdlr(phy, params,
|
||||
PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
|
||||
rc = bnx2x_848xx_cmd_hdlr(phy, params,
|
||||
PHY848xx_CMD_SET_EEE_MODE, &cmd_args, 1);
|
||||
if (rc) {
|
||||
DP(NETIF_MSG_LINK, "EEE disable failed.\n");
|
||||
return rc;
|
||||
|
|
@ -10136,8 +10240,8 @@ static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
|
|||
struct bnx2x *bp = params->bp;
|
||||
u16 cmd_args = 1;
|
||||
|
||||
rc = bnx2x_84833_cmd_hdlr(phy, params,
|
||||
PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
|
||||
rc = bnx2x_848xx_cmd_hdlr(phy, params,
|
||||
PHY848xx_CMD_SET_EEE_MODE, &cmd_args, 1);
|
||||
if (rc) {
|
||||
DP(NETIF_MSG_LINK, "EEE enable failed.\n");
|
||||
return rc;
|
||||
|
|
@ -10155,7 +10259,7 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
|
|||
u8 port, initialize = 1;
|
||||
u16 val;
|
||||
u32 actual_phy_selection;
|
||||
u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
|
||||
u16 cmd_args[PHY848xx_CMDHDLR_MAX_ARGS];
|
||||
int rc = 0;
|
||||
|
||||
usleep_range(1000, 2000);
|
||||
|
|
@ -10180,8 +10284,7 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
|
|||
|
||||
/* Wait for GPHY to come out of reset */
|
||||
msleep(50);
|
||||
if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
|
||||
(phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
|
||||
if (!bnx2x_is_8483x_8485x(phy)) {
|
||||
/* BCM84823 requires that XGXS links up first @ 10G for normal
|
||||
* behavior.
|
||||
*/
|
||||
|
|
@ -10192,7 +10295,19 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
|
|||
bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars);
|
||||
vars->line_speed = temp;
|
||||
}
|
||||
/* Check if this is actually BCM84858 */
|
||||
if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
|
||||
u16 hw_rev;
|
||||
|
||||
bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
|
||||
MDIO_AN_REG_848xx_ID_MSB, &hw_rev);
|
||||
if (hw_rev == BCM84858_PHY_ID) {
|
||||
params->link_attr_sync |= LINK_ATTR_84858;
|
||||
bnx2x_update_link_attr(params, params->link_attr_sync);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set dual-media configuration according to configuration */
|
||||
bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
|
||||
MDIO_CTL_REG_84823_MEDIA, &val);
|
||||
val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
|
||||
|
|
@ -10237,18 +10352,17 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
|
|||
DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
|
||||
params->multi_phy_config, val);
|
||||
|
||||
if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
|
||||
(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
|
||||
bnx2x_84833_pair_swap_cfg(phy, params, vars);
|
||||
if (bnx2x_is_8483x_8485x(phy)) {
|
||||
bnx2x_848xx_pair_swap_cfg(phy, params, vars);
|
||||
|
||||
/* Keep AutogrEEEn disabled. */
|
||||
cmd_args[0] = 0x0;
|
||||
cmd_args[1] = 0x0;
|
||||
cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
|
||||
cmd_args[3] = PHY84833_CONSTANT_LATENCY;
|
||||
rc = bnx2x_84833_cmd_hdlr(phy, params,
|
||||
PHY84833_CMD_SET_EEE_MODE, cmd_args,
|
||||
PHY84833_CMDHDLR_MAX_ARGS);
|
||||
rc = bnx2x_848xx_cmd_hdlr(phy, params,
|
||||
PHY848xx_CMD_SET_EEE_MODE, cmd_args,
|
||||
PHY848xx_CMDHDLR_MAX_ARGS);
|
||||
if (rc)
|
||||
DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
|
||||
}
|
||||
|
|
@ -10302,8 +10416,7 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
|
|||
vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
|
||||
}
|
||||
|
||||
if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
|
||||
(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
|
||||
if (bnx2x_is_8483x_8485x(phy)) {
|
||||
/* Bring PHY out of super isolate mode as the final step. */
|
||||
bnx2x_cl45_read_and_write(bp, phy,
|
||||
MDIO_CTL_DEVAD,
|
||||
|
|
@ -10435,8 +10548,7 @@ static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
|
|||
LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
|
||||
|
||||
/* Determine if EEE was negotiated */
|
||||
if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
|
||||
(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
|
||||
if (bnx2x_is_8483x_8485x(phy))
|
||||
bnx2x_eee_an_resolve(phy, params, vars);
|
||||
}
|
||||
|
||||
|
|
@ -11842,6 +11954,40 @@ static const struct bnx2x_phy phy_84834 = {
|
|||
.phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
|
||||
};
|
||||
|
||||
static const struct bnx2x_phy phy_84858 = {
|
||||
.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858,
|
||||
.addr = 0xff,
|
||||
.def_md_devad = 0,
|
||||
.flags = FLAGS_FAN_FAILURE_DET_REQ |
|
||||
FLAGS_REARM_LATCH_SIGNAL,
|
||||
.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
|
||||
.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
|
||||
.mdio_ctrl = 0,
|
||||
.supported = (SUPPORTED_100baseT_Half |
|
||||
SUPPORTED_100baseT_Full |
|
||||
SUPPORTED_1000baseT_Full |
|
||||
SUPPORTED_10000baseT_Full |
|
||||
SUPPORTED_TP |
|
||||
SUPPORTED_Autoneg |
|
||||
SUPPORTED_Pause |
|
||||
SUPPORTED_Asym_Pause),
|
||||
.media_type = ETH_PHY_BASE_T,
|
||||
.ver_addr = 0,
|
||||
.req_flow_ctrl = 0,
|
||||
.req_line_speed = 0,
|
||||
.speed_cap_mask = 0,
|
||||
.req_duplex = 0,
|
||||
.rsrv = 0,
|
||||
.config_init = (config_init_t)bnx2x_848x3_config_init,
|
||||
.read_status = (read_status_t)bnx2x_848xx_read_status,
|
||||
.link_reset = (link_reset_t)bnx2x_848x3_link_reset,
|
||||
.config_loopback = (config_loopback_t)NULL,
|
||||
.format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
|
||||
.hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
|
||||
.set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
|
||||
.phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
|
||||
};
|
||||
|
||||
static const struct bnx2x_phy phy_54618se = {
|
||||
.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
|
||||
.addr = 0xff,
|
||||
|
|
@ -12128,6 +12274,9 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
|
|||
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
|
||||
*phy = phy_84834;
|
||||
break;
|
||||
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
|
||||
*phy = phy_84858;
|
||||
break;
|
||||
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
|
||||
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
|
||||
*phy = phy_54618se;
|
||||
|
|
@ -12184,9 +12333,7 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
|
|||
}
|
||||
phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
|
||||
|
||||
if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
|
||||
(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
|
||||
(phy->ver_addr)) {
|
||||
if (bnx2x_is_8483x_8485x(phy) && (phy->ver_addr)) {
|
||||
/* Remove 100Mb link supported for BCM84833/4 when phy fw
|
||||
* version lower than or equal to 1.39
|
||||
*/
|
||||
|
|
@ -13281,6 +13428,7 @@ static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
|
|||
break;
|
||||
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
|
||||
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
|
||||
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
|
||||
/* GPIO3's are linked, and so both need to be toggled
|
||||
* to obtain required 2us pulse.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,13 +1,15 @@
|
|||
/* Copyright 2008-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* Unless you and QLogic execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available
|
||||
* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
|
||||
* at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* software in any way with any other Qlogic software provided under a
|
||||
* license other than the GPL, without Qlogic's express prior written
|
||||
* consent.
|
||||
*
|
||||
* Written by Yaniv Rosner
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/* bnx2x_main.c: Broadcom Everest network driver.
|
||||
/* bnx2x_main.c: QLogic Everest network driver.
|
||||
*
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -81,11 +83,11 @@
|
|||
#define TX_TIMEOUT (5*HZ)
|
||||
|
||||
static char version[] =
|
||||
"Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
|
||||
"QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
|
||||
DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
|
||||
|
||||
MODULE_AUTHOR("Eliezer Tamir");
|
||||
MODULE_DESCRIPTION("Broadcom NetXtreme II "
|
||||
MODULE_DESCRIPTION("QLogic "
|
||||
"BCM57710/57711/57711E/"
|
||||
"57712/57712_MF/57800/57800_MF/57810/57810_MF/"
|
||||
"57840/57840_MF Driver");
|
||||
|
|
@ -163,27 +165,27 @@ enum bnx2x_board_type {
|
|||
static struct {
|
||||
char *name;
|
||||
} board_info[] = {
|
||||
[BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
|
||||
[BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
|
||||
[BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
|
||||
[BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
|
||||
[BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
|
||||
[BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
|
||||
[BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
|
||||
[BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
|
||||
[BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
|
||||
[BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
|
||||
[BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
|
||||
[BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
|
||||
[BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
|
||||
[BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
|
||||
[BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
|
||||
[BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
|
||||
[BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
|
||||
[BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
|
||||
[BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
|
||||
[BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
|
||||
[BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
|
||||
[BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
|
||||
[BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" },
|
||||
[BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" },
|
||||
[BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" },
|
||||
[BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
|
||||
[BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
|
||||
[BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" },
|
||||
[BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
|
||||
[BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
|
||||
[BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" },
|
||||
[BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
|
||||
[BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
|
||||
[BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
|
||||
[BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
|
||||
[BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
|
||||
[BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
|
||||
[BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" },
|
||||
[BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
|
||||
[BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
|
||||
[BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
|
||||
[BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
|
||||
};
|
||||
|
||||
#ifndef PCI_DEVICE_ID_NX2_57710
|
||||
|
|
@ -2916,7 +2918,7 @@ static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
|
|||
func_params.f_obj = &bp->func_obj;
|
||||
func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
|
||||
|
||||
if (IS_MF_UFP(bp)) {
|
||||
if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
|
||||
int func = BP_ABS_FUNC(bp);
|
||||
u32 val;
|
||||
|
||||
|
|
@ -2943,16 +2945,16 @@ static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
|
|||
BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
|
||||
bp->mf_ov);
|
||||
goto fail;
|
||||
} else {
|
||||
DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
|
||||
bp->mf_ov);
|
||||
}
|
||||
} else {
|
||||
goto fail;
|
||||
}
|
||||
|
||||
DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov);
|
||||
|
||||
bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* not supported by SW yet */
|
||||
fail:
|
||||
bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
|
||||
}
|
||||
|
|
@ -3707,6 +3709,34 @@ out:
|
|||
ethver, iscsiver, fcoever);
|
||||
}
|
||||
|
||||
void bnx2x_update_mfw_dump(struct bnx2x *bp)
|
||||
{
|
||||
struct timeval epoc;
|
||||
u32 drv_ver;
|
||||
u32 valid_dump;
|
||||
|
||||
if (!SHMEM2_HAS(bp, drv_info))
|
||||
return;
|
||||
|
||||
/* Update Driver load time */
|
||||
do_gettimeofday(&epoc);
|
||||
SHMEM2_WR(bp, drv_info.epoc, epoc.tv_sec);
|
||||
|
||||
drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
|
||||
SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
|
||||
|
||||
SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
|
||||
|
||||
/* Check & notify On-Chip dump. */
|
||||
valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
|
||||
|
||||
if (valid_dump & FIRST_DUMP_VALID)
|
||||
DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
|
||||
|
||||
if (valid_dump & SECOND_DUMP_VALID)
|
||||
DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
|
||||
}
|
||||
|
||||
static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
|
||||
{
|
||||
u32 cmd_ok, cmd_fail;
|
||||
|
|
@ -5568,6 +5598,8 @@ static void bnx2x_eq_int(struct bnx2x *bp)
|
|||
BNX2X_STATE_OPEN):
|
||||
case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
|
||||
BNX2X_STATE_OPENING_WAIT4_PORT):
|
||||
case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
|
||||
BNX2X_STATE_CLOSING_WAIT4_HALT):
|
||||
cid = elem->message.data.eth_event.echo &
|
||||
BNX2X_SWCID_MASK;
|
||||
DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
|
||||
|
|
@ -7429,6 +7461,9 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
|
|||
} else
|
||||
BNX2X_ERR("Bootcode is missing - can not initialize link\n");
|
||||
|
||||
if (SHMEM2_HAS(bp, netproc_fw_ver))
|
||||
SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -11678,7 +11713,7 @@ static void validate_set_si_mode(struct bnx2x *bp)
|
|||
static int bnx2x_get_hwinfo(struct bnx2x *bp)
|
||||
{
|
||||
int /*abs*/func = BP_ABS_FUNC(bp);
|
||||
int vn;
|
||||
int vn, mfw_vn;
|
||||
u32 val = 0, val2 = 0;
|
||||
int rc = 0;
|
||||
|
||||
|
|
@ -11768,6 +11803,7 @@ static int bnx2x_get_hwinfo(struct bnx2x *bp)
|
|||
bp->mf_mode = 0;
|
||||
bp->mf_sub_mode = 0;
|
||||
vn = BP_VN(bp);
|
||||
mfw_vn = BP_FW_MB_IDX(bp);
|
||||
|
||||
if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
|
||||
BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
|
||||
|
|
@ -11824,6 +11860,31 @@ static int bnx2x_get_hwinfo(struct bnx2x *bp)
|
|||
} else
|
||||
BNX2X_DEV_INFO("illegal OV for SD\n");
|
||||
break;
|
||||
case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
|
||||
bp->mf_mode = MULTI_FUNCTION_SD;
|
||||
bp->mf_sub_mode = SUB_MF_MODE_BD;
|
||||
bp->mf_config[vn] =
|
||||
MF_CFG_RD(bp,
|
||||
func_mf_config[func].config);
|
||||
|
||||
if (SHMEM2_HAS(bp, mtu_size)) {
|
||||
int mtu_idx = BP_FW_MB_IDX(bp);
|
||||
u16 mtu_size;
|
||||
u32 mtu;
|
||||
|
||||
mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
|
||||
mtu_size = (u16)mtu;
|
||||
DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
|
||||
mtu_size, mtu);
|
||||
|
||||
/* if valid: update device mtu */
|
||||
if (((mtu_size + ETH_HLEN) >=
|
||||
ETH_MIN_PACKET_SIZE) &&
|
||||
(mtu_size <=
|
||||
ETH_MAX_JUMBO_PACKET_SIZE))
|
||||
bp->dev->mtu = mtu_size;
|
||||
}
|
||||
break;
|
||||
case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
|
||||
bp->mf_mode = MULTI_FUNCTION_SD;
|
||||
bp->mf_sub_mode = SUB_MF_MODE_UFP;
|
||||
|
|
@ -11871,9 +11932,10 @@ static int bnx2x_get_hwinfo(struct bnx2x *bp)
|
|||
|
||||
BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
|
||||
func, bp->mf_ov, bp->mf_ov);
|
||||
} else if (bp->mf_sub_mode == SUB_MF_MODE_UFP) {
|
||||
} else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
|
||||
(bp->mf_sub_mode == SUB_MF_MODE_BD)) {
|
||||
dev_err(&bp->pdev->dev,
|
||||
"Unexpected - no valid MF OV for func %d in UFP mode\n",
|
||||
"Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
|
||||
func);
|
||||
bp->path_has_ovlan = true;
|
||||
} else {
|
||||
|
|
@ -13561,6 +13623,9 @@ static int bnx2x_init_one(struct pci_dev *pdev,
|
|||
|
||||
bnx2x_register_phc(bp);
|
||||
|
||||
if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
|
||||
bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
|
||||
|
||||
return 0;
|
||||
|
||||
init_one_exit:
|
||||
|
|
@ -13623,6 +13688,7 @@ static void __bnx2x_remove(struct pci_dev *pdev,
|
|||
/* Power on: we can't let PCI layer write to us while we are in D3 */
|
||||
if (IS_PF(bp)) {
|
||||
bnx2x_set_power_state(bp, PCI_D0);
|
||||
bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
|
||||
|
||||
/* Set endianity registers to reset values in case next driver
|
||||
* boots in different endianty environment.
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/* bnx2x_mfw_req.h: Broadcom Everest network driver.
|
||||
/* bnx2x_mfw_req.h: Qlogic Everest network driver.
|
||||
*
|
||||
* Copyright (c) 2012-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/* bnx2x_reg.h: Broadcom Everest network driver.
|
||||
/* bnx2x_reg.h: Qlogic Everest network driver.
|
||||
*
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -2137,6 +2139,10 @@
|
|||
/* [RW 1] When this bit is set; the LLH will expect all packets to be with
|
||||
e1hov */
|
||||
#define NIG_REG_LLH_E1HOV_MODE 0x160d8
|
||||
/* [RW 16] Outer VLAN type identifier for multi-function mode. In non
|
||||
* multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
|
||||
*/
|
||||
#define NIG_REG_LLH_E1HOV_TYPE_1 0x16028
|
||||
/* [RW 1] When this bit is set; the LLH will classify the packet before
|
||||
sending it to the BRB or calculating WoL on it. */
|
||||
#define NIG_REG_LLH_MF_MODE 0x16024
|
||||
|
|
@ -2953,7 +2959,12 @@
|
|||
#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
|
||||
/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
|
||||
#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
|
||||
#define PB_REG_CONTROL 0
|
||||
/* [RW 16] One of 8 values that should be compared to type in Ethernet
|
||||
* parsing. If there is a match; the field after Ethernet is the first VLAN.
|
||||
* Reset value is 0x8100 which is the standard VLAN type. Note that when
|
||||
* checking second VLAN; type is compared only to 0x8100.
|
||||
*/
|
||||
#define PBF_REG_VLAN_TYPE_0 0x15c06c
|
||||
/* [RW 2] Interrupt mask register #0 read/write */
|
||||
#define PB_REG_PB_INT_MASK 0x28
|
||||
/* [R 2] Interrupt register #0 read */
|
||||
|
|
@ -3372,6 +3383,12 @@
|
|||
#define PRS_REG_TCM_CURRENT_CREDIT 0x40160
|
||||
/* [R 8] debug only: TSDM current credit. Transaction based. */
|
||||
#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
|
||||
/* [RW 16] One of 8 values that should be compared to type in Ethernet
|
||||
* parsing. If there is a match; the field after Ethernet is the first VLAN.
|
||||
* Reset value is 0x8100 which is the standard VLAN type. Note that when
|
||||
* checking second VLAN; type is compared only to 0x8100.
|
||||
*/
|
||||
#define PRS_REG_VLAN_TYPE_0 0x401a8
|
||||
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
|
||||
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
|
||||
#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
|
||||
|
|
@ -7240,6 +7257,9 @@ Theotherbitsarereservedandshouldbezero*/
|
|||
#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
|
||||
#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
|
||||
#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
|
||||
#define MDIO_AN_REG_848xx_ID_MSB 0xffe2
|
||||
#define BCM84858_PHY_ID 0x600d
|
||||
#define MDIO_AN_REG_848xx_ID_LSB 0xffe3
|
||||
#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
|
||||
#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
|
||||
#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
|
||||
|
|
@ -7283,31 +7303,31 @@ Theotherbitsarereservedandshouldbezero*/
|
|||
#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
|
||||
#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
|
||||
#define MDIO_84833_SUPER_ISOLATE 0x8000
|
||||
/* These are mailbox register set used by 84833. */
|
||||
#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
|
||||
#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
|
||||
#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
|
||||
#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
|
||||
#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
|
||||
#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
|
||||
#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
|
||||
#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
|
||||
#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
|
||||
#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
|
||||
#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
|
||||
#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
|
||||
#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
|
||||
#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
|
||||
#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
|
||||
#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
|
||||
#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
|
||||
#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
|
||||
/* These are mailbox register set used by 84833/84858. */
|
||||
#define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x4005
|
||||
#define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x4006
|
||||
#define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x4007
|
||||
#define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x4008
|
||||
#define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x4009
|
||||
#define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x4037
|
||||
#define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x4038
|
||||
#define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x4039
|
||||
#define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a
|
||||
#define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b
|
||||
#define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c
|
||||
#define MDIO_848xx_CMD_HDLR_COMMAND (MDIO_848xx_TOP_CFG_SCRATCH_REG0)
|
||||
#define MDIO_848xx_CMD_HDLR_STATUS (MDIO_848xx_TOP_CFG_SCRATCH_REG26)
|
||||
#define MDIO_848xx_CMD_HDLR_DATA1 (MDIO_848xx_TOP_CFG_SCRATCH_REG27)
|
||||
#define MDIO_848xx_CMD_HDLR_DATA2 (MDIO_848xx_TOP_CFG_SCRATCH_REG28)
|
||||
#define MDIO_848xx_CMD_HDLR_DATA3 (MDIO_848xx_TOP_CFG_SCRATCH_REG29)
|
||||
#define MDIO_848xx_CMD_HDLR_DATA4 (MDIO_848xx_TOP_CFG_SCRATCH_REG30)
|
||||
#define MDIO_848xx_CMD_HDLR_DATA5 (MDIO_848xx_TOP_CFG_SCRATCH_REG31)
|
||||
|
||||
/* Mailbox command set used by 84833. */
|
||||
#define PHY84833_CMD_SET_PAIR_SWAP 0x8001
|
||||
#define PHY84833_CMD_GET_EEE_MODE 0x8008
|
||||
#define PHY84833_CMD_SET_EEE_MODE 0x8009
|
||||
/* Mailbox status set used by 84833. */
|
||||
/* Mailbox command set used by 84833/84858 */
|
||||
#define PHY848xx_CMD_SET_PAIR_SWAP 0x8001
|
||||
#define PHY848xx_CMD_GET_EEE_MODE 0x8008
|
||||
#define PHY848xx_CMD_SET_EEE_MODE 0x8009
|
||||
/* Mailbox status set used by 84833 only */
|
||||
#define PHY84833_STATUS_CMD_RECEIVED 0x0001
|
||||
#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
|
||||
#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
|
||||
|
|
@ -7318,6 +7338,13 @@ Theotherbitsarereservedandshouldbezero*/
|
|||
#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
|
||||
#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
|
||||
|
||||
/* Mailbox status set used by 84858 only */
|
||||
#define PHY84858_STATUS_CMD_RECEIVED 0x0001
|
||||
#define PHY84858_STATUS_CMD_IN_PROGRESS 0x0002
|
||||
#define PHY84858_STATUS_CMD_COMPLETE_PASS 0x0004
|
||||
#define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x0008
|
||||
#define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb
|
||||
|
||||
|
||||
/* Warpcore clause 45 addressing */
|
||||
#define MDIO_WC_DEVAD 0x3
|
||||
|
|
|
|||
|
|
@ -1,15 +1,17 @@
|
|||
/* bnx2x_sp.c: Broadcom Everest network driver.
|
||||
/* bnx2x_sp.c: Qlogic Everest network driver.
|
||||
*
|
||||
* Copyright (c) 2011-2013 Broadcom Corporation
|
||||
* Copyright 2011-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* Unless you and Qlogic execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available
|
||||
* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
|
||||
* at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* software in any way with any other Qlogic software provided under a
|
||||
* license other than the GPL, without Qlogic's express prior written
|
||||
* consent.
|
||||
*
|
||||
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
|
||||
|
|
@ -4060,8 +4062,14 @@ static int bnx2x_setup_rss(struct bnx2x *bp,
|
|||
if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags))
|
||||
caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
|
||||
|
||||
if (test_bit(BNX2X_RSS_GRE_INNER_HDRS, &p->rss_flags))
|
||||
caps |= ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY;
|
||||
if (test_bit(BNX2X_RSS_IPV4_VXLAN, &p->rss_flags))
|
||||
caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY;
|
||||
|
||||
if (test_bit(BNX2X_RSS_IPV6_VXLAN, &p->rss_flags))
|
||||
caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY;
|
||||
|
||||
if (test_bit(BNX2X_RSS_TUNN_INNER_HDRS, &p->rss_flags))
|
||||
caps |= ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY;
|
||||
|
||||
/* RSS keys */
|
||||
if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) {
|
||||
|
|
@ -5669,10 +5677,14 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp,
|
|||
rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag);
|
||||
rdata->path_id = BP_PATH(bp);
|
||||
rdata->network_cos_mode = start_params->network_cos_mode;
|
||||
rdata->tunnel_mode = start_params->tunnel_mode;
|
||||
rdata->gre_tunnel_type = start_params->gre_tunnel_type;
|
||||
rdata->inner_gre_rss_en = start_params->inner_gre_rss_en;
|
||||
rdata->vxlan_dst_port = cpu_to_le16(4789);
|
||||
|
||||
rdata->vxlan_dst_port = cpu_to_le16(start_params->vxlan_dst_port);
|
||||
rdata->geneve_dst_port = cpu_to_le16(start_params->geneve_dst_port);
|
||||
rdata->inner_clss_l2gre = start_params->inner_clss_l2gre;
|
||||
rdata->inner_clss_l2geneve = start_params->inner_clss_l2geneve;
|
||||
rdata->inner_clss_vxlan = start_params->inner_clss_vxlan;
|
||||
rdata->inner_rss = start_params->inner_rss;
|
||||
|
||||
rdata->sd_accept_mf_clss_fail = start_params->class_fail;
|
||||
if (start_params->class_fail_ethtype) {
|
||||
rdata->sd_accept_mf_clss_fail_match_ethtype = 1;
|
||||
|
|
@ -5690,6 +5702,14 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp,
|
|||
cpu_to_le16(0x8100);
|
||||
|
||||
rdata->no_added_tags = start_params->no_added_tags;
|
||||
|
||||
rdata->c2s_pri_tt_valid = start_params->c2s_pri_valid;
|
||||
if (rdata->c2s_pri_tt_valid) {
|
||||
memcpy(rdata->c2s_pri_trans_table.val,
|
||||
start_params->c2s_pri,
|
||||
MAX_VLAN_PRIORITIES);
|
||||
rdata->c2s_pri_default = start_params->c2s_pri_default;
|
||||
}
|
||||
/* No need for an explicit memory barrier here as long we would
|
||||
* need to ensure the ordering of writing to the SPQ element
|
||||
* and updating of the SPQ producer which involves a memory
|
||||
|
|
@ -5750,15 +5770,22 @@ static inline int bnx2x_func_send_switch_update(struct bnx2x *bp,
|
|||
if (test_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
|
||||
&switch_update_params->changes)) {
|
||||
rdata->update_tunn_cfg_flg = 1;
|
||||
if (test_bit(BNX2X_F_UPDATE_TUNNEL_CLSS_EN,
|
||||
if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
|
||||
&switch_update_params->changes))
|
||||
rdata->tunn_clss_en = 1;
|
||||
if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_GRE_RSS_EN,
|
||||
rdata->inner_clss_l2gre = 1;
|
||||
if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
|
||||
&switch_update_params->changes))
|
||||
rdata->inner_gre_rss_en = 1;
|
||||
rdata->tunnel_mode = switch_update_params->tunnel_mode;
|
||||
rdata->gre_tunnel_type = switch_update_params->gre_tunnel_type;
|
||||
rdata->vxlan_dst_port = cpu_to_le16(4789);
|
||||
rdata->inner_clss_vxlan = 1;
|
||||
if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
|
||||
&switch_update_params->changes))
|
||||
rdata->inner_clss_l2geneve = 1;
|
||||
if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
|
||||
&switch_update_params->changes))
|
||||
rdata->inner_rss = 1;
|
||||
rdata->vxlan_dst_port =
|
||||
cpu_to_le16(switch_update_params->vxlan_dst_port);
|
||||
rdata->geneve_dst_port =
|
||||
cpu_to_le16(switch_update_params->geneve_dst_port);
|
||||
}
|
||||
|
||||
rdata->echo = SWITCH_UPDATE;
|
||||
|
|
@ -5885,6 +5912,8 @@ static inline int bnx2x_func_send_tx_start(struct bnx2x *bp,
|
|||
rdata->traffic_type_to_priority_cos[i] =
|
||||
tx_start_params->traffic_type_to_priority_cos[i];
|
||||
|
||||
for (i = 0; i < MAX_TRAFFIC_TYPES; i++)
|
||||
rdata->dcb_outer_pri[i] = tx_start_params->dcb_outer_pri[i];
|
||||
/* No need for an explicit memory barrier here as long as we
|
||||
* ensure the ordering of writing to the SPQ element
|
||||
* and updating of the SPQ producer which involves a memory
|
||||
|
|
|
|||
|
|
@ -1,15 +1,17 @@
|
|||
/* bnx2x_sp.h: Broadcom Everest network driver.
|
||||
/* bnx2x_sp.h: Qlogic Everest network driver.
|
||||
*
|
||||
* Copyright (c) 2011-2013 Broadcom Corporation
|
||||
* Copyright 2011-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* Unless you and Qlogic execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available
|
||||
* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
|
||||
* at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* software in any way with any other Qlogic software provided under a
|
||||
* license other than the GPL, without Qlogic's express prior written
|
||||
* consent.
|
||||
*
|
||||
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
|
||||
|
|
@ -711,7 +713,10 @@ enum {
|
|||
BNX2X_RSS_IPV6,
|
||||
BNX2X_RSS_IPV6_TCP,
|
||||
BNX2X_RSS_IPV6_UDP,
|
||||
BNX2X_RSS_GRE_INNER_HDRS,
|
||||
|
||||
BNX2X_RSS_IPV4_VXLAN,
|
||||
BNX2X_RSS_IPV6_VXLAN,
|
||||
BNX2X_RSS_TUNN_INNER_HDRS,
|
||||
};
|
||||
|
||||
struct bnx2x_config_rss_params {
|
||||
|
|
@ -1105,8 +1110,10 @@ enum {
|
|||
BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
|
||||
BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
|
||||
BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
|
||||
BNX2X_F_UPDATE_TUNNEL_CLSS_EN,
|
||||
BNX2X_F_UPDATE_TUNNEL_INNER_GRE_RSS_EN,
|
||||
BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
|
||||
BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
|
||||
BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
|
||||
BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
|
||||
};
|
||||
|
||||
/* Allowed Function states */
|
||||
|
|
@ -1171,19 +1178,23 @@ struct bnx2x_func_start_params {
|
|||
/* Function cos mode */
|
||||
u8 network_cos_mode;
|
||||
|
||||
/* TUNN_MODE_NONE/TUNN_MODE_VXLAN/TUNN_MODE_GRE */
|
||||
u8 tunnel_mode;
|
||||
/* UDP dest port for VXLAN */
|
||||
u16 vxlan_dst_port;
|
||||
|
||||
/* tunneling classification enablement */
|
||||
u8 tunn_clss_en;
|
||||
/* UDP dest port for Geneve */
|
||||
u16 geneve_dst_port;
|
||||
|
||||
/* NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
|
||||
u8 gre_tunnel_type;
|
||||
/* Enable inner Rx classifications for L2GRE packets */
|
||||
u8 inner_clss_l2gre;
|
||||
|
||||
/* Enables Inner GRE RSS on the function, depends on the client RSS
|
||||
* capailities
|
||||
*/
|
||||
u8 inner_gre_rss_en;
|
||||
/* Enable inner Rx classifications for L2-Geneve packets */
|
||||
u8 inner_clss_l2geneve;
|
||||
|
||||
/* Enable inner Rx classification for vxlan packets */
|
||||
u8 inner_clss_vxlan;
|
||||
|
||||
/* Enable RSS according to inner header */
|
||||
u8 inner_rss;
|
||||
|
||||
/* Allows accepting of packets failing MF classification, possibly
|
||||
* only matching a given ethertype
|
||||
|
|
@ -1200,6 +1211,11 @@ struct bnx2x_func_start_params {
|
|||
|
||||
/* Prevent inner vlans from being added by FW */
|
||||
u8 no_added_tags;
|
||||
|
||||
/* Inner-to-Outer vlan priority mapping */
|
||||
u8 c2s_pri[MAX_VLAN_PRIORITIES];
|
||||
u8 c2s_pri_default;
|
||||
u8 c2s_pri_valid;
|
||||
};
|
||||
|
||||
struct bnx2x_func_switch_update_params {
|
||||
|
|
@ -1207,8 +1223,8 @@ struct bnx2x_func_switch_update_params {
|
|||
u16 vlan;
|
||||
u16 vlan_eth_type;
|
||||
u8 vlan_force_prio;
|
||||
u8 tunnel_mode;
|
||||
u8 gre_tunnel_type;
|
||||
u16 vxlan_dst_port;
|
||||
u16 geneve_dst_port;
|
||||
};
|
||||
|
||||
struct bnx2x_func_afex_update_params {
|
||||
|
|
@ -1229,6 +1245,7 @@ struct bnx2x_func_tx_start_params {
|
|||
u8 dcb_enabled;
|
||||
u8 dcb_version;
|
||||
u8 dont_add_pri_0_en;
|
||||
u8 dcb_outer_pri[MAX_TRAFFIC_TYPES];
|
||||
};
|
||||
|
||||
struct bnx2x_func_set_timesync_params {
|
||||
|
|
|
|||
|
|
@ -1,15 +1,17 @@
|
|||
/* bnx2x_sriov.c: Broadcom Everest network driver.
|
||||
/* bnx2x_sriov.c: QLogic Everest network driver.
|
||||
*
|
||||
* Copyright 2009-2013 Broadcom Corporation
|
||||
* Copyright 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* Unless you and QLogic execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available
|
||||
* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* software in any way with any other QLogic software provided under a
|
||||
* license other than the GPL, without QLogic's express prior written
|
||||
* consent.
|
||||
*
|
||||
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
|
||||
|
|
@ -1338,6 +1340,9 @@ int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param,
|
|||
|
||||
mutex_init(&bp->vfdb->bulletin_mutex);
|
||||
|
||||
if (SHMEM2_HAS(bp, sriov_switch_mode))
|
||||
SHMEM2_WR(bp, sriov_switch_mode, SRIOV_SWITCH_MODE_VEB);
|
||||
|
||||
return 0;
|
||||
failed:
|
||||
DP(BNX2X_MSG_IOV, "Failed err=%d\n", err);
|
||||
|
|
|
|||
|
|
@ -1,15 +1,17 @@
|
|||
/* bnx2x_sriov.h: Broadcom Everest network driver.
|
||||
/* bnx2x_sriov.h: QLogic Everest network driver.
|
||||
*
|
||||
* Copyright 2009-2013 Broadcom Corporation
|
||||
* Copyright 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* Unless you and QLogic execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available
|
||||
* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* software in any way with any other QLogic software provided under a
|
||||
* license other than the GPL, without QLogic's express prior written
|
||||
* consent.
|
||||
*
|
||||
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/* bnx2x_stats.c: Broadcom Everest network driver.
|
||||
/* bnx2x_stats.c: QLogic Everest network driver.
|
||||
*
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/* bnx2x_stats.h: Broadcom Everest network driver.
|
||||
/* bnx2x_stats.h: QLogic Everest network driver.
|
||||
*
|
||||
* Copyright (c) 2007-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
|
|||
|
|
@ -1,15 +1,17 @@
|
|||
/* bnx2x_vfpf.c: Broadcom Everest network driver.
|
||||
/* bnx2x_vfpf.c: QLogic Everest network driver.
|
||||
*
|
||||
* Copyright 2009-2013 Broadcom Corporation
|
||||
* Copyright 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* Unless you and QLogic execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available
|
||||
* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* software in any way with any other QLogic software provided under a
|
||||
* license other than the GPL, without QLogic's express prior written
|
||||
* consent.
|
||||
*
|
||||
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
|
||||
|
|
|
|||
|
|
@ -1,16 +1,22 @@
|
|||
/* bnx2x_vfpf.h: Broadcom Everest network driver.
|
||||
/* bnx2x_vfpf.h: Qlogic Everest network driver.
|
||||
*
|
||||
* Copyright (c) 2011-2013 Broadcom Corporation
|
||||
* Copyright (c) 2014 QLogic Corporation
|
||||
* All rights reserved
|
||||
*
|
||||
* Unless you and Broadcom execute a separate written software license
|
||||
* Unless you and Qlogic execute a separate written software license
|
||||
* agreement governing use of this software, this software is licensed to you
|
||||
* under the terms of the GNU General Public License version 2, available
|
||||
* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
|
||||
* under the terms of the GNU General Public License version 2 (the “GPL”),
|
||||
* available at http://www.gnu.org/licenses/gpl-2.0.html, with the following
|
||||
* added to such license:
|
||||
*
|
||||
* Notwithstanding the above, under no circumstances may you combine this
|
||||
* software in any way with any other Broadcom software provided under a
|
||||
* license other than the GPL, without Broadcom's express prior written
|
||||
* consent.
|
||||
* As a special exception, the copyright holders of this software give you
|
||||
* permission to link this software with independent modules, and to copy and
|
||||
* distribute the resulting executable under terms of your choice, provided that
|
||||
* you also meet, for each linked independent module, the terms and conditions
|
||||
* of the license of that module. An independent module is a module which is
|
||||
* not derived from this software. The special exception does not apply to any
|
||||
* modifications of the software.
|
||||
*
|
||||
* Maintained by: Ariel Elior <ariel.elior@qlogic.com>
|
||||
* Written by: Ariel Elior <ariel.elior@qlogic.com>
|
||||
|
|
|
|||
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