staging: spmi: add Hikey 970 SPMI controller driver
Add the SPMI controller code required to use the Kirin 970 SPMI bus. [mchehab+huawei@kernel.org: added just the SPMI controller on this patch] The complete patch is at: https://github.com/96boards-hikey/linux/commit/08464419fba2 Signed-off-by: Mayulong <mayulong1@huawei.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/b4810f476e41e7de4efdf28b42472ae4ffe7defe.1597647359.git.mchehab+huawei@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mayulong
Greg Kroah-Hartman
Родитель
217b97f69e
Коммит
70f59c90c8
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@ -0,0 +1,390 @@
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/seq_file.h>
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#include <linux/spmi.h>
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#include <linux/spmi.h>
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#define SPMI_CONTROLLER_NAME "spmi_controller"
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/*
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* SPMI register addr
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*/
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#define SPMI_CHANNEL_OFFSET 0x0300
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#define SPMI_SLAVE_OFFSET 0x20
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#define SPMI_APB_SPMI_CMD_BASE_ADDR 0x0100
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/*lint -e750 -esym(750,*)*/
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#define SPMI_APB_SPMI_WDATA0_BASE_ADDR 0x0104
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#define SPMI_APB_SPMI_WDATA1_BASE_ADDR 0x0108
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#define SPMI_APB_SPMI_WDATA2_BASE_ADDR 0x010c
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#define SPMI_APB_SPMI_WDATA3_BASE_ADDR 0x0110
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#define SPMI_APB_SPMI_STATUS_BASE_ADDR 0x0200
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#define SPMI_APB_SPMI_RDATA0_BASE_ADDR 0x0204
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#define SPMI_APB_SPMI_RDATA1_BASE_ADDR 0x0208
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#define SPMI_APB_SPMI_RDATA2_BASE_ADDR 0x020c
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#define SPMI_APB_SPMI_RDATA3_BASE_ADDR 0x0210
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/*lint +e750 -esym(750,*)*/
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#define SPMI_PER_DATAREG_BYTE 4
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/*
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* SPMI cmd register
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*/
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#define SPMI_APB_SPMI_CMD_EN (1 << 31)
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#define SPMI_APB_SPMI_CMD_TYPE_OFFSET 24
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#define SPMI_APB_SPMI_CMD_LENGTH_OFFSET 20
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#define SPMI_APB_SPMI_CMD_SLAVEID_OFFSET 16
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#define SPMI_APB_SPMI_CMD_ADDR_OFFSET 0
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#define Tranverse32(X) ((((u32)(X) & 0xff000000) >> 24) | \
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(((u32)(X) & 0x00ff0000) >> 8) | \
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(((u32)(X) & 0x0000ff00) << 8) | \
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(((u32)(X) & 0x000000ff) << 24))
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/* Command Opcodes */
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/*lint -e749 -esym(749,*)*/
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enum spmi_controller_cmd_op_code {
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SPMI_CMD_REG_ZERO_WRITE = 0,
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SPMI_CMD_REG_WRITE = 1,
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SPMI_CMD_REG_READ = 2,
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SPMI_CMD_EXT_REG_WRITE = 3,
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SPMI_CMD_EXT_REG_READ = 4,
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SPMI_CMD_EXT_REG_WRITE_L = 5,
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SPMI_CMD_EXT_REG_READ_L = 6,
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SPMI_CMD_REG_RESET = 7,
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SPMI_CMD_REG_SLEEP = 8,
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SPMI_CMD_REG_SHUTDOWN = 9,
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SPMI_CMD_REG_WAKEUP = 10,
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};
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/*lint +e749 -esym(749,*)*/
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/*
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* SPMI status register
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*/
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#define SPMI_APB_TRANS_DONE (1 << 0)
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#define SPMI_APB_TRANS_FAIL (1 << 2)
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/* Command register fields */
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#define SPMI_CONTROLLER_CMD_MAX_BYTE_COUNT 16
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/* Maximum number of support PMIC peripherals */
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#define SPMI_CONTROLLER_TIMEOUT_US 1000
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#define SPMI_CONTROLLER_MAX_TRANS_BYTES (16)
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#define SPMI_WRITEL( dev, reg, addr ) \
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do { \
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writel( ( reg ), ( addr ) ); \
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} while (0)
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#define SPMI_READL( dev, reg, addr ) \
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do { \
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reg = readl( addr ); \
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} while (0)
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/*
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* @base base address of the PMIC Arbiter core registers.
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* @rdbase, @wrbase base address of the PMIC Arbiter read core registers.
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* For HW-v1 these are equal to base.
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* For HW-v2, the value is the same in eeraly probing, in order to read
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* PMIC_ARB_CORE registers, then chnls, and obsrvr are set to
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* PMIC_ARB_CORE_REGISTERS and PMIC_ARB_CORE_REGISTERS_OBS respectivly.
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* @intr base address of the SPMI interrupt control registers
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* @ppid_2_chnl_tbl lookup table f(SID, Periph-ID) -> channel num
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* entry is only valid if corresponding bit is set in valid_ppid_bitmap.
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* @valid_ppid_bitmap bit is set only for valid ppids.
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* @fmt_cmd formats a command to be set into PMIC_ARBq_CHNLn_CMD
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* @chnl_ofst calculates offset of the base of a channel reg space
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* @ee execution environment id
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* @irq_acc0_init_val initial value of the interrupt accumulator at probe time.
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* Use for an HW workaround. On handling interrupts, the first accumulator
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* register will be compared against this value, and bits which are set at
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* boot will be ignored.
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* @reserved_chnl entry of ppid_2_chnl_tbl that this driver should never touch.
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* value is positive channel number or negative to mark it unused.
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*/
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struct spmi_controller_dev {
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struct spmi_controller *controller;
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struct device *dev;
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void __iomem *base;
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spinlock_t lock;
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u32 channel;
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};
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static int spmi_controller_wait_for_done(struct spmi_controller_dev *ctrl_dev,
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void __iomem *base, u8 sid, u16 addr)
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{
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u32 status = 0;
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u32 timeout = SPMI_CONTROLLER_TIMEOUT_US;
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u32 offset = SPMI_APB_SPMI_STATUS_BASE_ADDR + SPMI_CHANNEL_OFFSET * ctrl_dev->channel
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+ SPMI_SLAVE_OFFSET * sid;
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while (timeout--) {
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SPMI_READL(ctrl_dev->dev, status, base + offset);/*lint !e732 */
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if (status & SPMI_APB_TRANS_DONE) {
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if (status & SPMI_APB_TRANS_FAIL) {
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dev_err(ctrl_dev->dev,
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"%s: transaction failed (0x%x)\n",
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__func__, status);
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return -EIO;
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}
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return 0;
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}
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udelay(1);/*lint !e778 !e774 !e747*/
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}
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dev_err(ctrl_dev->dev,
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"%s: timeout, status 0x%x\n",
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__func__, status);
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return -ETIMEDOUT;/*lint !e438*/
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}/*lint !e715 !e529*/
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static int spmi_read_cmd(struct spmi_controller *ctrl,
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u8 opc, u8 sid, u16 addr, u8 *buf, size_t bc)
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{
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struct spmi_controller_dev *spmi_controller = dev_get_drvdata(&ctrl->dev);
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unsigned long flags;
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u32 cmd, data;
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int rc;
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u32 chnl_ofst = SPMI_CHANNEL_OFFSET*spmi_controller->channel;
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u8 op_code, i;
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if (bc > SPMI_CONTROLLER_MAX_TRANS_BYTES) {
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dev_err(spmi_controller->dev
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, "spmi_controller supports 1..%d bytes per trans, but:%ld requested"
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, SPMI_CONTROLLER_MAX_TRANS_BYTES, bc);
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return -EINVAL;
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}
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/* Check the opcode */
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if (SPMI_CMD_READ == opc)
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op_code = SPMI_CMD_REG_READ;
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else if (SPMI_CMD_EXT_READ == opc)
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op_code = SPMI_CMD_EXT_REG_READ;
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else if (SPMI_CMD_EXT_READL == opc)
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op_code = SPMI_CMD_EXT_REG_READ_L;
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else {
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dev_err(spmi_controller->dev, "invalid read cmd 0x%x", opc);
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return -EINVAL;
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}
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cmd = SPMI_APB_SPMI_CMD_EN |/*lint !e648 !e701 */ /* cmd_en */
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(op_code << SPMI_APB_SPMI_CMD_TYPE_OFFSET) |/*lint !e648 !e701 */ /* cmd_type */
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((bc-1) << SPMI_APB_SPMI_CMD_LENGTH_OFFSET) |/*lint !e648 !e701 */ /* byte_cnt */
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((sid & 0xf) << SPMI_APB_SPMI_CMD_SLAVEID_OFFSET) | /* slvid */
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((addr & 0xffff) << SPMI_APB_SPMI_CMD_ADDR_OFFSET); /* slave_addr */
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spin_lock_irqsave(&spmi_controller->lock, flags);/*lint !e550 */
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SPMI_WRITEL(spmi_controller->dev, cmd, spmi_controller->base + chnl_ofst + SPMI_APB_SPMI_CMD_BASE_ADDR);
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rc = spmi_controller_wait_for_done(spmi_controller, spmi_controller->base, sid, addr);
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if (rc)
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goto done;
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i = 0;
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do {
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SPMI_READL(spmi_controller->dev, data, spmi_controller->base + chnl_ofst + SPMI_SLAVE_OFFSET*sid + SPMI_APB_SPMI_RDATA0_BASE_ADDR + i*SPMI_PER_DATAREG_BYTE);/*lint !e732 */
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data = Tranverse32(data);
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if ((bc - i*SPMI_PER_DATAREG_BYTE ) >> 2) {/*lint !e702 */
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memcpy(buf, &data, sizeof(data));
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buf += sizeof(data);
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} else {
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memcpy(buf, &data, bc%SPMI_PER_DATAREG_BYTE);/*lint !e747 */
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buf += (bc%SPMI_PER_DATAREG_BYTE);
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}
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i++;
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} while (bc > i*SPMI_PER_DATAREG_BYTE);
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done:
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spin_unlock_irqrestore(&spmi_controller->lock, flags);
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if (rc)
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dev_err(spmi_controller->dev, "spmi read wait timeout op:0x%x sid:%d addr:0x%x bc:%ld\n",
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opc, sid, addr, bc + 1);
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return rc;
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}/*lint !e550 !e529*/
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/*lint -e438 -esym(438,*)*/
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static int spmi_write_cmd(struct spmi_controller *ctrl,
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u8 opc, u8 sid, u16 addr, const u8 *buf, size_t bc)
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{
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struct spmi_controller_dev *spmi_controller = dev_get_drvdata(&ctrl->dev);
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unsigned long flags;
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u32 cmd;
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u32 data = 0;
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int rc;
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u32 chnl_ofst = SPMI_CHANNEL_OFFSET*spmi_controller->channel;
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u8 op_code, i;
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if (bc > SPMI_CONTROLLER_MAX_TRANS_BYTES) {
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dev_err(spmi_controller->dev
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, "spmi_controller supports 1..%d bytes per trans, but:%ld requested"
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, SPMI_CONTROLLER_MAX_TRANS_BYTES, bc);
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return -EINVAL;
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}
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/* Check the opcode */
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if (SPMI_CMD_WRITE == opc)
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op_code = SPMI_CMD_REG_WRITE;
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else if (SPMI_CMD_EXT_WRITE == opc)
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op_code = SPMI_CMD_EXT_REG_WRITE;
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else if (SPMI_CMD_EXT_WRITEL == opc)
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op_code = SPMI_CMD_EXT_REG_WRITE_L;
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else {
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dev_err(spmi_controller->dev, "invalid write cmd 0x%x", opc);
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return -EINVAL;
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}
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cmd = SPMI_APB_SPMI_CMD_EN |/*lint !e648 !e701 */ /* cmd_en */
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(op_code << SPMI_APB_SPMI_CMD_TYPE_OFFSET) |/*lint !e648 !e701 */ /* cmd_type */
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((bc-1) << SPMI_APB_SPMI_CMD_LENGTH_OFFSET) |/*lint !e648 !e701 */ /* byte_cnt */
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((sid & 0xf) << SPMI_APB_SPMI_CMD_SLAVEID_OFFSET) | /* slvid */
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((addr & 0xffff) << SPMI_APB_SPMI_CMD_ADDR_OFFSET); /* slave_addr */
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/* Write data to FIFOs */
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spin_lock_irqsave(&spmi_controller->lock, flags);/*lint !e550 */
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i = 0;
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do {
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memset(&data, 0, sizeof(data));
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if ((bc - i*SPMI_PER_DATAREG_BYTE ) >> 2) {/*lint !e702 */
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memcpy(&data, buf, sizeof(data));
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buf +=sizeof(data);
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} else {
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memcpy(&data, buf, bc%SPMI_PER_DATAREG_BYTE);/*lint !e747 */
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buf +=(bc%SPMI_PER_DATAREG_BYTE);
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}
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data = Tranverse32(data);
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SPMI_WRITEL(spmi_controller->dev, data, spmi_controller->base + chnl_ofst + SPMI_APB_SPMI_WDATA0_BASE_ADDR+SPMI_PER_DATAREG_BYTE*i);
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i++;
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} while (bc > i*SPMI_PER_DATAREG_BYTE);
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/* Start the transaction */
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SPMI_WRITEL(spmi_controller->dev, cmd, spmi_controller->base + chnl_ofst + SPMI_APB_SPMI_CMD_BASE_ADDR);
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rc = spmi_controller_wait_for_done(spmi_controller, spmi_controller->base, sid, addr);
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spin_unlock_irqrestore(&spmi_controller->lock, flags);
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if (rc)
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dev_err(spmi_controller->dev, "spmi write wait timeout op:0x%x sid:%d addr:0x%x bc:%ld\n",
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opc, sid, addr, bc);
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return rc;
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}/*lint !e438 !e550 !e529*/
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/*lint +e438 -esym(438,*)*/
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static int spmi_controller_probe(struct platform_device *pdev)
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{
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struct spmi_controller_dev *spmi_controller;
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struct spmi_controller *ctrl;
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struct resource *iores;
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int ret = 0;
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printk(KERN_INFO "HISI SPMI probe\n");
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ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*spmi_controller));
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if (!ctrl) {
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dev_err(&pdev->dev, "can not allocate spmi_controller data\n");
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return -ENOMEM; /*lint !e429*/
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}
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spmi_controller = spmi_controller_get_drvdata(ctrl);
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spmi_controller->controller = ctrl;
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/* NOTE: driver uses the static register mapping */
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iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!iores) {
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dev_err(&pdev->dev, "can not get resource! \n");
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return -EINVAL; /*lint !e429*/
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}
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spmi_controller->base = ioremap(iores->start, resource_size(iores));
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if (!spmi_controller->base) {
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dev_err(&pdev->dev, "can not remap base addr! \n");
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return -EADDRNOTAVAIL; /*lint !e429*/
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}
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dev_dbg(&pdev->dev, "spmi_add_controller base addr=0x%lx!\n", (long unsigned int)spmi_controller->base);/*lint !e774*/
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/* Get properties from the device tree */
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ret = of_property_read_u32(pdev->dev.of_node, "spmi-channel",
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&spmi_controller->channel);/*lint !e838*/
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if (ret) {
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dev_err(&pdev->dev, "can not get chanel \n");
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return -ENODEV; /*lint !e429*/
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}
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platform_set_drvdata(pdev, spmi_controller);
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dev_set_drvdata(&ctrl->dev, spmi_controller);
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spin_lock_init(&spmi_controller->lock);
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ctrl->nr = spmi_controller->channel;
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ctrl->dev.parent = pdev->dev.parent;
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ctrl->dev.of_node = of_node_get(pdev->dev.of_node);
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/* Callbacks */
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ctrl->read_cmd = spmi_read_cmd;
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ctrl->write_cmd = spmi_write_cmd;
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ret = spmi_controller_add(ctrl);
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if (ret) {
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dev_err(&pdev->dev, "spmi_add_controller failed!\n");
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goto err_add_controller;
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}
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err_add_controller:
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platform_set_drvdata(pdev, NULL);
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return ret; /*lint !e429*/
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}
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static int spmi_del_controller(struct platform_device *pdev)
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{
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struct spmi_controller *ctrl = platform_get_drvdata(pdev);
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platform_set_drvdata(pdev, NULL);
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spmi_controller_remove(ctrl);
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return 0;
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}
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static struct of_device_id spmi_controller_match_table[] = {
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{ .compatible = "hisilicon,spmi-controller",
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},/*lint !e785*/
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{}/*lint !e785*/
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};
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static struct platform_driver spmi_controller_driver = {
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.probe = spmi_controller_probe,
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.remove = spmi_del_controller,
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.driver = {
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.name = SPMI_CONTROLLER_NAME,
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.owner = THIS_MODULE,/*lint !e64*/
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.of_match_table = spmi_controller_match_table,
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},/*lint !e785*/
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};/*lint !e785*/
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/*lint -e528 -esym(528,*)*/
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static int __init spmi_controller_init(void)
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{
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return platform_driver_register(&spmi_controller_driver);/*lint !e64*/
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}
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postcore_initcall(spmi_controller_init);
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static void __exit spmi_controller_exit(void)
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{
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platform_driver_unregister(&spmi_controller_driver);
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}
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module_exit(spmi_controller_exit);
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/*lint -e753 -esym(753,*)*/
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MODULE_LICENSE("GPL v2");
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MODULE_VERSION("1.0");/*lint !e785 !e64 !e528*/
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MODULE_ALIAS("platform:spmi_controlller");
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/*lint -e753 +esym(753,*)*/
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/*lint -e528 +esym(528,*)*/
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